Make the same output as for v3.2 and 3.3 for idf_size.py --archives /path/to/file.map
and also for idf_size.py --archive_details libhap_min.a
/path/to/file.map
Closes: TW28774
The bug will cause memory corrupted (the largest range is from 0x3ffc0000 ~ 0x3ffc8000),
some strange error will happen, like IllegalInstruction, LoadProhibited and .etc.
Fix following WiFi bugs:
1. Fix a crash bug which is caused by WiFi static TX buffer alloc/free.
2. Fix the bug that iphone fails to connect to ESP32 AP by enabling AP BAR receiving.
3. Fix the bug that ESP32 station fails to connect some APs, such as Xiaomi hotspot etc,
after reset.
This commit adds the ability for backtracing to trace from the itnerrupt to the
task stack, and across nested interrupts. Test cases have also been added.
See merge request !4084
Note: "Test backtrace from abort" reset reason modified by removing abort as a reason.
esp32: update libphy.a to fix interrupt watchdog when WiFi and BT run at the same time and both enable modem sleep (backport v3.1)
See merge request idf/esp-idf!4193
Shortcircuit evaluation may cause skip of _mdns_strdup_check of any further question field, which after clear_rx_packet freed undefined memory.
Fixes https://ezredmine.espressif.cn:8765/issues/28465
Originally, when doing BLE active scan, Bluedroid will not report adv to
application layer until receive scan response. This option is used to
disable the behavior. When enable this option, Bluedroid will report
adv data or scan response to application layer immediately.
Previously, hardware SHA engine "locks" were mutex semaphores. This meant that the task which
started a particular SHA session (in hardware) needed to finalise that session, or an invalid
FreeRTOS state was created.
Replace with binary semaphore which can be shared between tasks.
Includes a unit test, but unit test doesn't crash even without this fix
(some other unknown condition is required).
Bootloader used to calculate the number of cache pages assuming that
load address was aligned, while in reality load address for DROM and
IROM was offset by 0x20 bytes from the start of 64kB page. This
caused the bootloader to map one less page if the size of the image
was 0x4..0x1c less than a multiple of 64kB.
Reported in https://esp32.com/viewtopic.php?f=13&t=6952.
In some cases, linker could choose to use ROM functions instead of the
ones defined in IDF.
For functions used in ROM stub table, this would lead to infinite
recursion when the corresponding function was called from ROM.
For crypto functions, some of these were modified in IDF, and
incompatible with ROM counterparts.
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
Due to a hardware limitation in ESP32, the first four bytes of some
CSI data is invalid, not the last four bytes.
Correct a mistake of CSI sub-carrier index in documentation.
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496
1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
I am stealing this delay coding from @jeremyherbert #2493 pr.
2. Change Bus Reset to handle interrupted READ sequences.
The current code does not handle interrupted READ cycles.
If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.
The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.
So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
3. fix typo
correct `sda_id` to `sda_io` in `i2c_master_clear_bus()` @ryan-ma found it. This typo was generated when I manually edited this patch on GitHub, I should have done a Copy/Paste operation!
