Merge branch 'test/reboot_between_unit_test_cases' into 'release/v2.0'
CI: add reset between running each unit test cases
Unit test is designed to detect bug **within** each test case. Therefore we'll reset between each case to provide a clean context. We will later add stress cases to run unit test cases together to detect potential bugs.
See merge request !636
See merge request !642
CI: add reset between running each unit test cases
Unit test is designed to detect bug **within** each test case. Therefore we'll reset between each case to provide a clean context. We will later add stress cases to run unit test cases together to detect potential bugs.
See merge request !636
CI: check if commit history need revise
Usually we need to cleanup the commit history before MR merged. Sometime we forget to squash before merge.
We can add certain pattern at the beginning of commit message, and add a job in deploy stage to check the patterns.
When we want to push code for review or resolve review comments, we can add this pattern to commit message as a reminder.
This will not block CI tests, checking job will always be put in the last CI stage.
See merge request !629
esp32: initialize cross-core interrupt in single core mode
The software interrupt originally used as the cross-core interrupt is
now also used to yield from a FreeRTOS critical section; therefore it
must be initialized for single core mode as well.
Fixes https://github.com/espressif/esp-idf/issues/496
See merge request !640
fix warnings generated by ESP_ERROR_CHECK(variable) in release builds
This uses the same pattern as “assert” in release builds to silence the
warning. At the same time, we make sure that if a statement is wrapped
into ESP_ERROR_CHECK, it is executed in release build as well.
Fixes https://github.com/espressif/esp-idf/issues/497
See merge request !641
You can set esp32 as AP/STA, client/sever, sender/recever in menuconfig.
You can set whether to display delay time info in menuconfig.
Now you can transfer data between esp and esp.
This uses the same pattern as “assert” in release builds to silence the
warning. At the same time, we make sure that if a statement is wrapped
into ESP_ERROR_CHECK, it is executed in release build as well.
The software interrupt originally used as the cross-core interrupt is
now also used to yield from a FreeRTOS critical section; therefore it
must be initialized for single core mode as well.
Fixes https://github.com/espressif/esp-idf/issues/496
esp32: RWDT is used to reboot system in case of panic handler crash
This branch uses RWDT to reboot system in case of panic handler crash.
See merge request !625
Feature/btdm uart hci
1. support UART HCI, devolper need not to make a bridge between VHCI and UART.
2. fix bug of rand/srand called in ISR.
3. fix bug of BLE rx packets may cause assert.
See merge request !626
component/bt : modify alarm APIs to be safely accessible from multiple tasks
Improve the osi_alarm module to make the alarm APIs become thread safe.
See merge request !570
1. support UART HCI, devolper need not to make a bridge between VHCI and UART.
2. fix bug of rand/srand called in ISR.
3. fix bug of BLE rx packets may cause assert.
lwip: implement lwip critical session with mutex
Currently lwip critical session is based on interrupt, now replace it with mutex
See merge request !595
spi_flash: fix race condition in s_flash_op_complete access
Flash operation complete flag was cleared by the CPU initiating flash operation. If the other core was running an ISR, then IPC task could be late to enter the loop to check `s_flash_op_complete` by the time next flash operation started. This would cause a deadlock, as the IPC task would still be waiting for `s_flash_op_complete` to be set (which was already cleared by the next flash operation), while the flash operation task would be blocked waiting for IPC task to set `s_flash_op_can_start`.
If the flag is cleared on the CPU waiting on this flag, then the race condition can not happen.
See merge request !615
Fix timing adjustment needed for higher speeds of SPI master bus.
Ref https://github.com/espressif/esp-idf/issues/363 . It was found out the master SPI driver didn't exactly calculate the delay compensation needed, breaking 20 and 26MHz full-duplex mode. This fixes these use cases. We also found out 40MHz full-duplex routed over the GPIO matrix does not work because of a hardware quirk; this MR adds a check/error for that case until we find a workaround.
See merge request !547
