Commit graph

4 commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
2b7681ec4f esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
2019-11-21 12:26:14 +08:00
Michael (XIAO Xufeng)
d3b54ec84a esp_flash: fix the coredump issue
During coredump, dangerous-area-checking should be disabled, and cache
disabling should be replaced by a safer version.

Dangerous-area-checking used to be in the HAL, but it seems to be more
fit to os functions. So it's moved to os functions. Interfaces are
provided to switch between os functions during coredump.
2019-09-18 14:30:23 +08:00
Michael (XIAO Xufeng)
a626b26cf9 esp_flash: improve the comments a bit 2019-08-20 14:05:35 +08:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00