2 commits

Author	SHA1	Message	Date
Marius Vikhammer	c63684cf6c	hw crypto: activated hardware acceleration for esp32s2beta ... Activated AES, RSA and SHA hardware acceleration for esp32s2 and enabled related unit tests. Updated with changes made for ESP32 from 0a04034, 961f59f and caea288. Added performance targets for esp32s2beta Closes IDF-757	2019-12-12 12:37:29 +08:00
Ivan Grokhotkov	589a1f216f	mbedtls: add SHA performance test ... Results with this revision: SHA256 rate 2.599MB/sec Debug 240MHz SW SHA256 rate 1.147MB/sec Release 80MHz SW SHA256 rate 3.469MB/sec Release 240MHz SW SHA256 rate 2.687MB/sec Release 240MHz SW + PSRAM workaround SHA256 rate 9.433MB/sec Debug 240MHz HW rev1 SHA256 rate 3.727MB/sec Release 80MHz HW rev1 SHA256 rate 10.961MB/sec Release 240MHz HW rev1 SHA256 rate 9.966MB/sec Release 240MHz HW rev1 + PRAM workaround SHA256 rate 10.974MB/sec Debug 240MHz HW rev3 SHA256 rate 4.362MB/sec Release 80MHz HW rev3 SHA256 rate 13.207MB/sec Release 240MHz HW rev3 Debug = Og, assertions enabled Release = O2, assertions disabled	2019-11-04 10:48:08 +01:00