Commit graph

6 commits

Author SHA1 Message Date
Michael (XIAO Xufeng)
ffc46954ae esp_flash: fix the write performance regression
Also changed internal delay unit into microsecond.
2020-07-15 02:20:35 +08:00
Armando
aa5b4fb372 esp_flash: fix the regression of non-quad mode by default chip driver 2020-06-28 15:52:58 +08:00
Michael (XIAO Xufeng)
b5d04a21fb esp_flash: fix the quad issue for some GD flash chips
The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
2019-11-21 12:26:15 +08:00
Michael (XIAO Xufeng)
2b7681ec4f esp_flash: fix set qe bit and write command issues
There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.
2019-11-21 12:26:14 +08:00
Michael (XIAO Xufeng)
1cc860216e esp_flash: fix the set/get write protection functions
Add support for get write protection support, fixed the duplicated
set_write_protection link.

All the write_protection check in the top layer are removed. The lower
levels (chip) should ensure to disable write protection before the
operation start.
2019-08-20 14:05:35 +08:00
Michael (XIAO Xufeng)
1036a091fe spi_flash: support working on differnt buses and frequency 2019-06-18 06:32:52 +00:00