Commit graph

179 commits

Author SHA1 Message Date
Ivan Grokhotkov
78fab8a0f9 sdmmc: implement partial DDR support
Works for 3.3V eMMC in 4 line mode.
Not implemented:
- DDR mode for SD cards (UHS-I) also need voltage to be switched to 1.8V.
- 8-line DDR mode for eMMC to be implemented later.
2018-08-30 13:11:54 +08:00
Mahavir Jain
f0fa66a50e rtc_wdt: fix overflow issue with setting wdt interval
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-24 18:06:39 +05:30
Ivan Grokhotkov
88d40e01b4 Merge branch 'feature/rtc_slowclk_extra_options' into 'master'
Add more RTC_SLOW_CLK options

See merge request idf/esp-idf!2984
2018-08-23 11:27:14 +08:00
Ivan Grokhotkov
902344c516 Merge branch 'bugfix/trace_mem_layout_pro_cpu' into 'master'
soc: fix trace memory region for single core mode

See merge request idf/esp-idf!3029
2018-08-22 16:51:43 +08:00
Ivan Grokhotkov
5bf3654637 soc/rtc: Force power on 8M clock if it is used to derive RTC slow clock 2018-08-22 11:33:20 +08:00
Ivan Grokhotkov
8365f0f5d2 soc/rtc: add support for external 32k oscillator
Compared to external 32k XTAL, when active oscillator is used as input,
some parameters need to be set differently.
2018-08-22 11:33:20 +08:00
Ivan Grokhotkov
e59571eece soc/rtc_clk: reduce data size by disabling CSWTCH generation
Saves about 200 bytes of DRAM at the expense of 4 bytes in IRAM.
2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
db2f0f45be soc/rtc_clk: split rtc_clk_init into separate object file
rtc_clk_init and related functions don’t need to be in IRAM/DRAM.
2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
bcf79e5cf2 tests: use new CPU frequency setting API 2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
bec70ce298 esp32: use new CPU frequency setting API 2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
2e31cce390 soc/rtc: CPU frequency settings refactoring
Previous APIs used to set CPU frequency used CPU frequencies listed in
rtc_cpu_freq_t enumeration. This was problematic for two reasons.
First, supporting many possible frequency values obtained by dividing
XTAL frequency was hard, as every value would have to be listed in
the enumeration. Since different base XTAL frequencies are supported,
this further complicated things, since not all of these divided
frequencies would be valid for any given XTAL frequency. Second,
having to deal with enumeration values often involved switch
statements to convert between enumeration and MHz values, handle
PLL/XTAL frequencies separately, etc.

This change introduces rtc_cpu_freq_config_t structure, which contains
CPU frequency (in MHz) and information on how this frequency has to
be generated: clock source (XTAL/PLL), source frequency, clock
divider value. More fields can be added to this structure in the
future. This structure simplifies many parts of the code, since both
frequency value and frequency generation settings can be accessed in
any place in code without the need for conversions.

Additionally, this change adds setting of REF_TICK dividers to support
frequencies lower then XTAL with DFS.
2018-08-21 13:02:03 +08:00
Mahavir Jain
0075e2f316 soc: fix trace memory region for single core mode
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-15 20:52:39 +05:30
Konstantin Kondrashov
a8e46775c6 soc/rtc_wdt: Add API functions for rtc_wdt
Added functions:
rtc_wdt_protect_off/on
rtc_wdt_set_length_of_reset_signal
rtc_wdt_set_stage
rtc_wdt_set_time
rtc_wdt_feed
rtc_wdt_disable/enable
2018-08-14 17:48:02 +05:00
Ivan Grokhotkov
8739111218 Merge branch 'bugfix/gpio_reset_bitmask' into 'master'
gpio: Bitmask overflow fix in gpio_reset_pin

See merge request idf/esp-idf!2966
2018-08-10 17:35:26 +08:00
Taavi Hein
f7749e18a8 gpio: Bitmask overflow fix in gpio_reset_pin
For pins 32 and up the BIT(nr) macro used here overflowed,
causing undetermined GPIO pins to be reset.
Example: freeing SPI device/bus where CS is on pin 33
caused debug UART to cease communication, TXD0 was
disabled.

Fixed as BIT64(nr) macro, to be used elsewhere as needed.
For example in definitions like GPIO_SEL_32..GPIO_SEL_39.
2018-08-08 15:31:17 +03:00
Angus Gratton
a5ae5ac4b3 soc: Allow components to reserve fixed memory ranges that they need
No longer necessary to keep all reserved addresses in 'soc'.

Means 'soc' does not need to know about 'bt', for example.

Also means that Bluetooth can be enabled in config without any memory being reserved for BT
controller. Only if code calling the BT controller is linked in, will this memory be reserved...
2018-08-06 01:37:55 +00:00
David Cermak
409c91bcb9 removed possible uint16 access to 32bit register, noted fifo use not recommended 2018-07-23 07:57:18 +02:00
Ivan Grokhotkov
fec079cd44 Merge branch 'bugfix/rtc_io_hold_regs' into 'master'
Fix errors in rtc_gpio_desc values

See merge request idf/esp-idf!2765
2018-07-19 15:04:42 +08:00
Ivan Grokhotkov
5376a06d7b Merge branch 'bugfix/range_CONFIG_ESP32_RTC_CLK_CAL_CYCLES' into 'master'
soc/clk: Fix range CONFIG_ESP32_RTC_CLK_CAL_CYCLES

See merge request idf/esp-idf!2719
2018-07-17 19:43:11 +08:00
negativekelvin
8a9e3875ed
Fix errors in rtc_gpio_desc values 2018-07-12 23:16:15 -07:00
Angus Gratton
a67d5d89e0 Replace all DOS line endings with Unix
Command run was:
git ls-tree -r HEAD --name-only | xargs dos2unix
2018-07-12 19:10:37 +08:00
Konstantin Kondrashov
ac3508615a soc/clk: Fix range CONFIG_ESP32_RTC_CLK_CAL_CYCLES
Fixed the error division on zero.
Also fixed range CONFIG_ESP32_RTC_CLK_CAL_CYCLES in Kconfig.
Fixed a overflow error by TIMG in the function rtc_clk_cal_internal. This error was due to a limit in values TIMG_RTC_CALI_MAX=0x7FFF (to write the slowclk_cycles) and TIMG_RTC_CALI_VALUE=0x1FFFFFF (to read xtal_cycles). Added assert finctions.

Closes https://github.com/espressif/esp-idf/issues/2147
2018-07-10 11:56:12 +05:00
Darian Leung
1d2727f4c8 CAN Driver
The following commit contains the first version of the ESP32 CAN Driver.

closes #544
2018-07-04 14:01:57 +08:00
Konstantin Kondrashov
32da455384 soc: Fix check_long_hold_gpio and move def to soc
Fix factory_reset_pin init as input
Move definition a structure rtc_gpio_desc to soc

Closes https://github.com/espressif/esp-idf/issues/2030
2018-06-22 09:20:27 +05:00
Ivan Grokhotkov
4b91c82cc4 Merge branch 'feat/sdio_pullup' into 'master'
feature(sdio): add features to make SDIO slave compatible with more devkits

See merge request idf/esp-idf!2454
2018-06-20 13:58:56 +08:00
michael
5b37a96ddc feature(sdio): allow to enable internal pullups of the SDIO host and slave as a debug feature
NOTE: the internal pullups are not totally reliable, please do add external pullups on your bus.
2018-06-14 12:04:22 +08:00
Michael (XIAO Xufeng)
ebfda40b7c refactor(spi): move pin information into soc folder 2018-06-14 11:29:15 +08:00
Michael (XIAO Xufeng)
939e5693a5 chore(spi): fix the terms of native to iomux 2018-06-06 06:08:39 +00:00
michael
5cf7d3768d feat(spi_master): fine tune the timing of SPI 2018-06-06 06:08:39 +00:00
Angus Gratton
3e1a93e5a7 soc: rtc_vddsdio_get_config() In default configuration, VDD_SDIO LDO is always enabled
When using bootstrapping pin to enable VDD_SDIO, the internal LDO is always enabled at either 1.8V
or 3.3V.
2018-05-25 15:14:13 +10:00
Angus Gratton
d775cc4c4c soc: Fix description of rtc_config_t.tieh, add macros
Usage of TIEH was correct but description had 1.8V & 3.3V backwards.

Add macro definitions for TIEH values to improve readability.
2018-05-25 14:58:37 +10:00
Angus Gratton
b8312a26c0 Merge branch 'feature/sdio_slave' into 'master'
feature(sdio_slave): add support for sdio_slave

See merge request idf/esp-idf!1829
2018-05-22 09:43:35 +08:00
Konstantin Kondrashov
e5b280f173 dport: Bigfix dport_read code move to IRAM
A new method of workaround an error with DPORT is to ensure that the APB is read and followed by the DPORT register without interruptions and pauses. This fix places this implementation in the IRAM to exclude errors associated with the cache miss.
2018-05-21 22:00:51 +05:00
Michael (XIAO Xufeng)
c73575de4f feat(sdio_slave): add headers for sdio slave components: slc, host, hinf 2018-05-21 23:48:33 +08:00
wangmengyang
22e21b38f7 component/bt: implement bluetooth modem sleep mode, one mode for BLE only and another for dual mode bluetooth
1. provide options for bluetooth low power mode
2. provide two options for bluetooth low power clock: main XTAL and external 32kHz XTAL
3. provide function and callbacks to control bluetooth low power mode, including enable/disable sleep, software wakeup request, low power clock settings, check power state, etc
4. modify vhci API vhci_host_send_packet to use blocking mode
5. note that DFS and bluetooth modem sleep can not be used together currently.
2018-05-19 15:37:26 +08:00
Angus Gratton
7ae1e9463e Merge branch 'bugfix/rtc_xtal_tests' into 'master'
ci: Only run XTAL unit tests assuming board has an XTAL

See merge request idf/esp-idf!2401
2018-05-15 18:44:46 +08:00
Angus Gratton
05e09a5bac ci: Only run XTAL unit tests assuming board has an XTAL, run less repeats 2018-05-15 15:43:24 +08:00
Angus Gratton
d1066e9d7f Merge branch 'feature/dport_access' into 'master'
soc: Dport access with pre-read register APB

See merge request idf/esp-idf!2257
2018-05-15 15:32:28 +08:00
Angus Gratton
662fe55996 Merge branch 'bugfix/select_rtc_slow_clk' into 'master'
esp32/clk: Fix starting rtc oscillator if it bad

See merge request idf/esp-idf!2215
2018-05-15 12:57:22 +08:00
Konstantin Kondrashov
9ad0760b9d esp32/clk:Fix starting rtc oscillator if it is bad
If the RTC crystal is bad or has no matched capacitance, then you do not need to start such the crystal. It is necessary to determine this case, output an error (about impossibility to start from the oscillator) and start from the internal RC of the chain.

Reduced the default value of the number of bootstrap cycles. Because we can oscillating the oscillator which then stops. (in Kconfig). Changed from 100 to 5.

The number of calibration cycles has been increased. It is the main criterion for estimating the launch of an oscillator. A large increase leads to an increase in the load time, as well as the stability of recognition of this case. (in Kconfig).
Changed from 1024 to 3000.
2018-05-15 08:59:15 +05:00
Konstantin Kondrashov
8f80cc733d soc: Change DPORT access
When two CPUs read the area of the DPORT and the area of the APB, the result is corrupted for the CPU that read the APB area.
And another CPU has valid data.

The method of eliminating this error.
Before reading the registers of the DPORT, make a preliminary reading of the APB register.
In this case, the joint access of the two CPUs to the registers of the APB and the DPORT is successful.
2018-05-14 17:54:57 +05:00
jack
c384fa2492 rename clock enable and reset bits for SPI modules
1.The names of clock enable and reset bits do not match with TRM, just rename them.
2018-05-14 16:45:03 +08:00
Jiang Jiang Jian
db90f49758 Merge branch 'bugfix/update_emac_h' into 'master'
update emac_reg_v2.h

See merge request idf/esp-idf!2050
2018-05-07 16:16:52 +08:00
Ivan Grokhotkov
94250e42a0 sleep: optimize light sleep wakeup latency 2018-04-26 19:36:47 +08:00
Ivan Grokhotkov
ac623a9756 soc/rtc: restore dbg attenuation when waking from sleep
This fixes inability to enter deep sleep after waking up from light sleep
2018-04-26 18:52:46 +08:00
Ivan Grokhotkov
d38b22b11b soc/rtc, sleep: don’t lower the bias for wakeup state
This fixes watchdog resets occurring during wakeup from light sleep.
2018-04-26 18:52:45 +08:00
Ivan Grokhotkov
b0a91630fb soc/rtc: allow main XTAL to be powered on in sleep 2018-04-26 18:52:45 +08:00
Ivan Grokhotkov
3c78faa0a9 soc/rtc: don’t switch frequency in rtc_sleep_init 2018-04-26 18:52:45 +08:00
shangke
5fc130f2c0 update emac_reg_v2.h 2018-04-25 14:54:09 +08:00
Ivan Grokhotkov
52f9a5ca16 Merge branch 'bugfix/sdspi_wp_cd_pins' into 'master'
sdmmc, sdspi: fix handling of CD and WP

See merge request idf/esp-idf!2285
2018-04-24 20:53:47 +08:00