When compiling in release mode, compiler was choosing same register for
oldint and intmask variables, so INTENABLE was never modified.
This effectively broke disabling of non-IRAM interrupts during flash
operations, observed in the existing tests if task watchdog is enabled.
This change adds an extra constraint tells the compiler that output
operand should not be placed into the same register as an input one.
Parse unit test cases from test files
As of now, we need to sync three different places when adding new unit test cases. The plan is to add a python script in tools/unit-test-app. This script would parse unit test cases from the C files with tests and generate the needed YAML files in components/idf_test/unit_test. CI would run this script in build stage to create the files and unit-test stage would use the generated files to run tests.
To get the needed test metadata, we need to add some more tags in the test case functions. For example:
```
TEST_CASE("SYS_LIB_0102 test time functions", "[stdlib][fails][env=UT_T1_APC]")
{
//...
}
```
Reason for this kind of implementation is that we need the YAML files for generating documents.
See merge request !275
Add python script that parses list of unit test cases for CI from component test folder
Modify .gitlab-ci.yml to run this script as part of build unit tests stage
spi_flash_enable_interrupts_caches_and_other_cpu function used to enable
non-IRAM interrupts after giving up flash operation lock, which would
cause problems if another task was waiting on the lock to start a flash
operation. In fact, non-IRAM interrupts should be re-enabled before the
task scheduler is resumed. Otherwise non-pinned task can be moved to the
other CPU due to preemption, causing esp_intr_noniram_enable to be
called on the other CPU, causing an abort to be triggered.
Fixes the issue reported in
https://github.com/espressif/esp-idf/pull/258
Delete option to select core timer 2 as a FreeRTOS tick source
Core timer 2 is unusable for FreeRTOS ticks because it triggers a high-level interrupt. This MR deletes the option to select it.
Ref https://github.com/espressif/esp-idf/issues/234
See merge request !418
In some cases (when RTC register reads are performed from the APP CPU), a write to FRC_TIMER_INT_REG may be lost on the bus.
Writing to another DPORT register immediately before or after that works around the issue.
We write one dummy value to an address which doesn’t have any register associated with it.
Fixes https://github.com/espressif/arduino-esp32/issues/120
1. add openssl option at menuconfig
2. remove SSL_ERR to reduce complexity
3. add more functions about debugging and assert
According these, our coders and customers may use and debug the OpenSSL code easily.
One common pattern of using assert function looks as follows:
int ret = do_foo();
assert(ret == 0); // which reads as: “do_foo should never fail here, by design”
The problem with such code is that if ‘assert’ is removed by the preprocessor in release build,
variable ret is no longer used, and the compiler issues a warning about this.
Changing assert definition in the way done here make the variable used, from language syntax perspective.
Semantically, the variable is still unused at run time (as sizeof can be evaluated at compile time), so the compiler
can optimize things away if possible.
These functions are marked as inline and are called from functions which are in IRAM.
In release (-Os) builds, the compiler may decide not to inline these functions.
Placing these functions into IRAM explicitly works around this.
update wifi lib: fix some wifi lib bugs
1. net80211: fix get ap info error(a4614877)
2. tw9358: sta mac same with softap(ea38d32c)
3. tw9221: scan channel error when connected(183d469c)
See merge request !425
