Commit graph

10 commits

Author SHA1 Message Date
Renz Christian Bagaporo
67983d5c1c esp_system: restore order of some init functions 2020-06-19 18:40:10 +10:00
Renz Christian Bagaporo
ef2a44d251 esp_system: introduce single core mode proxy config 2020-06-19 18:40:10 +10:00
Renz Christian Bagaporo
c53ad56515 esp_system: startup flow modifications
Changes the startup flow to the ff:

hardware -> core libraries init  -> other libraries init -> os
init (optional) -> app_main

- hardware init resides in the port layer, and is the entry point

- core libraries init executes init functions of core components

- other libraries init executes init functions of other components (weak
references)

- after other lib is init, the app_main function is called, however,

 an OS can wrap the real call to app_main to init its own stuff, and
 *then* call the real app_main
2020-06-19 18:40:09 +10:00
Ivan Grokhotkov
f4ea9d4cea freertos: increase configMINIMAL_STACK_SIZE when building with -O0
FreeRTOS scheduler uses additional stack space, as in some functions
variables are placed onto the stack instead of registers.

This issue resulted in occasional stack overflows in dport task, when
compiling at -O0 optimization level.

- Increase the configMINIMAL_STACK_SIZE to 1kB.
- Enable the watchpoint at the end of stack in CI startup test for
  this optimization level.
2020-06-02 18:51:16 +02:00
Ivan Grokhotkov
614a580bbb freertos, soc: don't lower INTLEVEL when entering critical sections
This fixes the issue where XTOS_SET_INTLEVEL would lower INTLEVEL from
4 to 3, when eTaskGetState is invoked during the core dump, triggered
from the interrupt watchdog.
2020-06-02 15:42:24 +02:00
Renz Christian Bagaporo
2b100789b7 esp32, esp32s2: move panic handling code to new component 2020-03-10 19:56:24 +08:00
Sachin Parekh
301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
2020-02-26 20:21:59 +08:00
Felipe Neves
9c8289b0d9 shared_stack: using watchpoint 1 to monitor the shared_stack instead of watchpoint 0 2020-02-10 12:03:30 -03:00
Angus Gratton
86034ad049 Merge branch 'feature/freertos_fpu_isr' into 'master'
feature/fpu: Enable usage of FPU inside of a ISR

Closes IDF-100

See merge request espressif/esp-idf!7348
2020-01-30 13:38:37 +08:00
Felipe Neves
429712c6eb freertos: moved all xtensa specific files into a separated folder 2020-01-27 16:05:30 -03:00