1. Use BIT[7:5] of EID to determine psram size
2. Add ID support for 16Mbit psram
3. Remove module reset on SPI1
4. Confirmed with the vendor that only the old 32Mbit psram need special clock timing. For other psram chips, we should use standard QPI mode.
1. add network channel switch function.
- users can obtain the new channel through the event MESH_EVENT_CHANNEL_SWITCH.
- the entire network will be moved to the same channel as the router without user intervention.
- if no router is in the network, users can call esp_mesh_switch_channel() on the root side to
move the entire network to their desired channel.
2. support not configuring the network channel.
3. support not configuring the router BSSID even if the router is hidden.
4. add allow_channel_switch to mesh configuration.
- if the channel is not specified, this value will be ignored.
- if the channel is specified and this value is set, when "fail" (mesh_attempts_t) times of parent selection
or look for networks are reached, device will change to perform a full channel scan for networks that could join.
- if the channel is specified and this value is set to 0, when a root is not elected, channel switch is not allowed.
but when a root appears, the root performs a full channel scan during the process of connecting to the router,
so even allow_channel_switch is set to 0, the root may still switch channel and eventually the entire network
changes channel.
5. add allow_router_switch to mesh router configuration.
- if the BSSID of router is not specified, this value will be ignored.
- if the BSSID of router is specified and this value is set, when the router of this specified BSSID fails to be found
after "fail" (mesh_attempts_t) times, the entire network is allowed to switch to another router with the same SSID.
6. modify the root to perform a full channel scan when esp_wifi_connect().
7. support handling beacon without DS Paramter Set.
The number of runners of integration test is not bottleneck to CI
pipeline performance now. Combine these 2 stages will make integration
test executed even unit test fails. This could help us to collect more
info about test history.
The DMA cannot receive data correctly when the buffer address is not
WORD aligned. Currently we only check whether the buffer is in the DRAM
region.
The DMA always write in WORDs, so the length arguments should also be
multiples of 32 bits.
A check is added to see whether the buffer is WORD aligned and has valid
length.
The driver decide whether use MOSI/MISO phases according to the buffer
address together with the SPI_TRANS_USE_*DATA. However someone may assue
that these phases will be skipped when the ``length``/``rxlength`` is
set to 0. In fact it is a feature that ``rxlength`` is allowed to be
set to 0 when tx and rx have the same length, and the driver fill the
``rxlength`` to ``length``.
An error check is added when the rxlength is 0 but there is data to be
sent.
