4 commits

Author	SHA1	Message	Date
Wu Jian Gang	04b53643ef	header files: clean up ... 1. format; 2. Slow RTC memory reverse 2KB;	2016-09-12 17:47:50 +08:00
jack	24011ddd05	header files: modify rom code and soc header files ... 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions	2016-09-12 17:47:49 +08:00
liuzhifu	ebfb8547d2	Implement ETS_INTR_ENABLE/ETS_INTR_DISABLE with xt_ints_on/xt_ints_off	2016-08-26 19:03:51 +08:00
Ivan Grokhotkov	bd6ea4393c	Initial public version	2016-08-17 23:08:22 +08:00