The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.
Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
SDMMC hardware treats all buffers as aligned, and ignores 2 LSBs of
addresses written into DMA descriptors. Previously SDMMC host driver
assumed that data buffers passed from SDDMC command layer would be
aligned. However alignment checks were never implemented in the command
layer, as were the checks that the buffer coming from the application
would be in DMA capable memory. Most of the time this was indeed true.
However in some cases FATFS library can pass buffers offset by 2 bytes
from word boundary. “DMA capable” restriction may be broken if pSRAM
support is used.
This change adds buffer checks to the SDMMC host driver (alignment and
DMA capability), so that the host layer will error out for incompatible
buffers. In SDMMC command layer, a check is added to read and write
functions. If an incompatible buffer is passed from the application, new
buffer (512 bytes size) is allocated, and the transfer is performed
using {READ,WRITE}_SINGLE_BLOCK commands.
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change: move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
I2S driver - fixed support for 24 and 32-bits, fixed tx/rx at the same time
- Modify sample can test with 24, 32-bits audio
- Add i2s sample README
- simply i2s_push function
- change sample rates, bits per sample, channel on fly
See merge request !483
Add support 24, 32 bits
@jxmao optimize i2s_zero_buffer
@jxmao correct config support slave mode
@jxmao correct setup pin support tx/rx at the same time
Enhance pin power
@jxmao add dynamic change number of channels
remove nvs_init
remove start log and enhance power pin setup
using enum for i2s_channel and i2s_bits_per_sample, return ESP_ERR_INVALID_ARG when check params
validate i2s_bits_per_sample and channel
check tx & rx buffer before fill zero
remove checking channel as @jxmao suggest
limit dma buffer
modify i2s pin back to gpio mux before configure gpio matrix, resolve github issue #512
Add support 24, 32 bits
reduce push function
Modify sample can test with 24, 32-bits
Add i2s sample README
Fixed i2s_set_clk got reset sometime
can changes bit-wide while running
Fix sample rate calculation for DAC mode from @jeroen
modify example can change bits per sample every 5 seconds
cleanup
add comment for bytes_per_sample
update as @angus suggestions
Add i2s_set_clk api
I2S driver bug fixed as following log:
@jxmao optimize i2s_zero_buffer
@jxmao correct config support slave mode
@jxmao correct setup pin support tx/rx at the same time
Enhance pin power
@jxmao add dynamic change number of channels
remove nvs_init
remove start log and enhance power pin setup
using enum for i2s_channel and i2s_bits_per_sample, return ESP_ERR_INVALID_ARG when check params
validate i2s_bits_per_sample and channel
check tx & rx buffer before fill zero
remove checking channel as @jxmao suggest
limit dma buffer
modify i2s pin back to gpio mux before configure gpio matrix, resolve github issue #512
limit dma buffer to 4092
change gpio_matrix_*_check to inline function, remove some comments and rename test_i2s function to setup_triangle_sine_waves
for change commit title
1. Add low speed channels for LEDC module.
2. Improve fade object allocate mechanism.
3. Improve ledc example, add 2 low speed channels in example.
4. Remove debug code
5. Improve the register bit field name of slow clock.
The touch pad read function taks too much time within spin lock waiting for the "done bit". (about 7.6ms as we tested)
So we try to use a mutex on the touch read function and any other functions might change the "done bit".
