If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
1. fix bug that there's very low ratio to cause BLE assert(32768, 0) in rwble.c at line 222
2. fix bug that there's very low ratio to cause BLE assert(65536, 0) in rwble.c at line 222
Fix some wifi bugs:
1. Enable RX BAR
2. Fix the bug that ESP32 AP negotiates with iphone to 11g
3. Fix the bug that ESP32 STA has ap_loss because CMCC AP contains two SSID
This commit resolves a blocking in esp_aes_block function.
Introduce:
The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing.
Fix some related issue with shared using of AES SHA RSA accelerators.
Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
1. Fix the bug that disable controller suddenly cause crash when ble is working.
2. Fix the bug that when disable controller, it will cause wifi cannot RX, TX timeout, buffer lack and etc.
When WIFI task or other high priority task blocks the Bluetooth task, ACL RX buffer will use up, ACL RX buffer ptr will point to null and will never point to a valid adress. Causing errors in Bluetooth.
Fix following WiFi bugs:
1. Fix the bug that sniffer can't catch control packets
2. Fix crash bug in soft-AP mode
3. Fix ACM(Admission Control Management) bug
Resolve the problem following:
1. when wifi and bluetooth coex, after call esp_bt_controller_disable(), it may cause WiFi cannot TX/RX packets.
Such as, it cause wifi disconnect, can't probe any SSIDs or etc.
1. remove use EID to distinguish psram voltage
2. 1V8 64Mbit psram and 3V3 64Mbit psram use the same psram driver(standard spi interface)
3. set cs hold time register as 1
1. Add reading psram EID.
2. Configure different clock mode for different EID.
3. add API to get psram size and voltage.
4. Remove unnecessary VSPI claim.
For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level.
For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case.
EID for psram:
32MBit 1.8v: 0x20
64MBit 1.8v: 0x26
64MBit 3.3v: 0x46
1. Fix the bug that ESP32 will reject the retry AddBA request frame
if AddBA response frame is failed to sent by WiFi LMAC
2. Fix the bug that AddBA request retrys too frequently
3. Forbid BA session setup for VO queue related TID
