From fa555e3109e5491688f6ffc4c3e7349c09854b5d Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Sun, 7 Jul 2019 18:11:02 +0800 Subject: [PATCH] esp_flash: fix a compatibility issue working with the ROM The esp_flash API has a side effects: it modifies the clock control registers, and this makes the clock inconsistent with the ROM variable `g_rom_spiflash_dummy_len_plus`. This commit helps the ROM to get the correct dummy cycles required by the latest clock settings. Every device on the SPI1 bus will update the ROM variable when it modifies the clock registers. --- components/soc/src/hal/spi_flash_hal_iram.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/components/soc/src/hal/spi_flash_hal_iram.c b/components/soc/src/hal/spi_flash_hal_iram.c index ddd2c7d5f..56a525baa 100644 --- a/components/soc/src/hal/spi_flash_hal_iram.c +++ b/components/soc/src/hal/spi_flash_hal_iram.c @@ -38,6 +38,17 @@ esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver) spi_flash_ll_reset(dev); spi_flash_ll_set_cs_pin(dev, drv_data->cs_num); spi_flash_ll_set_clock(dev, &drv_data->clock_conf); + + /* + * workaround for the ROM: the ROM, as well as the OpenOCD, don't know the + * clock registers and the dummy are modified this help the ROM to read and + * write correctly according to the new dummy len. + */ + if (dev == &SPI1) { + //0 for cache, 1 for SPI1 + extern uint8_t g_rom_spiflash_dummy_len_plus[]; + g_rom_spiflash_dummy_len_plus[1] = drv_data->extra_dummy; + } return ESP_OK; }