From a03e75d34ccc977ef1d3aa7efb944beee4b6748a Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Sat, 8 Oct 2016 14:11:34 +0800 Subject: [PATCH 1/3] Move heap_alloc_caps.h to a location where it can be included by components --- components/esp32/{ => include}/heap_alloc_caps.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename components/esp32/{ => include}/heap_alloc_caps.h (100%) diff --git a/components/esp32/heap_alloc_caps.h b/components/esp32/include/heap_alloc_caps.h similarity index 100% rename from components/esp32/heap_alloc_caps.h rename to components/esp32/include/heap_alloc_caps.h From 82df5f9aa0c6131cd9b167d5a2501d4f941959b3 Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Sat, 8 Oct 2016 14:12:55 +0800 Subject: [PATCH 2/3] Convert Windows -> Unix line ends in gpio.c --- components/driver/gpio.c | 736 +++++++++++++++++++-------------------- 1 file changed, 368 insertions(+), 368 deletions(-) diff --git a/components/driver/gpio.c b/components/driver/gpio.c index 320533e8d..14dfc00b4 100644 --- a/components/driver/gpio.c +++ b/components/driver/gpio.c @@ -1,368 +1,368 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#include -#include "esp_err.h" -#include "esp_intr.h" -#include "freertos/FreeRTOS.h" -#include "freertos/xtensa_api.h" -#include "driver/gpio.h" -#include "soc/soc.h" - -//TODO: move debug options to menuconfig -#define GPIO_DBG_ENABLE (0) -#define GPIO_WARNING_ENABLE (0) -#define GPIO_ERROR_ENABLE (0) -#define GPIO_INFO_ENABLE (0) -//DBG INFOR -#if GPIO_INFO_ENABLE -#define GPIO_INFO ets_printf -#else -#define GPIO_INFO(...) -#endif -#if GPIO_WARNING_ENABLE -#define GPIO_WARNING(format,...) do{\ - ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\ - ets_printf(format,##__VA_ARGS__);\ -}while(0) -#else -#define GPIO_WARNING(...) -#endif -#if GPIO_ERROR_ENABLE -#define GPIO_ERROR(format,...) do{\ - ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\ - ets_printf(format,##__VA_ARGS__);\ -}while(0) -#else -#define GPIO_ERROR(...) -#endif - -const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { - GPIO_PIN_REG_0, - GPIO_PIN_REG_1, - GPIO_PIN_REG_2, - GPIO_PIN_REG_3, - GPIO_PIN_REG_4, - GPIO_PIN_REG_5, - GPIO_PIN_REG_6, - GPIO_PIN_REG_7, - GPIO_PIN_REG_8, - GPIO_PIN_REG_9, - GPIO_PIN_REG_10, - GPIO_PIN_REG_11, - GPIO_PIN_REG_12, - GPIO_PIN_REG_13, - GPIO_PIN_REG_14, - GPIO_PIN_REG_15, - GPIO_PIN_REG_16, - GPIO_PIN_REG_17, - GPIO_PIN_REG_18, - GPIO_PIN_REG_19, - 0, - GPIO_PIN_REG_21, - GPIO_PIN_REG_22, - GPIO_PIN_REG_23, - 0, - GPIO_PIN_REG_25, - GPIO_PIN_REG_26, - GPIO_PIN_REG_27, - 0, - 0, - 0, - 0, - GPIO_PIN_REG_32, - GPIO_PIN_REG_33, - GPIO_PIN_REG_34, - GPIO_PIN_REG_35, - GPIO_PIN_REG_36, - GPIO_PIN_REG_37, - GPIO_PIN_REG_38, - GPIO_PIN_REG_39 -}; - -static int is_valid_gpio(int gpio_num) -{ - if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) { - GPIO_ERROR("GPIO io_num=%d does not exist\n",gpio_num); - return 0; - } - return 1; -} - -esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if(intr_type >= GPIO_INTR_MAX) { - GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type); - return ESP_ERR_INVALID_ARG; - } - GPIO.pin[gpio_num].int_type = intr_type; - return ESP_OK; -} - -esp_err_t gpio_intr_enable(gpio_num_t gpio_num) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if(xPortGetCoreID() == 0) { - GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr - } else { - GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr - } - return ESP_OK; -} - -esp_err_t gpio_intr_disable(gpio_num_t gpio_num) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr - return ESP_OK; -} - -static esp_err_t gpio_output_disable(gpio_num_t gpio_num) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if(gpio_num < 32) { - GPIO.enable_w1tc = (0x1 << gpio_num); - } else { - GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32)); - } - return ESP_OK; -} - -static esp_err_t gpio_output_enable(gpio_num_t gpio_num) -{ - if(gpio_num >= 34) { - GPIO_ERROR("io_num=%d can only be input\n",gpio_num); - return ESP_ERR_INVALID_ARG; - } - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if(gpio_num < 32) { - GPIO.enable_w1ts = (0x1 << gpio_num); - } else { - GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32)); - } - return ESP_OK; -} - -esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level) -{ - if(!GPIO_IS_VALID_GPIO(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if(level) { - if(gpio_num < 32) { - GPIO.out_w1ts = (1 << gpio_num); - } else { - GPIO.out1_w1ts.data = (1 << (gpio_num - 32)); - } - } else { - if(gpio_num < 32) { - GPIO.out_w1tc = (1 << gpio_num); - } else { - GPIO.out1_w1tc.data = (1 << (gpio_num - 32)); - } - } - return ESP_OK; -} - -int gpio_get_level(gpio_num_t gpio_num) -{ - if(gpio_num < 32) { - return (GPIO.in >> gpio_num) & 0x1; - } else { - return (GPIO.in1.data >> (gpio_num - 32)) & 0x1; - } -} - -esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - esp_err_t ret = ESP_OK; - switch(pull) { - case GPIO_PULLUP_ONLY: - PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]); - PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]); - break; - case GPIO_PULLDOWN_ONLY: - PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]); - PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]); - break; - case GPIO_PULLUP_PULLDOWN: - PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]); - PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]); - break; - case GPIO_FLOATING: - PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]); - PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]); - break; - default: - GPIO_ERROR("Unknown pull up/down mode,gpio_num=%u,pull=%u\n",gpio_num,pull); - ret = ESP_ERR_INVALID_ARG; - break; - } - return ret; -} - -esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) { - GPIO_ERROR("io_num=%d can only be input\n",gpio_num); - return ESP_ERR_INVALID_ARG; - } - esp_err_t ret = ESP_OK; - if(mode & GPIO_MODE_DEF_INPUT) { - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); - } else { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); - } - if(mode & GPIO_MODE_DEF_OUTPUT) { - if(gpio_num < 32) { - GPIO.enable_w1ts = (0x1 << gpio_num); - } else { - GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32)); - } - } else { - if(gpio_num < 32) { - GPIO.enable_w1tc = (0x1 << gpio_num); - } else { - GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32)); - } - } - if(mode & GPIO_MODE_DEF_OD) { - GPIO.pin[gpio_num].pad_driver = 1; - } else { - GPIO.pin[gpio_num].pad_driver = 0; - } - return ret; -} - -esp_err_t gpio_config(gpio_config_t *pGPIOConfig) -{ - uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask); - uint32_t io_reg = 0; - uint32_t io_num = 0; - uint64_t bit_valid = 0; - if(pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) { - GPIO_ERROR("GPIO_PIN mask error \n"); - return ESP_ERR_INVALID_ARG; - } - if((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) { - //GPIO 34/35/36/37/38/39 can only be used as input mode; - if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) { - GPIO_ERROR("GPIO34-39 can only be used as input mode\n"); - return ESP_ERR_INVALID_ARG; - } - } - do { - io_reg = GPIO_PIN_MUX_REG[io_num]; - if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) { - GPIO_INFO("Gpio%02d |Mode:",io_num); - if((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) { - GPIO_INFO("INPUT "); - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]); - } else { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]); - } - if((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) { - GPIO_INFO("OD "); - GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */ - } else { - GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */ - } - if((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) { - GPIO_INFO("OUTPUT "); - gpio_output_enable(io_num); - } else { - gpio_output_disable(io_num); - } - GPIO_INFO("|"); - if(pGPIOConfig->pull_up_en) { - GPIO_INFO("PU "); - PIN_PULLUP_EN(io_reg); - } else { - PIN_PULLUP_DIS(io_reg); - } - if(pGPIOConfig->pull_down_en) { - GPIO_INFO("PD "); - PIN_PULLDWN_EN(io_reg); - } else { - PIN_PULLDWN_DIS(io_reg); - } - GPIO_INFO("Intr:%d |\n",pGPIOConfig->intr_type); - gpio_set_intr_type(io_num, pGPIOConfig->intr_type); - if(pGPIOConfig->intr_type) { - gpio_intr_enable(io_num); - } else { - gpio_intr_disable(io_num); - } - PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */ - } else if(bit_valid && (io_reg == 0)) { - GPIO_WARNING("io_num=%d does not exist\n",io_num); - } - io_num++; - } while(io_num < GPIO_PIN_COUNT); - return ESP_OK; -} - -esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg) -{ - if(fn == NULL) { - return ESP_ERR_INVALID_ARG; - } - ESP_INTR_DISABLE(gpio_intr_num); - intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num); - xt_set_interrupt_handler(gpio_intr_num, fn, arg); - ESP_INTR_ENABLE(gpio_intr_num); - return ESP_OK; -} - -/*only level interrupt can be used for wake-up function*/ -esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - esp_err_t ret = ESP_OK; - if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) { - GPIO.pin[gpio_num].int_type = intr_type; - GPIO.pin[gpio_num].wakeup_enable = 0x1; - } else { - GPIO_ERROR("GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u\n",gpio_num); - ret = ESP_ERR_INVALID_ARG; - } - return ret; -} - -esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num) -{ - if(!is_valid_gpio(gpio_num)) { - return ESP_ERR_INVALID_ARG; - } - GPIO.pin[gpio_num].wakeup_enable = 0; - return ESP_OK; -} +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include +#include "esp_err.h" +#include "esp_intr.h" +#include "freertos/FreeRTOS.h" +#include "freertos/xtensa_api.h" +#include "driver/gpio.h" +#include "soc/soc.h" + +//TODO: move debug options to menuconfig +#define GPIO_DBG_ENABLE (0) +#define GPIO_WARNING_ENABLE (0) +#define GPIO_ERROR_ENABLE (0) +#define GPIO_INFO_ENABLE (0) +//DBG INFOR +#if GPIO_INFO_ENABLE +#define GPIO_INFO ets_printf +#else +#define GPIO_INFO(...) +#endif +#if GPIO_WARNING_ENABLE +#define GPIO_WARNING(format,...) do{\ + ets_printf("[waring][%s#%u]",__FUNCTION__,__LINE__);\ + ets_printf(format,##__VA_ARGS__);\ +}while(0) +#else +#define GPIO_WARNING(...) +#endif +#if GPIO_ERROR_ENABLE +#define GPIO_ERROR(format,...) do{\ + ets_printf("[error][%s#%u]",__FUNCTION__,__LINE__);\ + ets_printf(format,##__VA_ARGS__);\ +}while(0) +#else +#define GPIO_ERROR(...) +#endif + +const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { + GPIO_PIN_REG_0, + GPIO_PIN_REG_1, + GPIO_PIN_REG_2, + GPIO_PIN_REG_3, + GPIO_PIN_REG_4, + GPIO_PIN_REG_5, + GPIO_PIN_REG_6, + GPIO_PIN_REG_7, + GPIO_PIN_REG_8, + GPIO_PIN_REG_9, + GPIO_PIN_REG_10, + GPIO_PIN_REG_11, + GPIO_PIN_REG_12, + GPIO_PIN_REG_13, + GPIO_PIN_REG_14, + GPIO_PIN_REG_15, + GPIO_PIN_REG_16, + GPIO_PIN_REG_17, + GPIO_PIN_REG_18, + GPIO_PIN_REG_19, + 0, + GPIO_PIN_REG_21, + GPIO_PIN_REG_22, + GPIO_PIN_REG_23, + 0, + GPIO_PIN_REG_25, + GPIO_PIN_REG_26, + GPIO_PIN_REG_27, + 0, + 0, + 0, + 0, + GPIO_PIN_REG_32, + GPIO_PIN_REG_33, + GPIO_PIN_REG_34, + GPIO_PIN_REG_35, + GPIO_PIN_REG_36, + GPIO_PIN_REG_37, + GPIO_PIN_REG_38, + GPIO_PIN_REG_39 +}; + +static int is_valid_gpio(int gpio_num) +{ + if(gpio_num >= GPIO_PIN_COUNT || GPIO_PIN_MUX_REG[gpio_num] == 0) { + GPIO_ERROR("GPIO io_num=%d does not exist\n",gpio_num); + return 0; + } + return 1; +} + +esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + if(intr_type >= GPIO_INTR_MAX) { + GPIO_ERROR("Unknown GPIO intr:%u\n",intr_type); + return ESP_ERR_INVALID_ARG; + } + GPIO.pin[gpio_num].int_type = intr_type; + return ESP_OK; +} + +esp_err_t gpio_intr_enable(gpio_num_t gpio_num) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + if(xPortGetCoreID() == 0) { + GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA; //enable pro cpu intr + } else { + GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA; //enable pro cpu intr + } + return ESP_OK; +} + +esp_err_t gpio_intr_disable(gpio_num_t gpio_num) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + GPIO.pin[gpio_num].int_ena = 0; //disable GPIO intr + return ESP_OK; +} + +static esp_err_t gpio_output_disable(gpio_num_t gpio_num) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + if(gpio_num < 32) { + GPIO.enable_w1tc = (0x1 << gpio_num); + } else { + GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32)); + } + return ESP_OK; +} + +static esp_err_t gpio_output_enable(gpio_num_t gpio_num) +{ + if(gpio_num >= 34) { + GPIO_ERROR("io_num=%d can only be input\n",gpio_num); + return ESP_ERR_INVALID_ARG; + } + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + if(gpio_num < 32) { + GPIO.enable_w1ts = (0x1 << gpio_num); + } else { + GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32)); + } + return ESP_OK; +} + +esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level) +{ + if(!GPIO_IS_VALID_GPIO(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + if(level) { + if(gpio_num < 32) { + GPIO.out_w1ts = (1 << gpio_num); + } else { + GPIO.out1_w1ts.data = (1 << (gpio_num - 32)); + } + } else { + if(gpio_num < 32) { + GPIO.out_w1tc = (1 << gpio_num); + } else { + GPIO.out1_w1tc.data = (1 << (gpio_num - 32)); + } + } + return ESP_OK; +} + +int gpio_get_level(gpio_num_t gpio_num) +{ + if(gpio_num < 32) { + return (GPIO.in >> gpio_num) & 0x1; + } else { + return (GPIO.in1.data >> (gpio_num - 32)) & 0x1; + } +} + +esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + esp_err_t ret = ESP_OK; + switch(pull) { + case GPIO_PULLUP_ONLY: + PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]); + PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]); + break; + case GPIO_PULLDOWN_ONLY: + PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]); + PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]); + break; + case GPIO_PULLUP_PULLDOWN: + PIN_PULLUP_EN(GPIO_PIN_MUX_REG[gpio_num]); + PIN_PULLDWN_EN(GPIO_PIN_MUX_REG[gpio_num]); + break; + case GPIO_FLOATING: + PIN_PULLUP_DIS(GPIO_PIN_MUX_REG[gpio_num]); + PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[gpio_num]); + break; + default: + GPIO_ERROR("Unknown pull up/down mode,gpio_num=%u,pull=%u\n",gpio_num,pull); + ret = ESP_ERR_INVALID_ARG; + break; + } + return ret; +} + +esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) { + GPIO_ERROR("io_num=%d can only be input\n",gpio_num); + return ESP_ERR_INVALID_ARG; + } + esp_err_t ret = ESP_OK; + if(mode & GPIO_MODE_DEF_INPUT) { + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + } else { + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + } + if(mode & GPIO_MODE_DEF_OUTPUT) { + if(gpio_num < 32) { + GPIO.enable_w1ts = (0x1 << gpio_num); + } else { + GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32)); + } + } else { + if(gpio_num < 32) { + GPIO.enable_w1tc = (0x1 << gpio_num); + } else { + GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32)); + } + } + if(mode & GPIO_MODE_DEF_OD) { + GPIO.pin[gpio_num].pad_driver = 1; + } else { + GPIO.pin[gpio_num].pad_driver = 0; + } + return ret; +} + +esp_err_t gpio_config(gpio_config_t *pGPIOConfig) +{ + uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask); + uint32_t io_reg = 0; + uint32_t io_num = 0; + uint64_t bit_valid = 0; + if(pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) { + GPIO_ERROR("GPIO_PIN mask error \n"); + return ESP_ERR_INVALID_ARG; + } + if((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) { + //GPIO 34/35/36/37/38/39 can only be used as input mode; + if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) { + GPIO_ERROR("GPIO34-39 can only be used as input mode\n"); + return ESP_ERR_INVALID_ARG; + } + } + do { + io_reg = GPIO_PIN_MUX_REG[io_num]; + if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) { + GPIO_INFO("Gpio%02d |Mode:",io_num); + if((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) { + GPIO_INFO("INPUT "); + PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]); + } else { + PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]); + } + if((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) { + GPIO_INFO("OD "); + GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */ + } else { + GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */ + } + if((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) { + GPIO_INFO("OUTPUT "); + gpio_output_enable(io_num); + } else { + gpio_output_disable(io_num); + } + GPIO_INFO("|"); + if(pGPIOConfig->pull_up_en) { + GPIO_INFO("PU "); + PIN_PULLUP_EN(io_reg); + } else { + PIN_PULLUP_DIS(io_reg); + } + if(pGPIOConfig->pull_down_en) { + GPIO_INFO("PD "); + PIN_PULLDWN_EN(io_reg); + } else { + PIN_PULLDWN_DIS(io_reg); + } + GPIO_INFO("Intr:%d |\n",pGPIOConfig->intr_type); + gpio_set_intr_type(io_num, pGPIOConfig->intr_type); + if(pGPIOConfig->intr_type) { + gpio_intr_enable(io_num); + } else { + gpio_intr_disable(io_num); + } + PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */ + } else if(bit_valid && (io_reg == 0)) { + GPIO_WARNING("io_num=%d does not exist\n",io_num); + } + io_num++; + } while(io_num < GPIO_PIN_COUNT); + return ESP_OK; +} + +esp_err_t gpio_isr_register(uint32_t gpio_intr_num, void (*fn)(void*), void * arg) +{ + if(fn == NULL) { + return ESP_ERR_INVALID_ARG; + } + ESP_INTR_DISABLE(gpio_intr_num); + intr_matrix_set(xPortGetCoreID(), ETS_GPIO_INTR_SOURCE, gpio_intr_num); + xt_set_interrupt_handler(gpio_intr_num, fn, arg); + ESP_INTR_ENABLE(gpio_intr_num); + return ESP_OK; +} + +/*only level interrupt can be used for wake-up function*/ +esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + esp_err_t ret = ESP_OK; + if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) { + GPIO.pin[gpio_num].int_type = intr_type; + GPIO.pin[gpio_num].wakeup_enable = 0x1; + } else { + GPIO_ERROR("GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u\n",gpio_num); + ret = ESP_ERR_INVALID_ARG; + } + return ret; +} + +esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num) +{ + if(!is_valid_gpio(gpio_num)) { + return ESP_ERR_INVALID_ARG; + } + GPIO.pin[gpio_num].wakeup_enable = 0; + return ESP_OK; +} From df31bb8dfc2d6967a7bfbe122d6024b935802b2b Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Sun, 9 Oct 2016 15:32:08 +0800 Subject: [PATCH 3/3] Rename include, use spaces instead of tabs --- components/esp32/heap_alloc_caps.c | 294 +++++++++--------- .../esp32/include/esp_heap_alloc_caps.h | 34 ++ components/freertos/tasks.c | 1 - 3 files changed, 181 insertions(+), 148 deletions(-) create mode 100644 components/esp32/include/esp_heap_alloc_caps.h diff --git a/components/esp32/heap_alloc_caps.c b/components/esp32/heap_alloc_caps.c index 5b3ec33db..46b1125cc 100644 --- a/components/esp32/heap_alloc_caps.c +++ b/components/esp32/heap_alloc_caps.c @@ -15,7 +15,7 @@ #include -#include "heap_alloc_caps.h" +#include "esp_heap_alloc_caps.h" #include "spiram.h" #include "esp_log.h" @@ -40,23 +40,23 @@ Tag descriptors. These describe the capabilities of a bit of memory that's tagge Each tag contains NO_PRIOS entries; later entries are only taken if earlier ones can't fulfill the memory request. */ static const uint32_t tagDesc[][NO_PRIOS]={ - { MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 }, //Tag 0: Plain ole D-port RAM - { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, //Tag 1: Plain ole D-port RAM which has an alias on the I-port - { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 }, //Tag 2: IRAM - { MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //Tag 3-8: PID 2-7 IRAM - { MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //Tag 9-14: PID 2-7 DRAM - { MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // - { MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // - { MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data - { MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End + { MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 }, //Tag 0: Plain ole D-port RAM + { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, //Tag 1: Plain ole D-port RAM which has an alias on the I-port + { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 }, //Tag 2: IRAM + { MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, //Tag 3-8: PID 2-7 IRAM + { MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, //Tag 9-14: PID 2-7 DRAM + { MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // + { MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT }, // + { MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data + { MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End }; /* @@ -79,81 +79,81 @@ be sorted from low to high start address. This array is *NOT* const because it gets modified depending on what pools are/aren't available. */ static HeapRegionTagged_t regions[]={ - { (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available - { (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code - { (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT - { (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT - { (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0 - { (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1 - { (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2 - { (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3 - { (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4 - { (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5 - { (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6 - { (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7 - { (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8 - { (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9 - { (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10 - { (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11 - { (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12 - { (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13 - { (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14 - { (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15 - { (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1 - { (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0 - { (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump - { (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump - { (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory - { (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory - { (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0 - { (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1 - { (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0 - { (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1 - { (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2 - { (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3 - { (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4 - { (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5 - { (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6 - { (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7 - { (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8 - { (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9 - { (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10 - { (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11 - { (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12 - { (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13 - { (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14 - { (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15 - { NULL, 0, 0, 0} //end + { (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available + { (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code + { (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT + { (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- can be used for BT + { (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0 + { (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1 + { (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2 + { (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3 + { (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4 + { (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5 + { (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6 + { (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7 + { (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8 + { (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9 + { (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10 + { (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11 + { (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12 + { (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13 + { (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14 + { (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15 + { (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1 + { (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0 + { (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump + { (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump + { (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory + { (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory + { (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0 + { (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1 + { (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0 + { (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1 + { (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2 + { (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3 + { (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4 + { (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5 + { (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6 + { (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7 + { (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8 + { (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9 + { (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10 + { (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11 + { (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12 + { (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13 + { (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14 + { (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15 + { NULL, 0, 0, 0} //end }; //Modify regions array to disable the given range of memory. static void disable_mem_region(void *from, void *to) { - int i; - //Align from and to on word boundaries - from=(void*)((uint32_t)from&~3); - to=(void*)(((uint32_t)to+3)&~3); - for (i=0; regions[i].xSizeInBytes!=0; i++) { - void *regStart=regions[i].pucStartAddress; - void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes; - if (regStart>=from && regEnd<=to) { - //Entire region falls in the range. Disable entirely. - regions[i].xTag=-1; - } else if (regStart>=from && regEnd>to && regStartfrom && regEnd<=to) { - //End of the region falls in the range. Modify length. - regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from; - } else if (regStartto) { - //Range punches a hole in the region! We do not support this. - ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i); - regions[i].xTag=-1; //Just disable memory region. That'll teach them! - } - } + int i; + //Align from and to on word boundaries + from=(void*)((uint32_t)from&~3); + to=(void*)(((uint32_t)to+3)&~3); + for (i=0; regions[i].xSizeInBytes!=0; i++) { + void *regStart=regions[i].pucStartAddress; + void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes; + if (regStart>=from && regEnd<=to) { + //Entire region falls in the range. Disable entirely. + regions[i].xTag=-1; + } else if (regStart>=from && regEnd>to && regStartfrom && regEnd<=to) { + //End of the region falls in the range. Modify length. + regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from; + } else if (regStartto) { + //Range punches a hole in the region! We do not support this. + ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i); + regions[i].xTag=-1; //Just disable memory region. That'll teach them! + } + } } @@ -170,52 +170,52 @@ ToDo: The regions are different when stuff like trace memory, BT, ... is used. M Same with loading of apps. Same with using SPI RAM. */ void heap_alloc_caps_init() { - int i; - //Disable the bits of memory where this code is loaded. - disable_mem_region(&_bss_start, &_heap_start); - disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region - disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region - disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region - disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5 + int i; + //Disable the bits of memory where this code is loaded. + disable_mem_region(&_bss_start, &_heap_start); + disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region + disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region + disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region + disable_mem_region((void*)0x40080000, (void*)0x400a0000); //pool 2-5 - // TODO: this region should be checked, since we don't need to knock out all region finally - disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region + // TODO: this region should be checked, since we don't need to knock out all region finally + disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region #if CONFIG_MEMMAP_BT - disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region + disable_mem_region((void*)0x3ffb0000, (void*)0x3ffc0000); //knock out BT data region #endif #if CONFIG_MEMMAP_TRACEMEM - disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region + disable_mem_region((void*)0x3fff8000, (void*)0x40000000); //knock out trace mem region #endif #if 0 - enable_spi_sram(); + enable_spi_sram(); #else - disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed + disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed #endif - //The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory, - //it's useful to coalesce adjacent regions that have the same tag. + //The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory, + //it's useful to coalesce adjacent regions that have the same tag. - for (i=1; regions[i].xSizeInBytes!=0; i++) { - if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) && - regions[i].xTag == regions[i-1].xTag ) { - regions[i-1].xTag=-1; - regions[i].pucStartAddress=regions[i-1].pucStartAddress; - regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes; - } - } + for (i=1; regions[i].xSizeInBytes!=0; i++) { + if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) && + regions[i].xTag == regions[i-1].xTag ) { + regions[i-1].xTag=-1; + regions[i].pucStartAddress=regions[i-1].pucStartAddress; + regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes; + } + } - ESP_EARLY_LOGI(TAG, "Initializing heap allocator:"); - for (i=0; regions[i].xSizeInBytes!=0; i++) { - if (regions[i].xTag != -1) { - ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i, - (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag); - } - } - //Initialize the malloc implementation. - vPortDefineHeapRegionsTagged( regions ); + ESP_EARLY_LOGI(TAG, "Initializing heap allocator:"); + for (i=0; regions[i].xSizeInBytes!=0; i++) { + if (regions[i].xTag != -1) { + ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i, + (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag); + } + } + //Initialize the malloc implementation. + vPortDefineHeapRegionsTagged( regions ); } /* @@ -223,7 +223,7 @@ Standard malloc() implementation. Will return ho-hum byte-accessible data memory */ void *pvPortMalloc( size_t xWantedSize ) { - return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT ); + return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT ); } /* @@ -231,30 +231,30 @@ Routine to allocate a bit of memory with certain capabilities. caps is a bitfiel */ void *pvPortMallocCaps( size_t xWantedSize, uint32_t caps ) { - int prio; - int tag, j; - void *ret=NULL; - uint32_t remCaps; - for (prio=0; prio