From 897e69cc9d94fa1070db0eba613ac502f0e1f990 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 17 Apr 2020 18:54:12 +0200 Subject: [PATCH 1/3] soc, esp32s2: add usb_wrap peripheral --- components/esp32s2/ld/esp32s2.peripherals.ld | 2 +- .../soc/soc/esp32s2/include/soc/usb_periph.h | 4 +- .../soc/soc/esp32s2/include/soc/usb_pins.h | 5 + .../soc/esp32s2/include/soc/usb_wrap_reg.h | 254 ++++++++++ .../soc/esp32s2/include/soc/usb_wrap_struct.h | 443 ++++++++++++++++++ 5 files changed, 706 insertions(+), 2 deletions(-) create mode 100644 components/soc/soc/esp32s2/include/soc/usb_wrap_reg.h create mode 100644 components/soc/soc/esp32s2/include/soc/usb_wrap_struct.h diff --git a/components/esp32s2/ld/esp32s2.peripherals.ld b/components/esp32s2/ld/esp32s2.peripherals.ld index 8778b1006..0c364f92e 100644 --- a/components/esp32s2/ld/esp32s2.peripherals.ld +++ b/components/esp32s2/ld/esp32s2.peripherals.ld @@ -27,4 +27,4 @@ PROVIDE ( I2C1 = 0x3f427000 ); PROVIDE ( CAN = 0x3f42B000 ); PROVIDE ( APB_SARADC = 0x3f440000 ); PROVIDE ( USB0 = 0x60080000 ); -PROVIDE ( ToBeCleanedUpBelow = 0x00000000 ); +PROVIDE ( USB_WRAP = 0x3f439000 ); diff --git a/components/soc/soc/esp32s2/include/soc/usb_periph.h b/components/soc/soc/esp32s2/include/soc/usb_periph.h index db9ae6155..782e5ad24 100644 --- a/components/soc/soc/esp32s2/include/soc/usb_periph.h +++ b/components/soc/soc/esp32s2/include/soc/usb_periph.h @@ -21,9 +21,11 @@ #include "soc/usb_reg.h" #include "soc/usb_types.h" #include "soc/usb_struct.h" +#include "soc/usb_wrap_reg.h" +#include "soc/usb_wrap_struct.h" /** - * @brief A pin decriptor for init + * @brief A pin descriptor for init */ typedef struct { const int pin; diff --git a/components/soc/soc/esp32s2/include/soc/usb_pins.h b/components/soc/soc/esp32s2/include/soc/usb_pins.h index ed70069a1..c8ad806e0 100644 --- a/components/soc/soc/esp32s2/include/soc/usb_pins.h +++ b/components/soc/soc/esp32s2/include/soc/usb_pins.h @@ -14,9 +14,14 @@ #pragma once +/* GPIOs used to connect an external USB PHY */ #define USBPHY_VP_NUM 33 #define USBPHY_VM_NUM 34 #define USBPHY_RCV_NUM 35 #define USBPHY_OEN_NUM 36 #define USBPHY_VPO_NUM 37 #define USBPHY_VMO_NUM 38 + +/* GPIOs corresponding to the pads of the internal USB PHY */ +#define USBPHY_DP_NUM 20 +#define USBPHY_DM_NUM 19 diff --git a/components/soc/soc/esp32s2/include/soc/usb_wrap_reg.h b/components/soc/soc/esp32s2/include/soc/usb_wrap_reg.h new file mode 100644 index 000000000..7348c7eb9 --- /dev/null +++ b/components/soc/soc/esp32s2/include/soc/usb_wrap_reg.h @@ -0,0 +1,254 @@ +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** USB_WRAP_OTG_CONF_REG register + * PAD/DFIFO/PHY configuration register. + */ +#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0) +/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software override of srp session end signal.1'b0: + * the signal is controlled by the chip input.1'b1: the signal is controlled by the + * software. + */ +#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0)) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S) +#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001 +#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0 +/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0; + * Software override value of srp session end signal. + */ +#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1)) +#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S) +#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001 +#define USB_WRAP_SRP_SESSEND_VALUE_S 1 +/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0; + * Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY + */ +#define USB_WRAP_PHY_SEL (BIT(2)) +#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S) +#define USB_WRAP_PHY_SEL_V 0x00000001 +#define USB_WRAP_PHY_SEL_S 2 +/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PD (BIT(3)) +#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S) +#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001 +#define USB_WRAP_DFIFO_FORCE_PD_S 3 +/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid. + */ +#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4)) +#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S) +#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001 +#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4 +/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0; + * Enable software to control USB D+ D- exchange + */ +#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5)) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S) +#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001 +#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5 +/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0; + * USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-. + */ +#define USB_WRAP_EXCHG_PINS (BIT(6)) +#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S) +#define USB_WRAP_EXCHG_PINS_V 0x00000001 +#define USB_WRAP_EXCHG_PINS_S 6 +/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold. + */ +#define USB_WRAP_VREFH 0x00000003 +#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S) +#define USB_WRAP_VREFH_V 0x00000003 +#define USB_WRAP_VREFH_S 7 +/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold. + */ +#define USB_WRAP_VREFL 0x00000003 +#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S) +#define USB_WRAP_VREFL_V 0x00000003 +#define USB_WRAP_VREFL_S 9 +/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0; + * Enable software to control input threshold. + */ +#define USB_WRAP_VREF_OVERRIDE (BIT(11)) +#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S) +#define USB_WRAP_VREF_OVERRIDE_V 0x00000001 +#define USB_WRAP_VREF_OVERRIDE_S 11 +/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0; + * Enable software to control USB pad in pullup or pulldown mode. + */ +#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12)) +#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S) +#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001 +#define USB_WRAP_PAD_PULL_OVERRIDE_S 12 +/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0; + * Control USB D+ pullup. + */ +#define USB_WRAP_DP_PULLUP (BIT(13)) +#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S) +#define USB_WRAP_DP_PULLUP_V 0x00000001 +#define USB_WRAP_DP_PULLUP_S 13 +/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0; + * Control USB D+ pulldown. + */ +#define USB_WRAP_DP_PULLDOWN (BIT(14)) +#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S) +#define USB_WRAP_DP_PULLDOWN_V 0x00000001 +#define USB_WRAP_DP_PULLDOWN_S 14 +/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0; + * Control USB D+ pullup. + */ +#define USB_WRAP_DM_PULLUP (BIT(15)) +#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S) +#define USB_WRAP_DM_PULLUP_V 0x00000001 +#define USB_WRAP_DM_PULLUP_S 15 +/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0; + * Control USB D+ pulldown. + */ +#define USB_WRAP_DM_PULLDOWN (BIT(16)) +#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S) +#define USB_WRAP_DM_PULLDOWN_V 0x00000001 +#define USB_WRAP_DM_PULLDOWN_S 16 +/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0; + * Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K. + */ +#define USB_WRAP_PULLUP_VALUE (BIT(17)) +#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S) +#define USB_WRAP_PULLUP_VALUE_V 0x00000001 +#define USB_WRAP_PULLUP_VALUE_S 17 +/** USB_WRAP_PAD_ENABLE : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ +#define USB_WRAP_PAD_ENABLE (BIT(18)) +#define USB_WRAP_PAD_ENABLE_M (USB_WRAP_PAD_ENABLE_V << USB_WRAP_PAD_ENABLE_S) +#define USB_WRAP_PAD_ENABLE_V 0x00000001 +#define USB_WRAP_PAD_ENABLE_S 18 +/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 1; + * Force AHB clock always on. + */ +#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19)) +#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S) +#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001 +#define USB_WRAP_AHB_CLK_FORCE_ON_S 19 +/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1; + * Force PHY clock always on. + */ +#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20)) +#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S) +#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001 +#define USB_WRAP_PHY_CLK_FORCE_ON_S 20 +/** USB_WRAP_PHY_TX_EDGE_SEL : R/W; bitpos: [21]; default: 0; + * Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge. + */ +#define USB_WRAP_PHY_TX_EDGE_SEL (BIT(21)) +#define USB_WRAP_PHY_TX_EDGE_SEL_M (USB_WRAP_PHY_TX_EDGE_SEL_V << USB_WRAP_PHY_TX_EDGE_SEL_S) +#define USB_WRAP_PHY_TX_EDGE_SEL_V 0x00000001 +#define USB_WRAP_PHY_TX_EDGE_SEL_S 21 +/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ +#define USB_WRAP_DFIFO_FORCE_PU (BIT(22)) +#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S) +#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001 +#define USB_WRAP_DFIFO_FORCE_PU_S 22 +/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ +#define USB_WRAP_CLK_EN (BIT(31)) +#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S) +#define USB_WRAP_CLK_EN_V 0x00000001 +#define USB_WRAP_CLK_EN_S 31 + +/** USB_WRAP_TEST_CONF_REG register + * TEST relative configuration registers. + */ +#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4) +/** USB_WRAP_TEST_ENABLE : R/W; bitpos: [0]; default: 0; + * Enable to test the USB pad. + */ +#define USB_WRAP_TEST_ENABLE (BIT(0)) +#define USB_WRAP_TEST_ENABLE_M (USB_WRAP_TEST_ENABLE_V << USB_WRAP_TEST_ENABLE_S) +#define USB_WRAP_TEST_ENABLE_V 0x00000001 +#define USB_WRAP_TEST_ENABLE_S 0 +/** USB_WRAP_TEST_USB_WRAP_OE : R/W; bitpos: [1]; default: 0; + * USB pad oen in test. + */ +#define USB_WRAP_TEST_USB_WRAP_OE (BIT(1)) +#define USB_WRAP_TEST_USB_WRAP_OE_M (USB_WRAP_TEST_USB_WRAP_OE_V << USB_WRAP_TEST_USB_WRAP_OE_S) +#define USB_WRAP_TEST_USB_WRAP_OE_V 0x00000001 +#define USB_WRAP_TEST_USB_WRAP_OE_S 1 +/** USB_WRAP_TEST_TX_DP : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test. + */ +#define USB_WRAP_TEST_TX_DP (BIT(2)) +#define USB_WRAP_TEST_TX_DP_M (USB_WRAP_TEST_TX_DP_V << USB_WRAP_TEST_TX_DP_S) +#define USB_WRAP_TEST_TX_DP_V 0x00000001 +#define USB_WRAP_TEST_TX_DP_S 2 +/** USB_WRAP_TEST_TX_DM : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test. + */ +#define USB_WRAP_TEST_TX_DM (BIT(3)) +#define USB_WRAP_TEST_TX_DM_M (USB_WRAP_TEST_TX_DM_V << USB_WRAP_TEST_TX_DM_S) +#define USB_WRAP_TEST_TX_DM_V 0x00000001 +#define USB_WRAP_TEST_TX_DM_S 3 +/** USB_WRAP_TEST_RX_RCV : RO; bitpos: [4]; default: 0; + * USB differential rx value in test. + */ +#define USB_WRAP_TEST_RX_RCV (BIT(4)) +#define USB_WRAP_TEST_RX_RCV_M (USB_WRAP_TEST_RX_RCV_V << USB_WRAP_TEST_RX_RCV_S) +#define USB_WRAP_TEST_RX_RCV_V 0x00000001 +#define USB_WRAP_TEST_RX_RCV_S 4 +/** USB_WRAP_TEST_RX_DP : RO; bitpos: [5]; default: 0; + * USB D+ rx value in test. + */ +#define USB_WRAP_TEST_RX_DP (BIT(5)) +#define USB_WRAP_TEST_RX_DP_M (USB_WRAP_TEST_RX_DP_V << USB_WRAP_TEST_RX_DP_S) +#define USB_WRAP_TEST_RX_DP_V 0x00000001 +#define USB_WRAP_TEST_RX_DP_S 5 +/** USB_WRAP_TEST_RX_DM : RO; bitpos: [6]; default: 0; + * USB D- rx value in test. + */ +#define USB_WRAP_TEST_RX_DM (BIT(6)) +#define USB_WRAP_TEST_RX_DM_M (USB_WRAP_TEST_RX_DM_V << USB_WRAP_TEST_RX_DM_S) +#define USB_WRAP_TEST_RX_DM_V 0x00000001 +#define USB_WRAP_TEST_RX_DM_S 6 + +/** USB_WRAP_DATE_REG register + * Version register. + */ +#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc) +/** USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 419631616; + * data register. + */ +#define USB_WRAP_DATE 0xFFFFFFFF +#define USB_WRAP_DATE_M (USB_WRAP_DATE_V << USB_WRAP_DATE_S) +#define USB_WRAP_DATE_V 0xFFFFFFFF +#define USB_WRAP_DATE_S 0 + +#ifdef __cplusplus +} +#endif + + diff --git a/components/soc/soc/esp32s2/include/soc/usb_wrap_struct.h b/components/soc/soc/esp32s2/include/soc/usb_wrap_struct.h new file mode 100644 index 000000000..42a4b355e --- /dev/null +++ b/components/soc/soc/esp32s2/include/soc/usb_wrap_struct.h @@ -0,0 +1,443 @@ +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Control/Status registers */ +/** Type of otg_conf register + * PAD/DFIFO/PHY configuration register. + */ +typedef union { + struct { + /** srp_sessend_override : R/W; bitpos: [0]; default: 0; + * This bit is used to enable the software override of srp session end signal.1'b0: + * the signal is controlled by the chip input.1'b1: the signal is controlled by the + * software. + */ + uint32_t srp_sessend_override:1; + /** srp_sessend_value : R/W; bitpos: [1]; default: 0; + * Software override value of srp session end signal. + */ + uint32_t srp_sessend_value:1; + /** phy_sel : R/W; bitpos: [2]; default: 0; + * Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY + */ + uint32_t phy_sel:1; + /** dfifo_force_pd : R/W; bitpos: [3]; default: 0; + * Force the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pd:1; + /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0; + * Bypass Debounce filters for avalid. + */ + uint32_t dbnce_fltr_bypass:1; + /** exchg_pins_override : R/W; bitpos: [5]; default: 0; + * Enable software to control USB D+ D- exchange + */ + uint32_t exchg_pins_override:1; + /** exchg_pins : R/W; bitpos: [6]; default: 0; + * USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-. + */ + uint32_t exchg_pins:1; + /** vrefh : R/W; bitpos: [8:7]; default: 0; + * Control single-end input high threshold. + */ + uint32_t vrefh:2; + /** vrefl : R/W; bitpos: [10:9]; default: 0; + * Control single-end input low threshold. + */ + uint32_t vrefl:2; + /** vref_override : R/W; bitpos: [11]; default: 0; + * Enable software to control input threshold. + */ + uint32_t vref_override:1; + /** pad_pull_override : R/W; bitpos: [12]; default: 0; + * Enable software to control USB pad in pullup or pulldown mode. + */ + uint32_t pad_pull_override:1; + /** dp_pullup : R/W; bitpos: [13]; default: 0; + * Control USB D+ pullup. + */ + uint32_t dp_pullup:1; + /** dp_pulldown : R/W; bitpos: [14]; default: 0; + * Control USB D+ pulldown. + */ + uint32_t dp_pulldown:1; + /** dm_pullup : R/W; bitpos: [15]; default: 0; + * Control USB D+ pullup. + */ + uint32_t dm_pullup:1; + /** dm_pulldown : R/W; bitpos: [16]; default: 0; + * Control USB D+ pulldown. + */ + uint32_t dm_pulldown:1; + /** pullup_value : R/W; bitpos: [17]; default: 0; + * Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K. + */ + uint32_t pullup_value:1; + /** pad_enable : R/W; bitpos: [18]; default: 0; + * Enable USB pad function. + */ + uint32_t pad_enable:1; + /** ahb_clk_force_on : R/W; bitpos: [19]; default: 1; + * Force AHB clock always on. + */ + uint32_t ahb_clk_force_on:1; + /** phy_clk_force_on : R/W; bitpos: [20]; default: 1; + * Force PHY clock always on. + */ + uint32_t phy_clk_force_on:1; + /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0; + * Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge. + */ + uint32_t phy_tx_edge_sel:1; + /** dfifo_force_pu : R/W; bitpos: [22]; default: 0; + * Disable the dfifo to go into low power mode. The data in dfifo will not lost. + */ + uint32_t dfifo_force_pu:1; + uint32_t reserved_23:8; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Disable auto clock gating of CSR registers. + */ + uint32_t clk_en:1; + }; + uint32_t val; +} usb_wrap_otg_conf_reg_t; + +/** Type of test_conf register + * TEST relative configuration registers. + */ +typedef union { + struct { + /** test_enable : R/W; bitpos: [0]; default: 0; + * Enable to test the USB pad. + */ + uint32_t test_enable:1; + /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0; + * USB pad oen in test. + */ + uint32_t test_usb_wrap_oe:1; + /** test_tx_dp : R/W; bitpos: [2]; default: 0; + * USB D+ tx value in test. + */ + uint32_t test_tx_dp:1; + /** test_tx_dm : R/W; bitpos: [3]; default: 0; + * USB D- tx value in test. + */ + uint32_t test_tx_dm:1; + /** test_rx_rcv : RO; bitpos: [4]; default: 0; + * USB differential rx value in test. + */ + uint32_t test_rx_rcv:1; + /** test_rx_dp : RO; bitpos: [5]; default: 0; + * USB D+ rx value in test. + */ + uint32_t test_rx_dp:1; + /** test_rx_dm : RO; bitpos: [6]; default: 0; + * USB D- rx value in test. + */ + uint32_t test_rx_dm:1; + }; + uint32_t val; +} usb_wrap_test_conf_reg_t; + + +/** Status registers */ +/** Type of date register + * Version register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 419631616; + * data register. + */ + uint32_t date:32; + }; + uint32_t val; +} usb_wrap_date_reg_t; + + +typedef struct { + volatile usb_wrap_otg_conf_reg_t otg_conf; + volatile usb_wrap_test_conf_reg_t test_conf; + uint32_t reserved_008; + uint32_t reserved_00c; + uint32_t reserved_010; + uint32_t reserved_014; + uint32_t reserved_018; + uint32_t reserved_01c; + uint32_t reserved_020; + uint32_t reserved_024; + uint32_t reserved_028; + uint32_t reserved_02c; + uint32_t reserved_030; + uint32_t reserved_034; + uint32_t reserved_038; + uint32_t reserved_03c; + uint32_t reserved_040; + uint32_t reserved_044; + uint32_t reserved_048; + uint32_t reserved_04c; + uint32_t reserved_050; + uint32_t reserved_054; + uint32_t reserved_058; + uint32_t reserved_05c; + uint32_t reserved_060; + uint32_t reserved_064; + uint32_t reserved_068; + uint32_t reserved_06c; + uint32_t reserved_070; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + uint32_t reserved_0fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + volatile usb_wrap_date_reg_t date; +} usb_wrap_dev_t; + +_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size"); + +extern usb_wrap_dev_t USB_WRAP; + +#ifdef __cplusplus +} +#endif + + From d311144a00762deb023a73e2580fd0beeed78ed0 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 17 Apr 2020 18:56:09 +0200 Subject: [PATCH 2/3] soc/usb: use new headers in LL, move some code out of LL * Keep only USB related register operations in the LL. * Move pad-related logic into the driver. * Driver is now responsible for enabling the peripheral. --- .../soc/src/esp32s2/include/hal/usb_ll.h | 58 +++++++------------ components/soc/src/esp32s2/usb_hal.c | 7 ++- components/tinyusb/CMakeLists.txt | 2 +- components/tinyusb/port/esp32s2/src/tinyusb.c | 33 +++++++++++ 4 files changed, 60 insertions(+), 40 deletions(-) diff --git a/components/soc/src/esp32s2/include/hal/usb_ll.h b/components/soc/src/esp32s2/include/hal/usb_ll.h index 001fa071a..5496d7a6d 100644 --- a/components/soc/src/esp32s2/include/hal/usb_ll.h +++ b/components/soc/src/esp32s2/include/hal/usb_ll.h @@ -15,46 +15,28 @@ #include "soc/soc.h" #include "soc/system_reg.h" -#include "esp32s2/rom/gpio.h" #include "soc/gpio_sig_map.h" #include "soc/usb_periph.h" -void gpio_pad_input_enable(uint32_t pin); - -static inline void usb_ll_init(bool external_phy) +static inline void usb_ll_int_phy_enable(void) { - REG_SET_BIT(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN); - REG_CLR_BIT(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST); - - if (external_phy) { - REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(18)); //set usb_pad_enable - REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(2)); // set reg_phy_sel (external phy) - gpio_output_set_high(0x10, 0, 0x1E, 0xE); - } else { - REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(18)); //set usb_pad_enable - REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(2)); // clear reg_phy_sel (internal phy) - //drive strength needs to be 3 for full speed - REG_SET_FIELD(GPIO_PIN19_REG, GPIO_PIN19_PAD_DRIVER, 3); - REG_SET_FIELD(GPIO_PIN20_REG, GPIO_PIN20_PAD_DRIVER, 3); - } - - int i = 0; - while (usb_periph_iopins[i].pin != -1) { - if ((external_phy) || (usb_periph_iopins[i].ext_phy_only == 0)) { - gpio_pad_select_gpio(usb_periph_iopins[i].pin); - if (usb_periph_iopins[i].is_output) { - gpio_matrix_out(usb_periph_iopins[i].pin, usb_periph_iopins[i].func, false, false); - } else { - gpio_matrix_in(usb_periph_iopins[i].pin, usb_periph_iopins[i].func, false); - gpio_pad_input_enable(usb_periph_iopins[i].pin); - } - gpio_pad_unhold(usb_periph_iopins[i].pin); - } - i++; - } - REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(12)); //pull override - REG_SET_BIT(DR_REG_USB_WRAP_BASE, BIT(13)); //dp pullup - REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(14)); //dp pulldwn - REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(15)); //dm pullup - REG_CLR_BIT(DR_REG_USB_WRAP_BASE, BIT(16)); //dm pulldown + USB_WRAP.otg_conf.pad_enable = 1; + USB_WRAP.otg_conf.phy_sel = 0; +} + +static inline void usb_ll_ext_phy_enable(void) +{ + USB_WRAP.otg_conf.pad_enable = 1; + USB_WRAP.otg_conf.phy_sel = 1; +} + +static inline void usb_ll_int_phy_pullup_conf(bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd) +{ + usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; + conf.pad_pull_override = 1; + conf.dp_pullup = dp_pu; + conf.dp_pulldown = dp_pd; + conf.dm_pullup = dm_pu; + conf.dm_pulldown = dp_pd; + USB_WRAP.otg_conf = conf; } diff --git a/components/soc/src/esp32s2/usb_hal.c b/components/soc/src/esp32s2/usb_hal.c index f3cdbeed4..c0188804c 100644 --- a/components/soc/src/esp32s2/usb_hal.c +++ b/components/soc/src/esp32s2/usb_hal.c @@ -18,5 +18,10 @@ void usb_hal_init(usb_hal_context_t *usb) { - usb_ll_init(usb->use_external_phy); + if (usb->use_external_phy) { + usb_ll_ext_phy_enable(); + } else { + usb_ll_int_phy_enable(); + usb_ll_int_phy_pullup_conf(true, false, false, false); + } } diff --git a/components/tinyusb/CMakeLists.txt b/components/tinyusb/CMakeLists.txt index aff0b97ec..fc8dd5019 100644 --- a/components/tinyusb/CMakeLists.txt +++ b/components/tinyusb/CMakeLists.txt @@ -1,4 +1,4 @@ -idf_component_register( REQUIRES esp_rom freertos soc) +idf_component_register(REQUIRES esp_rom freertos soc driver) if(CONFIG_USB_ENABLED) idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH) diff --git a/components/tinyusb/port/esp32s2/src/tinyusb.c b/components/tinyusb/port/esp32s2/src/tinyusb.c index 1e46cf24d..6c5792a99 100644 --- a/components/tinyusb/port/esp32s2/src/tinyusb.c +++ b/components/tinyusb/port/esp32s2/src/tinyusb.c @@ -14,6 +14,35 @@ #include "tinyusb.h" #include "hal/usb_hal.h" +#include "soc/usb_periph.h" +#include "driver/periph_ctrl.h" +#include "driver/gpio.h" +#include "esp32s2/rom/gpio.h" + +static void configure_pins(usb_hal_context_t *usb) +{ + /* usb_periph_iopins currently configures USB_OTG as USB Device. + * Introduce additional parameters in usb_hal_context_t when adding support + * for USB Host. + */ + for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { + if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { + gpio_pad_select_gpio(iopin->pin); + if (iopin->is_output) { + gpio_matrix_out(iopin->pin, iopin->func, false, false); + } else { + gpio_matrix_in(iopin->pin, iopin->func, false); + gpio_pad_input_enable(iopin->pin); + } + gpio_pad_unhold(iopin->pin); + } + } + if (!usb->use_external_phy) { + gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + } +} + /** * @brief Initializes the tinyUSB driver. @@ -31,11 +60,15 @@ esp_err_t tinyusb_driver_install(const tinyusb_config_t *config) tusb_desc_device_t *descriptor; char **string_descriptor; + periph_module_reset(PERIPH_USB_MODULE); + periph_module_enable(PERIPH_USB_MODULE); + // Hal init usb_hal_context_t hal = { .use_external_phy = config->external_phy }; usb_hal_init(&hal); + configure_pins(&hal); if (config->descriptor == NULL) { descriptor = &descriptor_kconfig; From e0177eb252a434c8ce851c3744f88645092e3c12 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 17 Apr 2020 18:59:56 +0200 Subject: [PATCH 3/3] examples/tusb_sample_descriptor: default to esp32s2 target --- .../peripherals/usb/tusb_sample_descriptor/sdkconfig.defaults | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/peripherals/usb/tusb_sample_descriptor/sdkconfig.defaults b/examples/peripherals/usb/tusb_sample_descriptor/sdkconfig.defaults index 740f05f90..4d3be6399 100644 --- a/examples/peripherals/usb/tusb_sample_descriptor/sdkconfig.defaults +++ b/examples/peripherals/usb/tusb_sample_descriptor/sdkconfig.defaults @@ -1,5 +1,6 @@ +CONFIG_IDF_TARGET="esp32s2" CONFIG_USB_ENABLED=y CONFIG_USB_DESC_USE_ESPRESSIF_VID=n CONFIG_USB_DESC_CUSTOM_VID=0x303A CONFIG_USB_DESC_USE_DEFAULT_PID=n -CONFIG_USB_DESC_CUSTOM_PID=0x3000 \ No newline at end of file +CONFIG_USB_DESC_CUSTOM_PID=0x3000