intr_alloc: mark inline asm operand as earlyclobber

When compiling in release mode, compiler was choosing same register for
oldint and intmask variables, so INTENABLE was never modified.
This effectively broke disabling of non-IRAM interrupts during flash
operations, observed in the existing tests if task watchdog is enabled.
This change adds an extra constraint tells the compiler that output
operand should not be placed into the same register as an input one.

components/esp32/intr_alloc.c

@@ -700,7 +700,7 @@ void esp_intr_noniram_disable()
         "and a3,%0,%1\n"        //mask ints that need disabling
         "wsr a3,INTENABLE\n"    //write back
         "rsync\n"
-        :"=r"(oldint):"r"(intmask):"a3");
+        :"=&r"(oldint):"r"(intmask):"a3");
     //Save which ints we did disable
     non_iram_int_disabled[cpu]=oldint&non_iram_int_mask[cpu];
 }