spi: simplify the caps header
The mapping logic from register address to instance number is moved into the LL
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dae3196157
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@ -60,8 +60,8 @@
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//#define SOC_SPI_SUPPORT_CD_SIG
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) 1
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})
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// Peripheral doesn't support output given level during its "dummy phase"
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) 0
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_host) ({(void)spi_host; 0;})
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@ -47,20 +47,11 @@
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#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct spi_dev_s;
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extern volatile struct spi_dev_s GPSPI3;
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struct spi_mem_dev_s;
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extern volatile struct spi_mem_dev_s SPIMEM1;
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#ifdef __cplusplus
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}
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#endif
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3))
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// VSPI (SPI3) only support 1-bit mode
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
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// Peripheral supports output given level during its "dummy phase"
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) ((void*)spi_dev == (void*)&SPIMEM1)
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// Only SPI1 supports this feature
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id) ((host_id) == 0)
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@ -43,7 +43,16 @@ extern "C" {
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#define SPI_FLASH_LL_CLKREG_VAL_80MHZ ((spi_flash_ll_clock_reg_t){.val=0x80000000}) ///< Clock set to 80 MHz
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/// Get the start address of SPI peripheral registers by the host ID
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#define spi_flash_ll_get_hw(host_id) ((host_id)==SPI1_HOST? &SPI1:((host_id)==SPI2_HOST?&SPI2:((host_id)==SPI3_HOST?&SPI3:({abort();(spi_dev_t*)0;}))))
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#define spi_flash_ll_get_hw(host_id) ( ((host_id)==SPI1_HOST) ? &SPI1 :(\
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((host_id)==SPI2_HOST) ? &SPI2 :(\
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((host_id)==SPI3_HOST) ? &SPI3 :(\
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{abort();(spi_dev_t*)0;}\
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))) )
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#define spi_flash_ll_hw_get_id(dev) ( ((dev) == &SPI1) ? SPI1_HOST :(\
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((dev) == &SPI2) ? SPI2_HOST :(\
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((dev) == &SPI3) ? SPI3_HOST :(\
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-1\
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))) )
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/// Empty function to be compatible with new version chips.
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#define spi_flash_ll_set_dummy_out(dev, out_en, out_lev)
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@ -34,9 +34,14 @@
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extern "C" {
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#endif
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#define gpspi_flash_ll_get_hw(host_id) (((host_id)==SPI2_HOST ? &GPSPI2 \
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: ((host_id)==SPI3_HOST ? &GPSPI3 \
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: ({abort();(spi_dev_t*)0;}))))
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#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : (\
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((host_id)==SPI3_HOST) ? &GPSPI3 : (\
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{abort();(spi_dev_t*)0;}\
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)) )
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#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : (\
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((dev) == (void*)&GPSPI3) ? SPI3_HOST : (\
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-1 \
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)) )
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typedef typeof(GPSPI2.clock) gpspi_flash_ll_clock_reg_t;
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@ -41,6 +41,12 @@ extern "C" {
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#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
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: gpspi_flash_ll_get_hw(host_id)))
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#define spi_flash_ll_hw_get_id(dev) ({int dev_id = spimem_flash_ll_hw_get_id(dev); \
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if (dev_id < 0) {\
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dev_id = gpspi_flash_ll_hw_get_id(dev);\
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}\
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dev_id; \
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})
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typedef union {
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gpspi_flash_ll_clock_reg_t gpspi;
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@ -35,7 +35,8 @@
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extern "C" {
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#endif
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#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL ))
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#define spimem_flash_ll_get_hw(host_id) (((host_id)==SPI1_HOST ? &SPIMEM1 : NULL ))
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#define spimem_flash_ll_hw_get_id(dev) ((dev) == (void*)&SPIMEM1? SPI1_HOST: -1)
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typedef typeof(SPIMEM1.clock) spimem_flash_ll_clock_reg_t;
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@ -51,11 +51,12 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
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esp_flash_io_mode_t io_mode)
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{
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spi_dev_t *dev = get_spi_dev(host);
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int host_id = spi_flash_ll_hw_get_id(dev);
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if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(dev) && io_mode > SPI_FLASH_FASTRD) {
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if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) {
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return ESP_ERR_NOT_SUPPORTED;
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}
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if (addr_bitlen > 24 && SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(dev)) {
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if (addr_bitlen > 24 && SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id)) {
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/*
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* The extra address bits (24-addr_bitlen) are used to control the M7-M0 bits right after
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* the address field, to avoid the flash going into continuous read mode.
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