Merge branch 'bugfix/fix_16mbit_psram_id_read_error_v4.2' into 'release/v4.2'
psram: fix 16mbit psram id read error (backport v4.2) See merge request espressif/esp-idf!9424
This commit is contained in:
commit
f52c35258c
2 changed files with 32 additions and 13 deletions
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@ -397,11 +397,9 @@ static void psram_disable_qio_mode(psram_spi_num_t spi_num)
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psram_cmd_end(spi_num);
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psram_cmd_end(spi_num);
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}
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}
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//read psram id
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//read psram id, should issue `psram_disable_qio_mode` before calling this
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static void psram_read_id(uint64_t* dev_id)
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static void psram_read_id(psram_spi_num_t spi_num, uint64_t* dev_id)
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{
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{
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psram_spi_num_t spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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uint32_t dummy_bits = 0 + extra_dummy;
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uint32_t dummy_bits = 0 + extra_dummy;
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uint32_t psram_id[2] = {0};
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uint32_t psram_id[2] = {0};
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psram_cmd_t ps_cmd;
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psram_cmd_t ps_cmd;
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@ -900,9 +898,20 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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bootloader_common_vddsdio_configure();
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bootloader_common_vddsdio_configure();
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// GPIO related settings
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// GPIO related settings
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psram_gpio_config(&psram_io, mode);
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psram_gpio_config(&psram_io, mode);
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psram_read_id(&s_psram_id);
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psram_spi_num_t spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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psram_read_id(spi_num, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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if (!PSRAM_IS_VALID(s_psram_id)) {
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return ESP_FAIL;
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/* 16Mbit psram ID read error workaround:
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* treat the first read id as a dummy one as the pre-condition,
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* Send Read ID command again
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*/
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psram_read_id(spi_num, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", (uint32_t)s_psram_id);
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return ESP_FAIL;
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}
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}
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}
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if (psram_is_32mbit_ver0()) {
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if (psram_is_32mbit_ver0()) {
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@ -47,6 +47,8 @@
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM
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#include "soc/rtc.h"
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#include "soc/rtc.h"
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static const char* TAG = "psram";
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//Commands for PSRAM chip
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ 0x0B
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@ -150,7 +152,6 @@ typedef struct {
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.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \
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.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \
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}
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}
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//static const char* TAG = "psram";
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typedef enum {
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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PSRAM_SPI_1 = 0x1,
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/* PSRAM_SPI_2, */
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/* PSRAM_SPI_2, */
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@ -305,11 +306,9 @@ bool psram_support_wrap_size(uint32_t wrap_size)
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}
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}
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//read psram id
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//read psram id, should issue `psram_disable_qio_mode` before calling this
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static void psram_read_id(uint32_t* dev_id)
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static void psram_read_id(int spi_num, uint32_t* dev_id)
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{
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{
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int spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
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PSRAM_DEVICE_ID, 8, /* command and command bit len*/
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PSRAM_DEVICE_ID, 8, /* command and command bit len*/
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0, 24, /* address and address bit len*/
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0, 24, /* address and address bit len*/
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@ -431,9 +430,20 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
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/* SPI1: set cs timing(hold time) in order to send commands on SPI1 */
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/* SPI1: set cs timing(hold time) in order to send commands on SPI1 */
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psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
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psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
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psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
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psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
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psram_read_id(&s_psram_id);
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int spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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psram_read_id(spi_num, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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if (!PSRAM_IS_VALID(s_psram_id)) {
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return ESP_FAIL;
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/* 16Mbit psram ID read error workaround:
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* treat the first read id as a dummy one as the pre-condition,
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* Send Read ID command again
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*/
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psram_read_id(spi_num, &s_psram_id);
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if (!PSRAM_IS_VALID(s_psram_id)) {
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ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
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return ESP_FAIL;
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}
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}
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}
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psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX;
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psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX;
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