Crash_Override/OVMS3-idf
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

ld: add ld for bt/trace, choose different ld by menuconfig

Browse source
This commit is contained in:
Wu Jian Gang 2016-08-19 18:45:49 +08:00
parent 3e8bb67e75
commit ef36779bd3
4 changed files with 60 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
components/esp32/Makefile
View file

@ -6,16 +6,32 @@
# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
# please read the esp-idf build system document if you need to do this.
#
-include $(PROJECT_PATH)/build/include/config/auto.conf
LIBS := crypto core net80211 phy rtc pp wpa wps
ifeq ($(CONFIG_MEMMAP_BT),y)
ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
LINKER_SCRIPTS = -T esp32.bt.trace.ld
else
LINKER_SCRIPTS = -T esp32.bt.ld
endif
else
ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
LINKER_SCRIPTS = -T esp32.trace.ld
else
LINKER_SCRIPTS = -T esp32.ld
endif
endif
LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld
COMPONENT_ADD_LDFLAGS := -lesp32 \
$(abspath libhal.a) \
-L$(abspath lib) \
$(addprefix -l,$(LIBS)) \
-L $(abspath ld) \
-T eagle.fpga32.v7.ld \
-T eagle.fpga32.rom.addr.v7.ld
$(LINKER_SCRIPTS)
include $(IDF_PATH)/make/component.mk

14
components/esp32/ld/esp32.bt.ld Normal file
View file

@ -0,0 +1,14 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x40000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x40000000;

14
components/esp32/ld/esp32.bt.trace.ld Normal file
View file

@ -0,0 +1,14 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x38000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x3FFF8000;

14
components/esp32/ld/esp32.trace.ld Normal file
View file

@ -0,0 +1,14 @@
/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
/* The load addresses are defined later using the AT statements. */
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x48000 /* Shared RAM, minus rom bss/data/stack.*/
drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
}
_heap_end = 0x3FFF8000;