bootloader: Fix SPI dummy clock settings for ESP32S2-beta
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d5f5fadbee
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1 changed files with 39 additions and 35 deletions
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@ -17,9 +17,9 @@
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#include "sdkconfig.h"
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_log.h"
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#include "esp32/rom/gpio.h"
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#include "esp32s2beta/rom/gpio.h"
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#include "esp32/rom/spi_flash.h"
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32/rom/efuse.h"
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#include "esp32s2beta/rom/efuse.h"
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#include "soc/gpio_periph.h"
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#include "soc/gpio_periph.h"
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#include "soc/efuse_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/spi_reg.h"
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#include "soc/spi_reg.h"
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@ -27,6 +27,12 @@
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#include "soc/spi_caps.h"
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#include "soc/spi_caps.h"
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#include "flash_qio_mode.h"
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#include "flash_qio_mode.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_common.h"
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#define FLASH_IO_MATRIX_DUMMY_40M 0
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#define FLASH_IO_MATRIX_DUMMY_80M 0
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#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
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void bootloader_flash_update_id()
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void bootloader_flash_update_id()
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{
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{
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@ -73,42 +79,40 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
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void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
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void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
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{
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{
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int spi_cache_dummy = 0;
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int spi_cache_dummy = 0;
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uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
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int drv = 2;
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if (modebit & SPI_FAST_RD_MODE) {
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switch (pfhdr->spi_mode) {
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if (modebit & SPI_FREAD_QUAD) { //SPI mode is QIO
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case ESP_IMAGE_SPI_MODE_QIO:
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
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} else if (modebit & SPI_FREAD_DUAL) { //SPI mode is DIO
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break;
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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case ESP_IMAGE_SPI_MODE_DIO:
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3
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} else if(modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) { //SPI mode is QOUT or DIO
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break;
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case ESP_IMAGE_SPI_MODE_QOUT:
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case ESP_IMAGE_SPI_MODE_DOUT:
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default:
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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}
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break;
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}
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}
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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switch (pfhdr->spi_speed) {
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_80M:
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case ESP_IMAGE_SPI_SPEED_80M:
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g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
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SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
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drv = 3;
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break;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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case ESP_IMAGE_SPI_SPEED_40M:
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g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
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break;
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
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case ESP_IMAGE_SPI_SPEED_26M:
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SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
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case ESP_IMAGE_SPI_SPEED_20M:
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g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
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g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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bootloader_configure_spi_pins(drv);
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#define FLASH_IO_MATRIX_DUMMY_40M 0
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#define FLASH_IO_MATRIX_DUMMY_80M 0
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
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SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
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}
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}
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