esp_flash: fix the quad issue for some GD flash chips
The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
This commit is contained in:
parent
1e1d50376b
commit
eb104aa16f
9 changed files with 180 additions and 17 deletions
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@ -14,7 +14,7 @@ else()
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"partition.c"
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"partition.c"
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"spi_flash_rom_patch.c"
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"spi_flash_rom_patch.c"
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)
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)
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# New implementation
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# New implementation after IDF v4.0
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list(APPEND cache_srcs
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list(APPEND cache_srcs
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"esp_flash_api.c"
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"esp_flash_api.c"
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"esp_flash_spi_init.c"
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"esp_flash_spi_init.c"
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@ -25,6 +25,7 @@ else()
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"spi_flash_chip_drivers.c"
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"spi_flash_chip_drivers.c"
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"spi_flash_chip_generic.c"
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"spi_flash_chip_generic.c"
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"spi_flash_chip_issi.c"
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"spi_flash_chip_issi.c"
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"spi_flash_chip_gd.c"
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"memspi_host_driver.c"
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"memspi_host_driver.c"
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)
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)
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list(APPEND srcs ${cache_srcs})
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list(APPEND srcs ${cache_srcs})
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@ -90,8 +90,23 @@ menu "SPI Flash driver"
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bool "ISSI"
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bool "ISSI"
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default y
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default y
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help
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help
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Enable this to support auto detection of ISSI chips if chip vendor not specified.
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Enable this to support auto detection of ISSI chips if chip vendor not directly
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This adds support for variant chips, however will extend detecting time.
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given by ``chip_drv`` member of the chip struct. This adds support for variant
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chips, however will extend detecting time.
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config SPI_FLASH_SUPPORT_GD_CHIP
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bool "GigaDevice"
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default y
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help
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Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not
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directly given by ``chip_drv`` member of the chip struct. If you are using Wrover
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modules, please don't disable this, otherwise your flash may not work in 4-bit
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mode.
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This adds support for variant chips, however will extend detecting time and image
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size. Note that the default chip driver supports the GD chips with product ID
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60H.
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endmenu #auto detect flash chips
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endmenu #auto detect flash chips
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endmenu
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endmenu
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@ -62,6 +62,7 @@ static const char io_mode_str[][IO_STR_LEN] = {
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_Static_assert(sizeof(io_mode_str)/IO_STR_LEN == SPI_FLASH_READ_MODE_MAX, "the io_mode_str should be consistent with the esp_flash_io_mode_t defined in spi_flash_ll.h");
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_Static_assert(sizeof(io_mode_str)/IO_STR_LEN == SPI_FLASH_READ_MODE_MAX, "the io_mode_str should be consistent with the esp_flash_io_mode_t defined in spi_flash_ll.h");
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esp_err_t esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id);
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/* Static function to notify OS of a new SPI flash operation.
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/* Static function to notify OS of a new SPI flash operation.
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@ -115,6 +116,18 @@ esp_err_t IRAM_ATTR esp_flash_init(esp_flash_t *chip)
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return ESP_ERR_INVALID_ARG;
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return ESP_ERR_INVALID_ARG;
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}
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}
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//read chip id
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uint32_t flash_id;
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int retries = 10;
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do {
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err = esp_flash_read_chip_id(chip, &flash_id);
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} while (err == ESP_ERR_FLASH_NOT_INITIALISED && retries-- > 0);
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if (err != ESP_OK) {
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return err;
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}
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chip->chip_id = flash_id;
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if (!esp_flash_chip_driver_initialized(chip)) {
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if (!esp_flash_chip_driver_initialized(chip)) {
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// Detect chip_drv
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// Detect chip_drv
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err = detect_spi_flash_chip(chip);
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err = detect_spi_flash_chip(chip);
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@ -175,15 +188,7 @@ esp_err_t IRAM_ATTR esp_flash_read_chip_id(esp_flash_t* chip, uint32_t* flash_id
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static esp_err_t IRAM_ATTR detect_spi_flash_chip(esp_flash_t *chip)
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static esp_err_t IRAM_ATTR detect_spi_flash_chip(esp_flash_t *chip)
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{
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{
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esp_err_t err;
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esp_err_t err;
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uint32_t flash_id;
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uint32_t flash_id = chip->chip_id;
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int retries = 10;
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do {
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err = esp_flash_read_chip_id(chip, &flash_id);
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} while (err == ESP_ERR_FLASH_NOT_INITIALISED && retries-- > 0);
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if (err != ESP_OK) {
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return err;
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}
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// Detect the chip and set the chip_drv structure for it
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// Detect the chip and set the chip_drv structure for it
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const spi_flash_chip_t **drivers = esp_flash_registered_chips;
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const spi_flash_chip_t **drivers = esp_flash_registered_chips;
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@ -65,6 +65,7 @@ struct esp_flash_t {
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esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
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esp_flash_io_mode_t read_mode; ///< Configured SPI flash read mode. Set before ``esp_flash_init`` is called.
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uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation.
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uint32_t size; ///< Size of SPI flash in bytes. If 0, size will be detected during initialisation.
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uint32_t chip_id; ///< Detected chip id.
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};
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};
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32
components/spi_flash/include/spi_flash_chip_gd.h
Normal file
32
components/spi_flash/include/spi_flash_chip_gd.h
Normal file
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@ -0,0 +1,32 @@
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp_flash.h"
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#include "spi_flash_chip_driver.h"
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/**
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* GD (GigaDevice) SPI flash chip_drv, uses all the above functions for its operations. In
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* default autodetection, this is used as a catchall if a more specific chip_drv
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* is not found.
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*
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* Note that this is for GD chips with product ID 40H (GD25Q) and 60H (GD25LQ). The chip diver uses
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* different commands to write the SR2 register according to the chip ID. For GD25Q40 - GD25Q16
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* chips, and GD25LQ chips, WRSR (01H) command is used; while WRSR2 (31H) is used for GD25Q32 -
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* GD25Q127 chips.
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*/
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extern const spi_flash_chip_t esp_flash_chip_gd;
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@ -4,5 +4,6 @@ entries:
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spi_flash_rom_patch (noflash_text)
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spi_flash_rom_patch (noflash_text)
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spi_flash_chip_generic (noflash)
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spi_flash_chip_generic (noflash)
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spi_flash_chip_issi (noflash)
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spi_flash_chip_issi (noflash)
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spi_flash_chip_gd(noflash)
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memspi_host_driver (noflash)
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memspi_host_driver (noflash)
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@ -16,6 +16,7 @@
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#include "spi_flash_chip_driver.h"
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#include "spi_flash_chip_driver.h"
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#include "spi_flash_chip_generic.h"
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#include "spi_flash_chip_generic.h"
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#include "spi_flash_chip_issi.h"
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#include "spi_flash_chip_issi.h"
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#include "spi_flash_chip_gd.h"
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#include "sdkconfig.h"
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#include "sdkconfig.h"
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/*
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/*
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@ -30,6 +31,9 @@
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static const spi_flash_chip_t *default_registered_chips[] = {
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static const spi_flash_chip_t *default_registered_chips[] = {
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#ifdef CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP
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#ifdef CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP
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&esp_flash_chip_issi,
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&esp_flash_chip_issi,
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#endif
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#ifdef CONFIG_SPI_FLASH_SUPPORT_GD_CHIP
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&esp_flash_chip_gd,
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#endif
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#endif
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&esp_flash_chip_generic,
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&esp_flash_chip_generic,
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NULL,
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NULL,
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108
components/spi_flash/spi_flash_chip_gd.c
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108
components/spi_flash/spi_flash_chip_gd.c
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@ -0,0 +1,108 @@
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "spi_flash_chip_generic.h"
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#include "spi_flash_defs.h"
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#define FLASH_ID_MASK 0xFF00
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#define FLASH_SIZE_MASK 0xFF
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#define GD25Q_PRODUCT_ID 0x4000
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#define GD25LQ_PRODUCT_ID 0x6000
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#define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \
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((chip_id) & FLASH_SIZE_MASK) <= 0x15)
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/* Driver for GD flash chip */
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esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id)
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{
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/* Check manufacturer and product IDs match our desired masks */
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const uint8_t MFG_ID = 0xC8;
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if (flash_id >> 16 != MFG_ID) {
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return ESP_ERR_NOT_FOUND;
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}
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uint32_t product_id = flash_id & FLASH_ID_MASK;
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if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) {
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return ESP_ERR_NOT_FOUND;
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}
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_gd_set_io_mode(esp_flash_t *chip)
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{
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if (WRSR_16B_REQUIRED(chip->chip_id)) {
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const uint32_t qe = 1<<9;
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return spi_flash_common_set_io_mode(chip,
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spi_flash_common_write_status_16b_wrsr,
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spi_flash_common_read_status_16b_rdsr_rdsr2,
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qe);
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} else {
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const uint32_t qe = 1<<1;
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return spi_flash_common_set_io_mode(chip,
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spi_flash_common_write_status_8b_wrsr2,
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spi_flash_common_read_status_8b_rdsr2,
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qe);
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}
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}
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esp_err_t spi_flash_chip_gd_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
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{
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/* GD uses bit 1 of SR2 as Quad Enable */
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const uint8_t BIT_QE = 1 << 1;
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uint32_t sr;
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esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
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if (ret == ESP_OK) {
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*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
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}
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return ret;
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}
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static const char chip_name[] = "gd";
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// The issi chip can use the functions for generic chips except from set read mode and probe,
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// So we only replace these two functions.
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const spi_flash_chip_t esp_flash_chip_gd = {
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.name = chip_name,
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.probe = spi_flash_chip_gd_probe,
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.reset = spi_flash_chip_generic_reset,
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.detect_size = spi_flash_chip_generic_detect_size,
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.erase_chip = spi_flash_chip_generic_erase_chip,
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.erase_sector = spi_flash_chip_generic_erase_sector,
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.erase_block = spi_flash_chip_generic_erase_block,
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.sector_size = 4 * 1024,
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.block_erase_size = 64 * 1024,
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.get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
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.set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
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// TODO support protected regions on ISSI flash
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.num_protectable_regions = 0,
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.protectable_regions = NULL,
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.get_protected_regions = NULL,
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.set_protected_regions = NULL,
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.read = spi_flash_chip_generic_read,
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.write = spi_flash_chip_generic_write,
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.program_page = spi_flash_chip_generic_page_program,
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.page_size = 256,
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.write_encrypted = spi_flash_chip_generic_write_encrypted,
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.wait_idle = spi_flash_chip_generic_wait_idle,
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.set_io_mode = spi_flash_chip_gd_set_io_mode,
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.get_io_mode = spi_flash_chip_gd_get_io_mode,
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};
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@ -60,12 +60,8 @@ esp_err_t spi_flash_chip_generic_reset(esp_flash_t *chip)
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esp_err_t spi_flash_chip_generic_detect_size(esp_flash_t *chip, uint32_t *size)
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esp_err_t spi_flash_chip_generic_detect_size(esp_flash_t *chip, uint32_t *size)
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{
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{
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uint32_t id = 0;
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uint32_t id = chip->chip_id;
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*size = 0;
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*size = 0;
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esp_err_t err = chip->host->read_id(chip->host, &id);
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if (err != ESP_OK) {
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return err;
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}
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/* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
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/* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
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* 0xC0 or similar. */
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* 0xC0 or similar. */
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