From 305354d0a2f464ae3042d6b0e2bbce09af1f8151 Mon Sep 17 00:00:00 2001 From: michael Date: Sun, 30 Sep 2018 19:00:06 +0800 Subject: [PATCH 1/2] test: change spi test host to macros --- components/driver/test/test_common_spi.c | 2 +- components/driver/test/test_spi_master.c | 112 +++++++++++------------ components/driver/test/test_spi_param.c | 16 ++-- components/driver/test/test_spi_slave.c | 23 ++--- 4 files changed, 73 insertions(+), 80 deletions(-) diff --git a/components/driver/test/test_common_spi.c b/components/driver/test/test_common_spi.c index ed0a681ca..b05bd271e 100644 --- a/components/driver/test/test_common_spi.c +++ b/components/driver/test/test_common_spi.c @@ -44,7 +44,7 @@ esp_err_t init_slave_context(spi_slave_task_context_t *context) if ( context->data_received == NULL ) { return ESP_ERR_NO_MEM; } - context->spi=VSPI_HOST; + context->spi=TEST_SLAVE_HOST; return ESP_OK; } diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 5f6da2570..449e0d9d7 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -46,7 +46,7 @@ static void check_spi_pre_n_for(int clk, int pre, int n) spi_transaction_t t; memset(&t, 0, sizeof(t)); - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &handle); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle); TEST_ASSERT(ret==ESP_OK); t.length=16*8; @@ -73,7 +73,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") .quadhd_io_num=-1 }; esp_err_t ret; - ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); check_spi_pre_n_for(26000000, 1, 3); @@ -86,7 +86,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") check_spi_pre_n_for(1, 8192, 64); //Actually should generate the minimum clock speed, 152Hz check_spi_pre_n_for(26000000, 1, 3); - ret=spi_bus_free(HSPI_HOST); + ret=spi_bus_free(TEST_SPI_HOST); TEST_ASSERT(ret==ESP_OK); } @@ -112,12 +112,12 @@ static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) { esp_err_t ret; spi_device_handle_t handle; - ret=spi_bus_initialize(HSPI_HOST, &buscfg, dma?1:0); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma?1:0); TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &handle); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle); TEST_ASSERT(ret==ESP_OK); //connect MOSI to two devices breaks the output, fix it. - spitest_gpio_output_sel(26, FUNC_GPIO, HSPID_OUT_IDX); + spitest_gpio_output_sel(26, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); printf("Bus/dev inited.\n"); return handle; } @@ -235,7 +235,7 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") { }; spi_device_handle_t handle1=setup_spi_bus(80000, true); spi_device_handle_t handle2; - spi_bus_add_device(HSPI_HOST, &devcfg, &handle2); + spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle2); printf("Sending to dev 1\n"); success &= spi_test(handle1, 7); @@ -273,18 +273,18 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_NATIVE_PINS | SPICOMMON_BUSFLAG_QUAD; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test 4 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_NATIVE_PINS | SPICOMMON_BUSFLAG_DUAL; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test 6 output pins..."); @@ -292,9 +292,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test 4 output pins..."); @@ -302,23 +302,23 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin..."); @@ -326,14 +326,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO; cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "check native flag for 6 output pins..."); @@ -341,70 +341,70 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check native flag for 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_NATIVE_PINS; //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check sclk flag..."); flags_expected = SPICOMMON_BUSFLAG_SCLK; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = -1, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check mosi flag..."); flags_expected = SPICOMMON_BUSFLAG_MOSI; cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check miso flag..."); flags_expected = SPICOMMON_BUSFLAG_MISO; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = -1, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check quad flag..."); flags_expected = SPICOMMON_BUSFLAG_QUAD; cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(HSPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); } TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)", "[spi]") @@ -519,13 +519,13 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); //Initialize the SPI bus - ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); //Attach the LCD to the SPI bus - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi); TEST_ASSERT(ret==ESP_OK); //connect MOSI to two devices breaks the output, fix it. - spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX); + spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); #define TEST_REGION_SIZE 5 static spi_transaction_t trans[TEST_REGION_SIZE]; @@ -569,7 +569,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") } } TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); - TEST_ASSERT(spi_bus_free(HSPI_HOST) == ESP_OK); + TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK); free(data_malloc); free(data_iram); } @@ -600,14 +600,14 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") .pre_cb=NULL, }; //Initialize the SPI bus - ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); //Attach the LCD to the SPI bus - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi); TEST_ASSERT(ret==ESP_OK); //connect MOSI to two devices breaks the output, fix it. - spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX); + spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); memset(rx_buf, 0x66, 320); @@ -646,7 +646,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") } TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); - TEST_ASSERT(spi_bus_free(HSPI_HOST) == ESP_OK); + TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK); } static uint8_t bitswap(uint8_t in) @@ -812,9 +812,9 @@ static void speed_setup(spi_device_handle_t* spi, bool use_dma) devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time //Initialize the SPI bus and the device to test - ret=spi_bus_initialize(HSPI_HOST, &buscfg, (use_dma?1:0)); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma?1:0)); TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(HSPI_HOST, &devcfg, spi); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); TEST_ASSERT(ret==ESP_OK); } @@ -1043,13 +1043,13 @@ TEST_CASE("spi poll tasks","[spi]") devcfg.queue_size = 100; //Initialize the SPI bus and 3 devices - ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &context1.handle); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context1.handle); TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &context2.handle); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context2.handle); TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(HSPI_HOST, &devcfg, &context3.handle); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &context3.handle); TEST_ASSERT(ret==ESP_OK); xTaskCreate( spi_task1, "task1", 2048, &context1, 0, &task1 ); @@ -1064,7 +1064,7 @@ TEST_CASE("spi poll tasks","[spi]") TEST_ESP_OK( spi_bus_remove_device(context1.handle) ); TEST_ESP_OK( spi_bus_remove_device(context2.handle) ); TEST_ESP_OK( spi_bus_remove_device(context3.handle) ); - TEST_ESP_OK( spi_bus_free(HSPI_HOST) ); + TEST_ESP_OK( spi_bus_free(TEST_SPI_HOST) ); } diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/test_spi_param.c index 87036e0cd..40d91eda0 100644 --- a/components/driver/test/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -91,12 +91,12 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p slave_pull_up(&buscfg, slvcfg.spics_io_num); - TEST_ESP_OK(spi_bus_initialize(HSPI_HOST, &buscfg, pset->master_dma_chan)); - TEST_ESP_OK(spi_bus_add_device(HSPI_HOST, &devcfg, spi)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, pset->master_dma_chan)); + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); //slave automatically use iomux pins if pins are on VSPI_* pins buscfg.quadhd_io_num = -1; - TEST_ESP_OK(spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, pset->slave_dma_chan)); + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, pset->slave_dma_chan)); //initialize master and slave on the same pins break some of the output configs, fix them if (pset->master_iomux) { @@ -170,7 +170,7 @@ static void local_test_loop(const void* arg1, void* arg2) vRingbufferReturnItem(context->slave_context.data_received, rcv_data); } master_free_device_bus(spi); - TEST_ASSERT(spi_slave_free(VSPI_HOST) == ESP_OK); + TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK); } } @@ -504,8 +504,8 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_ devpset.input_delay_ns = pset->slave_tv_ns; devpset.clock_speed_hz = freq; if (pset->master_limit != 0 && freq > pset->master_limit) devpset.flags |= SPI_DEVICE_NO_DUMMY; - TEST_ESP_OK(spi_bus_initialize(HSPI_HOST, &buspset, pset->master_dma_chan)); - TEST_ESP_OK(spi_bus_add_device(HSPI_HOST, &devpset, spi)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buspset, pset->master_dma_chan)); + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devpset, spi)); //prepare data for the slave for (int i = 0; i < pset->test_size; i ++) { @@ -624,7 +624,7 @@ static void timing_slave_start(int speed, const spitest_param_set_t* pset, spite //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. slave_pull_up(&slv_buscfg, slvcfg.spics_io_num); - TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &slv_buscfg, &slvcfg, pset->slave_dma_chan) ); + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, pset->slave_dma_chan)); //prepare data for the master for (int i = 0; i < pset->test_size; i++) { @@ -684,7 +684,7 @@ static void test_slave_loop(const void *arg1, void* arg2) //clean vRingbufferReturnItem( context->slave_context.data_received, rcv_data ); } - TEST_ASSERT(spi_slave_free(VSPI_HOST) == ESP_OK); + TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK); } } diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/test_spi_slave.c index bee3fada6..0095ec28e 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -8,18 +8,11 @@ #include "driver/spi_slave.h" #include "esp_log.h" #include "sdkconfig.h" +#include "test/test_common_spi.h" #ifndef CONFIG_SPIRAM_SUPPORT //This test should be removed once the timing test is merged. -#define PIN_NUM_MISO 25 -#define PIN_NUM_MOSI 23 -#define PIN_NUM_CLK 19 -#define PIN_NUM_CS 22 - - -static const char MASTER_TAG[] = "test_master"; -static const char SLAVE_TAG[] = "test_slave"; #define MASTER_SEND {0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43} #define SLAVE_SEND { 0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0 } @@ -50,10 +43,10 @@ static void master_init_nodma( spi_device_handle_t* spi) .cs_ena_pretrans=1, }; //Initialize the SPI bus - ret=spi_bus_initialize(HSPI_HOST, &buscfg, 0); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 0); TEST_ASSERT(ret==ESP_OK); //Attach the LCD to the SPI bus - ret=spi_bus_add_device(HSPI_HOST, &devcfg, spi); + ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); TEST_ASSERT(ret==ESP_OK); } @@ -77,7 +70,7 @@ static void slave_init() gpio_set_pull_mode(PIN_NUM_CLK, GPIO_PULLUP_ONLY); gpio_set_pull_mode(PIN_NUM_CS, GPIO_PULLUP_ONLY); //Initialize SPI slave interface - TEST_ESP_OK( spi_slave_initialize(VSPI_HOST, &buscfg, &slvcfg, 2) ); + TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, 2) ); } TEST_CASE("test slave send unaligned","[spi]") @@ -107,7 +100,7 @@ TEST_CASE("test slave send unaligned","[spi]") slave_t.length=8*32; slave_t.tx_buffer=slave_txbuf+i; slave_t.rx_buffer=slave_rxbuf; - TEST_ESP_OK( spi_slave_queue_trans( VSPI_HOST, &slave_t, portMAX_DELAY ) ); + TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY)); //send spi_transaction_t t = {}; @@ -119,7 +112,7 @@ TEST_CASE("test slave send unaligned","[spi]") spi_device_transmit( spi, (spi_transaction_t*)&t ); //wait for end - TEST_ESP_OK( spi_slave_get_trans_result( VSPI_HOST, &out, portMAX_DELAY ) ); + TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &out, portMAX_DELAY)); //show result ESP_LOGI(SLAVE_TAG, "trans_len: %d", slave_t.trans_len); @@ -138,10 +131,10 @@ TEST_CASE("test slave send unaligned","[spi]") memset( slave_rxbuf, 0x66, sizeof(slave_rxbuf)); } - TEST_ASSERT(spi_slave_free(VSPI_HOST) == ESP_OK); + TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK); TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); - TEST_ASSERT(spi_bus_free(HSPI_HOST) == ESP_OK); + TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK); ESP_LOGI(MASTER_TAG, "test passed."); } From 2dc3c611142d5c43aaf3872a33dddd2d2f47c9f6 Mon Sep 17 00:00:00 2001 From: michael Date: Sun, 30 Sep 2018 19:00:25 +0800 Subject: [PATCH 2/2] test: add unit test for spi sio mode --- components/driver/test/test_spi_sio.c | 221 ++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) create mode 100644 components/driver/test/test_spi_sio.c diff --git a/components/driver/test/test_spi_sio.c b/components/driver/test/test_spi_sio.c new file mode 100644 index 000000000..a286bedde --- /dev/null +++ b/components/driver/test/test_spi_sio.c @@ -0,0 +1,221 @@ +/* + Tests for the spi sio mode +*/ + +#include +#include +#include +#include +#include +#include "rom/ets_sys.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/semphr.h" +#include "freertos/queue.h" +#include "freertos/xtensa_api.h" +#include "unity.h" +#include "driver/spi_master.h" +#include "driver/spi_slave.h" +#include "soc/dport_reg.h" +#include "esp_heap_caps.h" +#include "esp_log.h" +#include "soc/spi_periph.h" +#include "test_utils.h" +#include "test/test_common_spi.h" +#include "soc/gpio_periph.h" +#include "sdkconfig.h" + + +/******************************************************************************** + * Test SIO + ********************************************************************************/ +TEST_CASE("local test sio", "[spi]") +{ + spi_device_handle_t spi; + WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320]; + WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320]; + + for (int i = 0; i < 16; i++) { + SPI1.data_buf[0] = 0xcccccccc; + SPI2.data_buf[0] = 0xcccccccc; + } + + /* This test use a strange connection to test the SIO mode: + * master spid -> slave spid + * slave spiq -> master spid + */ + spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); + spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); + spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); + slv_cfg.spics_io_num = dev_cfg.spics_io_num; + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0)); + + int miso_io_num = bus_cfg.miso_io_num; + int mosi_io_num = bus_cfg.mosi_io_num; + bus_cfg.mosi_io_num = bus_cfg.miso_io_num; + bus_cfg.miso_io_num = -1; + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0)); + + dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE; + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi)); + + spitest_gpio_output_sel(mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); + spitest_gpio_output_sel(miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); + spitest_gpio_output_sel(dev_cfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]); + spitest_gpio_output_sel(bus_cfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out); + + for (int i = 0; i < 8; i ++) { + int tlen = i*2+1; + int rlen = 9-i; + + ESP_LOGI(MASTER_TAG, "=========== TEST%d ==========", i); + + spi_transaction_t master_t = { + .length = tlen*8, + .tx_buffer = spitest_master_send+i, + .rxlength = rlen*8, + .rx_buffer = master_rx_buffer+i, + }; + spi_slave_transaction_t slave_t = { + .length = (tlen+rlen)*8, + .tx_buffer = spitest_slave_send+i, + .rx_buffer = slave_rx_buffer, + }; + memset(master_rx_buffer, 0x66, sizeof(master_rx_buffer)); + memset(slave_rx_buffer, 0x66, sizeof(slave_rx_buffer)); + TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY)); + + TEST_ESP_OK(spi_device_transmit(spi, &master_t)); + spi_slave_transaction_t* ret_t; + TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY)); + TEST_ASSERT(ret_t == &slave_t); + + ESP_LOG_BUFFER_HEXDUMP("master tx", master_t.tx_buffer, tlen, ESP_LOG_INFO); + ESP_LOG_BUFFER_HEXDUMP("slave rx", slave_t.rx_buffer, tlen+rlen, ESP_LOG_INFO); + ESP_LOG_BUFFER_HEXDUMP("slave tx", slave_t.tx_buffer, tlen+rlen, ESP_LOG_INFO); + ESP_LOG_BUFFER_HEXDUMP("master rx", master_t.rx_buffer, rlen, ESP_LOG_INFO); + + TEST_ASSERT_EQUAL_HEX8_ARRAY(master_t.tx_buffer, slave_t.rx_buffer, tlen); + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t.tx_buffer + tlen, master_t.rx_buffer, rlen); + } + + spi_slave_free(TEST_SLAVE_HOST); + master_free_device_bus(spi); +} + +/******************************************************************************** + * Test SIO Master & Slave + ********************************************************************************/ +//if test_mosi is false, test on miso of slave, otherwise test on mosi of slave +void test_sio_master_round(bool test_mosi) +{ + spi_device_handle_t spi; + WORD_ALIGNED_ATTR uint8_t rx_buffer[320]; + + if (test_mosi) { + ESP_LOGI(MASTER_TAG, "======== TEST MOSI ==========="); + } else { + ESP_LOGI(MASTER_TAG, "======== TEST MISO ==========="); + } + + spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); + if (!test_mosi) bus_cfg.mosi_io_num = bus_cfg.miso_io_num; + bus_cfg.miso_io_num = -1; + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0)); + + spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); + dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE; + dev_cfg.clock_speed_hz = 1*1000*1000; + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi)); + + for (int i = 0; i < 8; i ++) { + int tlen = i*2+1; + int rlen = 9-i; + spi_transaction_t t = { + .length = tlen*8, + .tx_buffer = spitest_master_send+i, + .rxlength = rlen*8, + .rx_buffer = rx_buffer+i, + }; + memset(rx_buffer, 0x66, sizeof(rx_buffer)); + + //get signal + unity_wait_for_signal("slave ready"); + + TEST_ESP_OK(spi_device_transmit(spi, &t)); + uint8_t* exp_ptr = spitest_slave_send+i; + ESP_LOG_BUFFER_HEXDUMP("master tx", t.tx_buffer, tlen, ESP_LOG_INFO); + ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, rlen, ESP_LOG_INFO); + ESP_LOG_BUFFER_HEXDUMP("master rx", t.rx_buffer, rlen, ESP_LOG_INFO); + if (!test_mosi) { + TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr+tlen, t.rx_buffer, rlen); + } + } + + master_free_device_bus(spi); +} + +void test_sio_master() +{ + test_sio_master_round(true); + unity_send_signal("master ready"); + test_sio_master_round(false); +} + +void test_sio_slave_round(bool test_mosi) +{ + WORD_ALIGNED_ATTR uint8_t rx_buffer[320]; + + if (test_mosi) { + ESP_LOGI(SLAVE_TAG, "======== TEST MOSI ==========="); + } else { + ESP_LOGI(SLAVE_TAG, "======== TEST MISO ==========="); + } + + spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG(); + bus_cfg.mosi_io_num = spi_periph_signal[TEST_SLAVE_HOST].spid_iomux_pin; + bus_cfg.miso_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiq_iomux_pin; + bus_cfg.sclk_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiclk_iomux_pin; + + spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); + slv_cfg.spics_io_num = spi_periph_signal[TEST_SLAVE_HOST].spics0_iomux_pin; + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0)); + + for (int i = 0; i < 8; i++) { + int tlen = 9-i; + int rlen = i*2+1; + spi_slave_transaction_t t = { + .length = (tlen+rlen)*8, + .tx_buffer = spitest_slave_send+i, + .rx_buffer = rx_buffer, + }; + + TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &t, portMAX_DELAY)); + + ESP_LOG_BUFFER_HEXDUMP("slave tx", t.tx_buffer, tlen+rlen, ESP_LOG_INFO); + + //send signal_idx + unity_send_signal("slave ready"); + + uint8_t *exp_ptr = spitest_master_send+i; + spi_slave_transaction_t* ret_t; + TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY)); + + ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, tlen+rlen, ESP_LOG_INFO); + ESP_LOG_BUFFER_HEXDUMP("slave rx", t.rx_buffer, tlen+rlen, ESP_LOG_INFO); + if (test_mosi) { + TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr, t.rx_buffer, rlen); + } + } + + spi_slave_free(TEST_SLAVE_HOST); +} + +void test_sio_slave() +{ + test_sio_slave_round(true); + unity_wait_for_signal("master ready"); + test_sio_slave_round(false); +} + +TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave);