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clk: fix regression in clock setting for SPIRAM with 80MHz config

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Support for HSPI to output clock for 4M SPIRAM introduced regression
in clock configuration affecting SPIRAM access with 80MHz clock. This
commit fixes the issue.
This commit is contained in:
Mahavir Jain 2018-11-17 00:05:56 +05:30
parent 960c240578
commit e3956787f6
1 changed files with 2 additions and 2 deletions
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4
components/esp32/clk.c
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@ -297,10 +297,10 @@ void esp_perip_clk_init(void)
//a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
//in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
//not modify that state, regardless of what we calculated earlier.
if (!spicommon_periph_in_use(HSPI_HOST)) {
if (spicommon_periph_in_use(HSPI_HOST)) {
common_perip_clk &= ~DPORT_SPI2_CLK_EN;
}
if (!spicommon_periph_in_use(VSPI_HOST)) {
if (spicommon_periph_in_use(VSPI_HOST)) {
common_perip_clk &= ~DPORT_SPI3_CLK_EN;
}
#endif