periph_clk_gating: add reference counter
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@ -28,6 +28,10 @@ extern "C" {
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*
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*
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* Clock for the module will be ungated, and reset de-asserted.
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* Clock for the module will be ungated, and reset de-asserted.
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*
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*
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* @note If periph_module_enable is called a number of times,
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* periph_module_disable has to be called the same number of times
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* in order to put the peripheral into disabled state.
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*
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* @return NULL
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* @return NULL
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*
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*
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*/
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*/
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@ -40,6 +44,10 @@ void periph_module_enable(periph_module_t periph);
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*
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*
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* Clock for the module will be gated, reset asserted.
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* Clock for the module will be gated, reset asserted.
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*
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*
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* @note If periph_module_enable is called a number of times,
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* periph_module_disable has to be called the same number of times
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* in order to put the peripheral into disabled state.
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*
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* @return NULL
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* @return NULL
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*
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*
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*/
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*/
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@ -17,22 +17,33 @@
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static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static uint8_t ref_counts[PERIPH_MODULE_MAX] = {0};
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void periph_module_enable(periph_module_t periph)
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void periph_module_enable(periph_module_t periph)
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{
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{
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assert(periph < PERIPH_MODULE_MAX);
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portENTER_CRITICAL_SAFE(&periph_spinlock);
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portENTER_CRITICAL_SAFE(&periph_spinlock);
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periph_ll_enable_clk_clear_rst(periph);
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if (ref_counts[periph] == 0) {
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periph_ll_enable_clk_clear_rst(periph);
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}
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ref_counts[periph]++;
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portEXIT_CRITICAL_SAFE(&periph_spinlock);
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portEXIT_CRITICAL_SAFE(&periph_spinlock);
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}
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}
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void periph_module_disable(periph_module_t periph)
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void periph_module_disable(periph_module_t periph)
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{
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{
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assert(periph < PERIPH_MODULE_MAX);
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portENTER_CRITICAL_SAFE(&periph_spinlock);
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portENTER_CRITICAL_SAFE(&periph_spinlock);
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periph_ll_disable_clk_set_rst(periph);
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ref_counts[periph]--;
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if (ref_counts[periph] == 0) {
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periph_ll_disable_clk_set_rst(periph);
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}
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portEXIT_CRITICAL_SAFE(&periph_spinlock);
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portEXIT_CRITICAL_SAFE(&periph_spinlock);
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}
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}
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void periph_module_reset(periph_module_t periph)
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void periph_module_reset(periph_module_t periph)
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{
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{
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assert(periph < PERIPH_MODULE_MAX);
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portENTER_CRITICAL_SAFE(&periph_spinlock);
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portENTER_CRITICAL_SAFE(&periph_spinlock);
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periph_ll_reset(periph);
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periph_ll_reset(periph);
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portEXIT_CRITICAL_SAFE(&periph_spinlock);
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portEXIT_CRITICAL_SAFE(&periph_spinlock);
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@ -55,6 +55,7 @@ typedef enum {
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PERIPH_AES_MODULE,
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PERIPH_AES_MODULE,
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PERIPH_SHA_MODULE,
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PERIPH_SHA_MODULE,
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PERIPH_RSA_MODULE,
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PERIPH_RSA_MODULE,
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PERIPH_MODULE_MAX
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} periph_module_t;
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} periph_module_t;
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -54,6 +54,7 @@ typedef enum {
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PERIPH_CRYPTO_DMA_MODULE, //this DMA is shared between AES and SHA
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PERIPH_CRYPTO_DMA_MODULE, //this DMA is shared between AES and SHA
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PERIPH_AES_DMA_MODULE,
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PERIPH_AES_DMA_MODULE,
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PERIPH_SHA_DMA_MODULE,
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PERIPH_SHA_DMA_MODULE,
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PERIPH_MODULE_MAX
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} periph_module_t;
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} periph_module_t;
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typedef enum {
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typedef enum {
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