From db84ba868c4c7b266f1574a1dc500203630077d8 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Tue, 18 Jun 2019 19:34:05 +0800 Subject: [PATCH] efuse: Add support for esp32s2beta Updated: - CI test_esp32s2beta_efuse_table_on_host. - efuse_table_gen.py. - esp_efuse_table.csv file and generated headers files. - splitted esp32 and esp32s2beta parts. - unit tests and api efuse. --- components/efuse/CMakeLists.txt | 43 +- components/efuse/Kconfig | 2 + components/efuse/component.mk | 10 +- components/efuse/efuse_table_gen.py | 66 +- components/efuse/esp32s2beta/component.mk | 0 .../efuse/esp32s2beta/esp_efuse_table.c | 939 ++++++++++++++++++ .../efuse/esp32s2beta/esp_efuse_table.csv | 138 +++ .../esp32s2beta/include/esp_efuse_table.h | 131 +++ components/efuse/esp32s2beta/sources.cmake | 1 + components/efuse/include/esp32/esp_efuse.h | 44 + .../efuse/include/esp32s2beta/esp_efuse.h | 69 ++ components/efuse/include/esp_efuse.h | 39 +- .../private_include/esp32/esp_efuse_utility.h | 49 + .../esp32s2beta/esp_efuse_utility.h | 30 + .../esp_efuse_utility.h | 24 +- components/efuse/src/esp32/esp_efuse_api.c | 69 ++ components/efuse/src/esp32/esp_efuse_fields.c | 102 ++ .../efuse/src/esp32/esp_efuse_utility.c | 234 +++++ .../efuse/src/esp32s2beta/esp_efuse_api.c | 83 ++ .../efuse/src/esp32s2beta/esp_efuse_fields.c | 76 ++ .../efuse/src/esp32s2beta/esp_efuse_utility.c | 178 ++++ components/efuse/src/esp_efuse_api.c | 51 +- components/efuse/src/esp_efuse_fields.c | 132 +-- components/efuse/src/esp_efuse_utility.c | 208 +--- components/efuse/test/CMakeLists.txt | 11 +- components/efuse/test/component.mk | 2 + components/efuse/test/esp32/test_efuse.c | 67 ++ .../{ => esp32}/test_efuse_coding_scheme.c | 13 +- .../efuse/test/esp32s2beta/test_efuse.c | 130 +++ .../esp32s2beta/test_efuse_coding_scheme.c | 0 components/efuse/test/test_efuse.c | 129 +-- .../efuse/test_efuse_host/efuse_tests.py | 2 +- tools/ci/config/host-test.yml | 20 +- 33 files changed, 2573 insertions(+), 519 deletions(-) create mode 100644 components/efuse/esp32s2beta/component.mk create mode 100644 components/efuse/esp32s2beta/esp_efuse_table.c create mode 100644 components/efuse/esp32s2beta/esp_efuse_table.csv create mode 100644 components/efuse/esp32s2beta/include/esp_efuse_table.h create mode 100644 components/efuse/esp32s2beta/sources.cmake create mode 100644 components/efuse/include/esp32/esp_efuse.h create mode 100644 components/efuse/include/esp32s2beta/esp_efuse.h create mode 100644 components/efuse/private_include/esp32/esp_efuse_utility.h create mode 100644 components/efuse/private_include/esp32s2beta/esp_efuse_utility.h rename components/efuse/{src => private_include}/esp_efuse_utility.h (91%) create mode 100644 components/efuse/src/esp32/esp_efuse_api.c create mode 100644 components/efuse/src/esp32/esp_efuse_fields.c create mode 100644 components/efuse/src/esp32/esp_efuse_utility.c create mode 100644 components/efuse/src/esp32s2beta/esp_efuse_api.c create mode 100644 components/efuse/src/esp32s2beta/esp_efuse_fields.c create mode 100644 components/efuse/src/esp32s2beta/esp_efuse_utility.c create mode 100644 components/efuse/test/esp32/test_efuse.c rename components/efuse/test/{ => esp32}/test_efuse_coding_scheme.c (95%) create mode 100644 components/efuse/test/esp32s2beta/test_efuse.c create mode 100644 components/efuse/test/esp32s2beta/test_efuse_coding_scheme.c diff --git a/components/efuse/CMakeLists.txt b/components/efuse/CMakeLists.txt index 08eccf264..70a1c360e 100644 --- a/components/efuse/CMakeLists.txt +++ b/components/efuse/CMakeLists.txt @@ -1,34 +1,35 @@ -idf_build_get_property(soc_name IDF_TARGET) - -# TODO: add esp32sbeta support for efuse component -#require_idf_targets(esp32) - idf_build_get_property(target IDF_TARGET) -if(NOT "${target}" STREQUAL "esp32") - return() + +if(EXISTS "${COMPONENT_DIR}/${target}") + include(${COMPONENT_DIR}/${target}/sources.cmake) + spaces2list(EFUSE_SOC_SRCS) + set(include_dirs include ${target}/include) + add_prefix(srcs "${target}/" ${EFUSE_SOC_SRCS}) + list(APPEND srcs "src/${target}/esp_efuse_api.c" + "src/${target}/esp_efuse_fields.c" + "src/${target}/esp_efuse_utility.c") endif() -include(${COMPONENT_DIR}/${soc_name}/sources.cmake) -spaces2list(EFUSE_SOC_SRCS) -add_prefix(srcs "${soc_name}/" ${EFUSE_SOC_SRCS}) -set(include_dirs include ${soc_name}/include) - -list(APPEND srcs - "src/esp_efuse_api.c" - "src/esp_efuse_fields.c" - "src/esp_efuse_utility.c") +list(APPEND srcs "src/esp_efuse_api.c" + "src/esp_efuse_fields.c" + "src/esp_efuse_utility.c") idf_component_register(SRCS "${srcs}" PRIV_REQUIRES bootloader_support soc spi_flash - INCLUDE_DIRS "${include_dirs}") + INCLUDE_DIRS "${include_dirs}" + PRIV_INCLUDE_DIRS private_include) -set(GEN_EFUSE_TABLE_ARG --max_blk_len ${CONFIG_EFUSE_MAX_BLK_LEN}) +if(target) + set(TOOL_TARGET -t ${target}) +endif() + +set(GEN_EFUSE_TABLE_ARG ${TOOL_TARGET} --max_blk_len ${CONFIG_EFUSE_MAX_BLK_LEN}) idf_build_get_property(python PYTHON) ################### # Make common files esp_efuse_table.c and include/esp_efuse_table.h files. -set(EFUSE_COMMON_TABLE_CSV_PATH "${COMPONENT_DIR}/${soc_name}/esp_efuse_table.csv") +set(EFUSE_COMMON_TABLE_CSV_PATH "${COMPONENT_DIR}/${target}/esp_efuse_table.csv") add_custom_target(efuse_common_table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py" ${EFUSE_COMMON_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG}) @@ -39,9 +40,9 @@ if(${CONFIG_EFUSE_CUSTOM_TABLE}) # Custom filename expands any path relative to the project idf_build_get_property(project_dir PROJECT_DIR) get_filename_component(EFUSE_CUSTOM_TABLE_CSV_PATH "${CONFIG_EFUSE_CUSTOM_TABLE_FILENAME}" ABSOLUTE BASE_DIR "${project_dir}") - add_custom_target(efuse_custom_table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py" ${EFUSE_COMMON_TABLE_CSV_PATH} ${EFUSE_CUSTOM_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG}) + add_custom_target(efuse_custom_table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py" ${EFUSE_COMMON_TABLE_CSV_PATH} ${EFUSE_CUSTOM_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG}) else() - add_custom_target(efuse_custom_table COMMAND) + add_custom_target(efuse_custom_table COMMAND) endif()#if(${CONFIG_EFUSE_CUSTOM_TABLE}) add_custom_target(show_efuse_table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py" ${EFUSE_COMMON_TABLE_CSV_PATH} ${EFUSE_CUSTOM_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG} "--info") diff --git a/components/efuse/Kconfig b/components/efuse/Kconfig index bf40e2dfc..c33fa053d 100644 --- a/components/efuse/Kconfig +++ b/components/efuse/Kconfig @@ -25,6 +25,7 @@ menu "eFuse Bit Manager" choice EFUSE_CODE_SCHEME_SELECTOR prompt "Coding Scheme Compatibility" default EFUSE_CODE_SCHEME_COMPAT_3_4 + depends on IDF_TARGET_ESP32 help Selector eFuse code scheme. @@ -41,5 +42,6 @@ menu "eFuse Bit Manager" default 256 if EFUSE_CODE_SCHEME_COMPAT_NONE default 192 if EFUSE_CODE_SCHEME_COMPAT_3_4 default 128 if EFUSE_CODE_SCHEME_COMPAT_REPEAT + default 256 if IDF_TARGET_ESP32S2BETA endmenu diff --git a/components/efuse/component.mk b/components/efuse/component.mk index 393f21020..530b590fd 100644 --- a/components/efuse/component.mk +++ b/components/efuse/component.mk @@ -1,10 +1,10 @@ # # Component Makefile # currently the only SoC supported; to be moved into Kconfig -SOC_NAME := $(IDF_TARGET) +TARGET := $(IDF_TARGET) -COMPONENT_SRCDIRS := $(SOC_NAME) src +COMPONENT_SRCDIRS := $(TARGET) src src/$(TARGET) +COMPONENT_PRIV_INCLUDEDIRS := private_include +COMPONENT_ADD_INCLUDEDIRS := $(TARGET)/include include -COMPONENT_ADD_INCLUDEDIRS := $(SOC_NAME)/include include - --include $(COMPONENT_PATH)/$(SOC_NAME)/component.mk \ No newline at end of file +-include $(COMPONENT_PATH)/$(TARGET)/component.mk \ No newline at end of file diff --git a/components/efuse/efuse_table_gen.py b/components/efuse/efuse_table_gen.py index 02940c27a..a5a8e52c9 100755 --- a/components/efuse/efuse_table_gen.py +++ b/components/efuse/efuse_table_gen.py @@ -28,6 +28,7 @@ __version__ = '1.0' quiet = False max_blk_len = 256 +idf_target = "esp32" copyright = '''// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD // @@ -244,35 +245,36 @@ class FuseTable(list): rows += [""] - rows += ["#define MAX_BLK_LEN CONFIG_EFUSE_MAX_BLK_LEN"] + if idf_target == "esp32": + rows += ["#define MAX_BLK_LEN CONFIG_EFUSE_MAX_BLK_LEN"] - rows += [""] + rows += [""] - last_free_bit_blk1 = self.get_str_position_last_free_bit_in_blk("EFUSE_BLK1") - last_free_bit_blk2 = self.get_str_position_last_free_bit_in_blk("EFUSE_BLK2") - last_free_bit_blk3 = self.get_str_position_last_free_bit_in_blk("EFUSE_BLK3") + last_free_bit_blk1 = self.get_str_position_last_free_bit_in_blk("EFUSE_BLK1") + last_free_bit_blk2 = self.get_str_position_last_free_bit_in_blk("EFUSE_BLK2") + last_free_bit_blk3 = self.get_str_position_last_free_bit_in_blk("EFUSE_BLK3") - rows += ["// The last free bit in the block is counted over the entire file."] - if last_free_bit_blk1 is not None: - rows += ["#define LAST_FREE_BIT_BLK1 " + last_free_bit_blk1] - if last_free_bit_blk2 is not None: - rows += ["#define LAST_FREE_BIT_BLK2 " + last_free_bit_blk2] - if last_free_bit_blk3 is not None: - rows += ["#define LAST_FREE_BIT_BLK3 " + last_free_bit_blk3] + rows += ["// The last free bit in the block is counted over the entire file."] + if last_free_bit_blk1 is not None: + rows += ["#define LAST_FREE_BIT_BLK1 " + last_free_bit_blk1] + if last_free_bit_blk2 is not None: + rows += ["#define LAST_FREE_BIT_BLK2 " + last_free_bit_blk2] + if last_free_bit_blk3 is not None: + rows += ["#define LAST_FREE_BIT_BLK3 " + last_free_bit_blk3] - rows += [""] + rows += [""] - if last_free_bit_blk1 is not None: - rows += ['_Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' - 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] - if last_free_bit_blk2 is not None: - rows += ['_Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' - 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] - if last_free_bit_blk3 is not None: - rows += ['_Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' - 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] + if last_free_bit_blk1 is not None: + rows += ['_Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' + 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] + if last_free_bit_blk2 is not None: + rows += ['_Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' + 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] + if last_free_bit_blk3 is not None: + rows += ['_Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. ' + 'Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");'] - rows += [""] + rows += [""] last_name = '' for p in self: @@ -348,8 +350,16 @@ class FuseDefinition(object): def parse_block(self, strval): if strval == "": raise InputError("Field 'efuse_block' can't be left empty.") - if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3"]: - raise InputError("Field 'efuse_block' should consist from EFUSE_BLK0..EFUSE_BLK3") + if idf_target == "esp32": + if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3"]: + raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK3") + + if idf_target == "esp32s2beta": + if strval not in ["EFUSE_BLK0", "EFUSE_BLK1", "EFUSE_BLK2", "EFUSE_BLK3", "EFUSE_BLK4", + "EFUSE_BLK5", "EFUSE_BLK6", "EFUSE_BLK7", "EFUSE_BLK8", "EFUSE_BLK9", + "EFUSE_BLK10"]: + raise InputError("Field 'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK10") + return strval def get_max_bits_of_block(self): @@ -450,17 +460,21 @@ def create_output_files(name, output_table, debug): def main(): global quiet global max_blk_len + global idf_target parser = argparse.ArgumentParser(description='ESP32 eFuse Manager') + parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32','esp32s2beta'], default='esp32') parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true') parser.add_argument('--debug', help='Create header file with debug info', default=False, action="store_false") parser.add_argument('--info', help='Print info about range of used bits', default=False, action="store_true") - parser.add_argument('--max_blk_len', help='Max number of bits in BLK1, BLK2 and BLK3', type=int, default=256) + parser.add_argument('--max_blk_len', help='Max number of bits in BLOCKs', type=int, default=256) parser.add_argument('common_input', help='Path to common CSV file to parse.', type=argparse.FileType('r')) parser.add_argument('custom_input', help='Path to custom CSV file to parse.', type=argparse.FileType('r'), nargs='?', default=None) args = parser.parse_args() + idf_target = args.idf_target + max_blk_len = args.max_blk_len print("Max number of bits in BLK %d" % (max_blk_len)) if max_blk_len not in [256, 192, 128]: diff --git a/components/efuse/esp32s2beta/component.mk b/components/efuse/esp32s2beta/component.mk new file mode 100644 index 000000000..e69de29bb diff --git a/components/efuse/esp32s2beta/esp_efuse_table.c b/components/efuse/esp32s2beta/esp_efuse_table.c new file mode 100644 index 000000000..076615a85 --- /dev/null +++ b/components/efuse/esp32s2beta/esp_efuse_table.c @@ -0,0 +1,939 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at", +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +#include "sdkconfig.h" +#include "esp_efuse.h" +#include +#include "esp_efuse_table.h" + +// md5_digest_table fc489601ff9b21658f4eb9c617ee072d +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_RTC_RAM_BOOT[] = { + {EFUSE_BLK0, 1, 1}, // Write protection for DIS_RTC_RAM_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { + {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { + {EFUSE_BLK0, 3, 1}, // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { + {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { + {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { + {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { + {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { + {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { + {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { + {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK1[] = { + {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, +}; + +static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { + {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { + {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 30, 1}, // Write protection for USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t RD_DIS_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +}; + +static const esp_efuse_desc_t RD_DIS_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +}; + +static const esp_efuse_desc_t RD_DIS_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +}; + +static const esp_efuse_desc_t RD_DIS_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +}; + +static const esp_efuse_desc_t RD_DIS_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +}; + +static const esp_efuse_desc_t RD_DIS_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +}; + +static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { + {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { + {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, +}; + +static const esp_efuse_desc_t DIS_ICACHE[] = { + {EFUSE_BLK0, 40, 1}, // Disable Icache, +}; + +static const esp_efuse_desc_t DIS_DCACHE[] = { + {EFUSE_BLK0, 41, 1}, // Disable Dcace, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode include boot_mode 0 1 2 3 6 7, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_DCACHE[] = { + {EFUSE_BLK0, 43, 1}, // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7, +}; + +static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, +}; + +static const esp_efuse_desc_t DIS_USB[] = { + {EFUSE_BLK0, 45, 1}, // Disable USB function, +}; + +static const esp_efuse_desc_t DIS_CAN[] = { + {EFUSE_BLK0, 46, 1}, // Disable CAN function, +}; + +static const esp_efuse_desc_t DIS_BOOT_REMAP[] = { + {EFUSE_BLK0, 47, 1}, // Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function, +}; + +static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 49, 1}, // Software disable jtag jtag can be activated again by hmac module, +}; + +static const esp_efuse_desc_t HARD_DIS_JTAG[] = { + {EFUSE_BLK0, 50, 1}, // Hardware disable jtag permanently disable jtag function, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 51, 1}, // Disable flash encrypt function, +}; + +static const esp_efuse_desc_t USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 56, 1}, // Exchange D+ D- pins, +}; + +static const esp_efuse_desc_t USB_EXT_PHY_ENABLE[] = { + {EFUSE_BLK0, 57, 1}, // Enable external PHY, +}; + +static const esp_efuse_desc_t VDD_SPI_XPD[] = { + {EFUSE_BLK0, 68, 1}, // VDD_SPI regulator power up, +}; + +static const esp_efuse_desc_t VDD_SPI_TIEH[] = { + {EFUSE_BLK0, 69, 1}, // VDD_SPI regulator tie high to vdda, +}; + +static const esp_efuse_desc_t VDD_SPI_FORCE[] = { + {EFUSE_BLK0, 70, 1}, // Force using eFuse configuration of VDD_SPI, +}; + +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, +}; + +static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 88, 4}, // Key0 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 92, 4}, // Key1 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 96, 4}, // Key2 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 100, 4}, // Key3 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 104, 4}, // Key4 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 108, 4}, // Key5 purpose, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 116, 1}, // Secure boot enable, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, +}; + +static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = { + {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4, +}; + +static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = { + {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1, +}; + +static const esp_efuse_desc_t DIS_TINY_BASIC[] = { + {EFUSE_BLK0, 131, 1}, // Disable tiny basic console in ROM, +}; + +static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 132, 1}, // Disable download through USB, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 133, 1}, // Enable security download mode, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print., +}; + +static const esp_efuse_desc_t PIN_POWER_SELECTION[] = { + {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., +}; + +static const esp_efuse_desc_t FLASH_TYPE[] = { + {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line, +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 138, 1}, // Force ROM code to send a resume command during SPI boot, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 139, 16}, // Secure version for anti-rollback, +}; + +static const esp_efuse_desc_t MAC_FACTORY[] = { + {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], + {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], + {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], + {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], + {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], + {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { + {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { + {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { + {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { + {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, +}; + +static const esp_efuse_desc_t CLK8M_FREQ[] = { + {EFUSE_BLK1, 114, 12}, // The frequency of 8M CLK (0.01MHz), +}; + +static const esp_efuse_desc_t SYS_DATA_PART0[] = { + {EFUSE_BLK1, 126, 66}, // System configuration, +}; + +static const esp_efuse_desc_t SYS_DATA_PART1[] = { + {EFUSE_BLK2, 0, 256}, // System configuration, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // User data, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // System configuration, +}; + + + + + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = { + &WR_DIS_DIS_RTC_RAM_BOOT[0], // Write protection for DIS_RTC_RAM_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { + &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { + &WR_DIS_GROUP_2[0], // Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { + &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { + &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { + &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { + &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { + &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { + &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { + &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { + &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { + &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { + &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { + &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { + &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { + &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { + &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { + &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { + &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { + &WR_DIS_USB_EXCHG_PINS[0], // Write protection for USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { + &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { + &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { + &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { + &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { + &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { + &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { + &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { + &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { + &DIS_ICACHE[0], // Disable Icache + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[] = { + &DIS_DCACHE[0], // Disable Dcace + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { + &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode include boot_mode 0 1 2 3 6 7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = { + &DIS_DOWNLOAD_DCACHE[0], // Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { + &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = { + &DIS_USB[0], // Disable USB function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { + &DIS_CAN[0], // Disable CAN function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[] = { + &DIS_BOOT_REMAP[0], // Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { + &SOFT_DIS_JTAG[0], // Software disable jtag jtag can be activated again by hmac module + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[] = { + &HARD_DIS_JTAG[0], // Hardware disable jtag permanently disable jtag function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encrypt function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { + &USB_EXCHG_PINS[0], // Exchange D+ D- pins + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[] = { + &USB_EXT_PHY_ENABLE[0], // Enable external PHY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[] = { + &VDD_SPI_XPD[0], // VDD_SPI regulator power up + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[] = { + &VDD_SPI_TIEH[0], // VDD_SPI regulator tie high to vdda + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[] = { + &VDD_SPI_FORCE[0], // Force using eFuse configuration of VDD_SPI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { + &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { + &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { + &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { + &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { + &KEY_PURPOSE_0[0], // Key0 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { + &KEY_PURPOSE_1[0], // Key1 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { + &KEY_PURPOSE_2[0], // Key2 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { + &KEY_PURPOSE_3[0], // Key3 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { + &KEY_PURPOSE_4[0], // Key4 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { + &KEY_PURPOSE_5[0], // Key5 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { + &SECURE_BOOT_EN[0], // Secure boot enable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { + &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { + &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = { + &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = { + &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_TINY_BASIC[] = { + &DIS_TINY_BASIC[0], // Disable tiny basic console in ROM + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = { + &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { + &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { + &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = { + &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { + &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { + &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { + &SECURE_VERSION[0], // Secure version for anti-rollback + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { + &MAC_FACTORY[0], // Factory MAC addr [0] + &MAC_FACTORY[1], // Factory MAC addr [1] + &MAC_FACTORY[2], // Factory MAC addr [2] + &MAC_FACTORY[3], // Factory MAC addr [3] + &MAC_FACTORY[4], // Factory MAC addr [4] + &MAC_FACTORY[5], // Factory MAC addr [5] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { + &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { + &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { + &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { + &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { + &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { + &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { + &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { + &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { + &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { + &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { + &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[] = { + &CLK8M_FREQ[0], // The frequency of 8M CLK (0.01MHz) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = { + &SYS_DATA_PART0[0], // System configuration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[] = { + &SYS_DATA_PART1[0], // System configuration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // System configuration + NULL +}; + diff --git a/components/efuse/esp32s2beta/esp_efuse_table.csv b/components/efuse/esp32s2beta/esp_efuse_table.csv new file mode 100644 index 000000000..0f95ec705 --- /dev/null +++ b/components/efuse/esp32s2beta/esp_efuse_table.csv @@ -0,0 +1,138 @@ +# field_name, | efuse_block, | bit_start, | bit_count, |comment # +# | (EFUSE_BLK0 | (0..255) | (1..-) | # +# | EFUSE_BLK1 | |MAX_BLK_LEN*| # +# | ... | | | # +# | EFUSE_BLK10)| | | # +########################################################################## +# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. +# !!!!!!!!!!! # +# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table" +# this will generate new source files, next rebuild all the sources. +# !!!!!!!!!!! # + +# EFUSE_RD_REPEAT_DATA BLOCK # +############################## + # EFUSE_RD_WR_DIS_REG # + # EFUSE_WR_DIS [WR_DIS 0 32] # + WR_DIS_RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + WR_DIS_DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT + WR_DIS_GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + WR_DIS_GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL + WR_DIS_SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT + WR_DIS_SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 + WR_DIS_SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 + WR_DIS_SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 + WR_DIS_KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 + WR_DIS_KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 + WR_DIS_KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 + WR_DIS_KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 + WR_DIS_KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 + WR_DIS_KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 + WR_DIS_SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN + WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + WR_DIS_GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION + WR_DIS_BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + WR_DIS_SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 + WR_DIS_USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA + WR_DIS_KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 + WR_DIS_KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 + WR_DIS_KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 + WR_DIS_KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 + WR_DIS_KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 + WR_DIS_KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 + WR_DIS_SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 + WR_DIS_USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS + + # EFUSE_RD_REPEAT_DATA0_REG # + # [RD_DIS 0 7] # + RD_DIS_KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 + RD_DIS_KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 + RD_DIS_KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 + RD_DIS_KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 + RD_DIS_KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 + RD_DIS_KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 + RD_DIS_SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 + DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM + DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache + DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace + DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 + DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 + DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function + DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function + DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function + DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function + SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, Software disable jtag jtag can be activated again by hmac module + HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, Hardware disable jtag permanently disable jtag function + DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode + USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, Exchange D+ D- pins + USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, Enable external PHY + + # EFUSE_RD_REPEAT_DATA1_REG # + VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up + VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda + VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI + WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold + SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key + SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key + SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key + KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose + KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose + + # EFUSE_RD_REPEAT_DATA2_REG # + KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose + KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose + KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose + KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose + SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable + SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke + FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + + # EFUSE_RD_REPEAT_DATA3_REG # + DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 + UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1 + DIS_TINY_BASIC, EFUSE_BLK0, 131, 1, Disable tiny basic console in ROM + DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB + ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode + UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. + PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line + FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, Force ROM code to send a resume command during SPI boot + SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback + + # EFUSE_RD_REPEAT_DATA4_REG # + + +# MAC_SPI_8M_SYS BLOCK# +####################### + MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] + , EFUSE_BLK1, 32, 8, Factory MAC addr [1] + , EFUSE_BLK1, 24, 8, Factory MAC addr [2] + , EFUSE_BLK1, 16, 8, Factory MAC addr [3] + , EFUSE_BLK1, 8, 8, Factory MAC addr [4] + , EFUSE_BLK1, 0, 8, Factory MAC addr [5] + SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK + SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) + SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) + SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS + SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) + SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) + SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS + SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 + SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 + SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 + SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + CLK8M_FREQ, EFUSE_BLK1, 114, 12, The frequency of 8M CLK (0.01MHz) + SYS_DATA_PART0, EFUSE_BLK1, 126, 66, System configuration + +################ +SYS_DATA_PART1, EFUSE_BLK2, 0, 256, System configuration +USER_DATA, EFUSE_BLK3, 0, 256, User data +KEY0, EFUSE_BLK4, 0, 256, Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration \ No newline at end of file diff --git a/components/efuse/esp32s2beta/include/esp_efuse_table.h b/components/efuse/esp32s2beta/include/esp_efuse_table.h new file mode 100644 index 000000000..3eaf5600c --- /dev/null +++ b/components/efuse/esp32s2beta/include/esp_efuse_table.h @@ -0,0 +1,131 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at", +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License + +#ifdef __cplusplus +extern "C" { +#endif + + +// md5_digest_table fc489601ff9b21658f4eb9c617ee072d +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TINY_BASIC[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CLK8M_FREQ[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; + +#ifdef __cplusplus +} +#endif + diff --git a/components/efuse/esp32s2beta/sources.cmake b/components/efuse/esp32s2beta/sources.cmake new file mode 100644 index 000000000..492216be2 --- /dev/null +++ b/components/efuse/esp32s2beta/sources.cmake @@ -0,0 +1 @@ +set(EFUSE_SOC_SRCS "esp_efuse_table.c") \ No newline at end of file diff --git a/components/efuse/include/esp32/esp_efuse.h b/components/efuse/include/esp32/esp_efuse.h new file mode 100644 index 000000000..43531820a --- /dev/null +++ b/components/efuse/include/esp32/esp_efuse.h @@ -0,0 +1,44 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks for ESP32 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse block. Reserved. */ + EFUSE_BLK1 = 1, /**< Number of eFuse block. Used for Flash Encryption. If not using that Flash Encryption feature, they can be used for another purpose. */ + EFUSE_BLK2 = 2, /**< Number of eFuse block. Used for Secure Boot. If not using that Secure Boot feature, they can be used for another purpose. */ + EFUSE_BLK3 = 3, /**< Number of eFuse block. Uses for the purpose of the user. */ + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_3_4 = 1, /**< 3/4 coding */ + EFUSE_CODING_SCHEME_REPEAT = 2, /**< Repeat coding */ +} esp_efuse_coding_scheme_t; + + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/include/esp32s2beta/esp_efuse.h b/components/efuse/include/esp32s2beta/esp_efuse.h new file mode 100644 index 000000000..94fbb2168 --- /dev/null +++ b/components/efuse/include/esp32s2beta/esp_efuse.h @@ -0,0 +1,69 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32S2BETA + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index 792d2a725..f1497dc26 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -21,6 +21,12 @@ extern "C" { #include #include "esp_err.h" #include "esp_log.h" +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/esp_efuse.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/esp_efuse.h" +#endif #define ESP_ERR_EFUSE 0x1600 /*!< Base error code for efuse api. */ #define ESP_OK_EFUSE_CNT (ESP_ERR_EFUSE + 0x01) /*!< OK the required number of bits is set. */ @@ -28,25 +34,6 @@ extern "C" { #define ESP_ERR_EFUSE_REPEATED_PROG (ESP_ERR_EFUSE + 0x03) /*!< Error repeated programming of programmed bits is strictly forbidden. */ #define ESP_ERR_CODING (ESP_ERR_EFUSE + 0x04) /*!< Error while a encoding operation. */ -/** - * @brief Type of eFuse blocks - */ -typedef enum { - EFUSE_BLK0 = 0, /**< Number of eFuse block. Reserved. */ - EFUSE_BLK1 = 1, /**< Number of eFuse block. Used for Flash Encryption. If not using that Flash Encryption feature, they can be used for another purpose. */ - EFUSE_BLK2 = 2, /**< Number of eFuse block. Used for Secure Boot. If not using that Secure Boot feature, they can be used for another purpose. */ - EFUSE_BLK3 = 3 /**< Number of eFuse block. Uses for the purpose of the user. */ -} esp_efuse_block_t; - -/** - * @brief Type of coding scheme - */ -typedef enum { - EFUSE_CODING_SCHEME_NONE = 0, /**< None */ - EFUSE_CODING_SCHEME_3_4 = 1, /**< 3/4 coding */ - EFUSE_CODING_SCHEME_REPEAT = 2, /**< Repeat coding */ -} esp_efuse_coding_scheme_t; - /** * @brief Structure eFuse field */ @@ -286,20 +273,6 @@ void esp_efuse_reset(void); */ void esp_efuse_disable_basic_rom_console(void); -/* @brief Encode one or more sets of 6 byte sequences into - * 8 bytes suitable for 3/4 Coding Scheme. - * - * This function is only useful if the CODING_SCHEME efuse - * is set to value 1 for 3/4 Coding Scheme. - * - * @param[in] in_bytes Pointer to a sequence of bytes to encode for 3/4 Coding Scheme. Must have length in_bytes_len. After being written to hardware, these bytes will read back as little-endian words. - * @param[out] out_words Pointer to array of words suitable for writing to efuse write registers. Array must contain 2 words (8 bytes) for every 6 bytes in in_bytes_len. Can be a pointer to efuse write registers. - * @param in_bytes_len. Length of array pointed to by in_bytes, in bytes. Must be a multiple of 6. - * - * @return ESP_ERR_INVALID_ARG if either pointer is null or in_bytes_len is not a multiple of 6. ESP_OK otherwise. - */ -esp_err_t esp_efuse_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len); - /* @brief Write random data to efuse key block write registers * * @note Caller is responsible for ensuring efuse diff --git a/components/efuse/private_include/esp32/esp_efuse_utility.h b/components/efuse/private_include/esp32/esp_efuse_utility.h new file mode 100644 index 000000000..36f23e611 --- /dev/null +++ b/components/efuse/private_include/esp32/esp_efuse_utility.h @@ -0,0 +1,49 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_BLOCKS 4 /* The number of blocks. */ +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK3 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(blk, max_num_bit) \ + esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(blk); \ + if ((scheme == EFUSE_CODING_SCHEME_3_4 && max_num_bit > 192) || \ + (scheme == EFUSE_CODING_SCHEME_REPEAT && max_num_bit > 128)) { \ + return false; \ + } + +/* @brief Encode one or more sets of 6 byte sequences into + * 8 bytes suitable for 3/4 Coding Scheme. + * + * This function is only useful if the CODING_SCHEME efuse + * is set to value 1 for 3/4 Coding Scheme. + * + * @param[in] in_bytes Pointer to a sequence of bytes to encode for 3/4 Coding Scheme. Must have length in_bytes_len. After being written to hardware, these bytes will read back as little-endian words. + * @param[out] out_words Pointer to array of words suitable for writing to efuse write registers. Array must contain 2 words (8 bytes) for every 6 bytes in in_bytes_len. Can be a pointer to efuse write registers. + * @param in_bytes_len. Length of array pointed to by in_bytes, in bytes. Must be a multiple of 6. + * + * @return ESP_ERR_INVALID_ARG if either pointer is null or in_bytes_len is not a multiple of 6. ESP_OK otherwise. + */ +esp_err_t esp_efuse_utility_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len); + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/private_include/esp32s2beta/esp_efuse_utility.h b/components/efuse/private_include/esp32s2beta/esp_efuse_utility.h new file mode 100644 index 000000000..a573d7504 --- /dev/null +++ b/components/efuse/private_include/esp32s2beta/esp_efuse_utility.h @@ -0,0 +1,30 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_BLOCKS 11 /* The number of blocks. */ +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/src/esp_efuse_utility.h b/components/efuse/private_include/esp_efuse_utility.h similarity index 91% rename from components/efuse/src/esp_efuse_utility.h rename to components/efuse/private_include/esp_efuse_utility.h index eadd80e02..c6b2e691a 100644 --- a/components/efuse/src/esp_efuse_utility.h +++ b/components/efuse/private_include/esp_efuse_utility.h @@ -12,8 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _ESP_EFUSE_UTILITY_H_ -#define _ESP_EFUSE_UTILITY_H_ +#pragma once #ifdef __cplusplus extern "C" { @@ -23,6 +22,20 @@ extern "C" { #include "esp_types.h" #include "esp_err.h" #include "esp_efuse.h" +#include "sdkconfig.h" +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/esp_efuse_utility.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/esp_efuse_utility.h" +#endif + +/** + * @brief Structure range address by blocks + */ +typedef struct { + uint32_t start; + uint32_t end; +} esp_efuse_range_addr_t; /** * @brief This is type of function that will handle the efuse field register. @@ -133,8 +146,11 @@ void esp_efuse_utility_erase_virt_blocks(void); */ esp_err_t esp_efuse_utility_apply_new_coding_scheme(void); +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + */ +void esp_efuse_utility_clear_program_registers(void); + #ifdef __cplusplus } #endif - -#endif // _ESP_EFUSE_UTILITY_H_ diff --git a/components/efuse/src/esp32/esp_efuse_api.c b/components/efuse/src/esp32/esp_efuse_api.c new file mode 100644 index 000000000..5cc14d770 --- /dev/null +++ b/components/efuse/src/esp32/esp_efuse_api.c @@ -0,0 +1,69 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "assert.h" +#include "sdkconfig.h" +#include "esp_efuse_table.h" + +const static char *TAG = "efuse"; + +// Sets a write protection for the whole block. +esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk) +{ + if (blk == EFUSE_BLK1) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK1, 1); + } else if (blk == EFUSE_BLK2) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK2, 1); + } else if (blk == EFUSE_BLK3) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK3, 1); + } + return ESP_ERR_NOT_SUPPORTED; +} + +// read protect for blk. +esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk) +{ + if (blk == EFUSE_BLK1) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_BLK1, 1); + } else if (blk == EFUSE_BLK2) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_BLK2, 1); + } else if (blk == EFUSE_BLK3) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_BLK3, 1); + } + return ESP_ERR_NOT_SUPPORTED; +} + +// get efuse coding_scheme. +esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk) +{ + esp_efuse_coding_scheme_t scheme; + if (blk == EFUSE_BLK0) { + scheme = EFUSE_CODING_SCHEME_NONE; + } else { + uint32_t coding_scheme = REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); + if (coding_scheme == EFUSE_CODING_SCHEME_VAL_NONE || + coding_scheme == (EFUSE_CODING_SCHEME_VAL_34 | EFUSE_CODING_SCHEME_VAL_REPEAT)) { + scheme = EFUSE_CODING_SCHEME_NONE; + } else if (coding_scheme == EFUSE_CODING_SCHEME_VAL_34) { + scheme = EFUSE_CODING_SCHEME_3_4; + } else { + scheme = EFUSE_CODING_SCHEME_REPEAT; + } + } + ESP_LOGD(TAG, "coding scheme %d", scheme); + return scheme; +} diff --git a/components/efuse/src/esp32/esp_efuse_fields.c b/components/efuse/src/esp32/esp_efuse_fields.c new file mode 100644 index 000000000..d76054cdf --- /dev/null +++ b/components/efuse/src/esp32/esp_efuse_fields.c @@ -0,0 +1,102 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_table.h" +#include "stdlib.h" +#include "esp_types.h" +#include "esp32/rom/efuse.h" +#include "assert.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/efuse_periph.h" +#include "bootloader_random.h" +#include "sys/param.h" +#include "soc/apb_ctrl_reg.h" + +const static char *TAG = "efuse"; + +// Contains functions that provide access to efuse fields which are often used in IDF. + +// Returns chip version from efuse +uint8_t esp_efuse_get_chip_ver(void) +{ + uint8_t eco_bit0, eco_bit1, eco_bit2; + esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1); + esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1); + eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 80000000) >> 31; + uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; + uint8_t chip_ver = 0; + switch (combine_value) { + case 0: + chip_ver = 0; + break; + case 1: + chip_ver = 1; + break; + case 3: + chip_ver = 2; + break; + case 7: + chip_ver = 3; + break; + default: + chip_ver = 0; + break; + } + return chip_ver; +} + +// Returns chip package from efuse +uint32_t esp_efuse_get_pkg_ver(void) +{ + uint32_t pkg_ver = 0; + esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_PKG, &pkg_ver, 3); + return pkg_ver; +} + +// Disable BASIC ROM Console via efuse +void esp_efuse_disable_basic_rom_console(void) +{ + uint8_t console_debug_disable = 0; + esp_efuse_read_field_blob(ESP_EFUSE_CONSOLE_DEBUG_DISABLE, &console_debug_disable, 1); + if (console_debug_disable == 0) { + esp_efuse_write_field_cnt(ESP_EFUSE_CONSOLE_DEBUG_DISABLE, 1); + ESP_EARLY_LOGI(TAG, "Disable BASIC ROM Console fallback via efuse..."); + } +} + +void esp_efuse_write_random_key(uint32_t blk_wdata0_reg) +{ + uint32_t buf[8]; + uint8_t raw[24]; + + if (esp_efuse_get_coding_scheme(EFUSE_BLK2) == EFUSE_CODING_SCHEME_NONE) { + bootloader_fill_random(buf, sizeof(buf)); + } else { // 3/4 Coding Scheme + bootloader_fill_random(raw, sizeof(raw)); + esp_err_t r = esp_efuse_utility_apply_34_encoding(raw, buf, sizeof(raw)); + (void) r; + assert(r == ESP_OK); + } + + ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg); + for (int i = 0; i < 8; i++) { + ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]); + REG_WRITE(blk_wdata0_reg + 4*i, buf[i]); + } + bzero(buf, sizeof(buf)); + bzero(raw, sizeof(raw)); +} diff --git a/components/efuse/src/esp32/esp_efuse_utility.c b/components/efuse/src/esp32/esp_efuse_utility.c new file mode 100644 index 000000000..2983ea958 --- /dev/null +++ b/components/efuse/src/esp32/esp_efuse_utility.c @@ -0,0 +1,234 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "esp32/clk.h" +#include "esp_log.h" +#include "assert.h" +#include "sdkconfig.h" +#include + +static const char *TAG = "efuse"; + +#ifdef CONFIG_EFUSE_VIRTUAL +extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK]; +#endif // CONFIG_EFUSE_VIRTUAL + +/*Range addresses to read blocks*/ +const esp_efuse_range_addr_t range_read_addr_blocks[] = { + {EFUSE_BLK0_RDATA0_REG, EFUSE_BLK0_RDATA6_REG}, // range address of EFUSE_BLK0 + {EFUSE_BLK1_RDATA0_REG, EFUSE_BLK1_RDATA7_REG}, // range address of EFUSE_BLK1 + {EFUSE_BLK2_RDATA0_REG, EFUSE_BLK2_RDATA7_REG}, // range address of EFUSE_BLK2 + {EFUSE_BLK3_RDATA0_REG, EFUSE_BLK3_RDATA7_REG} // range address of EFUSE_BLK3 +}; + +/*Range addresses to write blocks*/ +const esp_efuse_range_addr_t range_write_addr_blocks[] = { + {EFUSE_BLK0_WDATA0_REG, EFUSE_BLK0_WDATA6_REG}, // range address of EFUSE_BLK0 + {EFUSE_BLK1_WDATA0_REG, EFUSE_BLK1_WDATA7_REG}, // range address of EFUSE_BLK1 + {EFUSE_BLK2_WDATA0_REG, EFUSE_BLK2_WDATA7_REG}, // range address of EFUSE_BLK2 + {EFUSE_BLK3_WDATA0_REG, EFUSE_BLK3_WDATA7_REG} // range address of EFUSE_BLK3 +}; + +#define EFUSE_CONF_WRITE 0x5A5A /* eFuse_pgm_op_ena, force no rd/wr disable. */ +#define EFUSE_CONF_READ 0x5AA5 /* eFuse_read_op_ena, release force. */ +#define EFUSE_CMD_PGM 0x02 /* Command to program. */ +#define EFUSE_CMD_READ 0x01 /* Command to read. */ + +#ifndef CONFIG_EFUSE_VIRTUAL +// Update Efuse timing configuration +static esp_err_t esp_efuse_set_timing(void) +{ + uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; + uint32_t clk_sel0, clk_sel1, dac_clk_div; + if (apb_freq_mhz <= 26) { + clk_sel0 = 250; + clk_sel1 = 255; + dac_clk_div = 52; + } else if (apb_freq_mhz <= 40) { + clk_sel0 = 160; + clk_sel1 = 255; + dac_clk_div = 80; + } else { + clk_sel0 = 80; + clk_sel1 = 128; + dac_clk_div = 100; + } + REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0); + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1); + return ESP_OK; +} +#endif // ifndef CONFIG_EFUSE_VIRTUAL + +// Efuse read operation: copies data from physical efuses to efuse read registers. +void esp_efuse_utility_clear_program_registers(void) +{ + REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); +} + +// Burn values written to the efuse write registers +void esp_efuse_utility_burn_efuses(void) +{ +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) { + esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block); + if (scheme == EFUSE_CODING_SCHEME_3_4) { + uint8_t buf[COUNT_EFUSE_REG_PER_BLOCK * 4] = { 0 }; + int i = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) { + *((uint32_t*)buf + i) = REG_READ(addr_wr_block); + } + int j = 0; + uint32_t out_buf[COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; + for (int k = 0; k < 4; ++k, ++j) { + memcpy((uint8_t*)out_buf + j * 6, &buf[k * 8], 6); + } + for (int k = 0; k < COUNT_EFUSE_REG_PER_BLOCK; ++k) { + REG_WRITE(range_write_addr_blocks[num_block].start + k * 4, out_buf[k]); + } + } + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#else + esp_efuse_set_timing(); + // Permanently update values written to the efuse write registers + REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE); + REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM); + while (REG_READ(EFUSE_CMD_REG) != 0) {}; + REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); + REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ); + while (REG_READ(EFUSE_CMD_REG) != 0) {}; +#endif // CONFIG_EFUSE_VIRTUAL + esp_efuse_utility_reset(); +} + +esp_err_t esp_efuse_utility_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len) +{ + if (in_bytes == NULL || out_words == NULL || in_bytes_len % 6 != 0) { + return ESP_ERR_INVALID_ARG; + } + + while (in_bytes_len > 0) { + uint8_t out[8]; + uint8_t xor = 0; + uint8_t mul = 0; + for (int i = 0; i < 6; i++) { + xor ^= in_bytes[i]; + mul += (i + 1) * __builtin_popcount(in_bytes[i]); + } + + memcpy(out, in_bytes, 6); // Data bytes + out[6] = xor; + out[7] = mul; + + memcpy(out_words, out, 8); + + in_bytes_len -= 6; + in_bytes += 6; + out_words += 2; + } + + return ESP_OK; +} + +static bool read_w_data_and_check_fill(esp_efuse_block_t num_block, uint32_t *buf_w_data) +{ + bool blk_is_filled = false; + int i = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) { + buf_w_data[i] = REG_READ(addr_wr_block); + if (buf_w_data[i] != 0) { + REG_WRITE(addr_wr_block, 0); + blk_is_filled = true; + } + } + return blk_is_filled; +} + +static void read_r_data(esp_efuse_block_t num_block, uint32_t* buf_r_data) +{ + int i = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++i) { + buf_r_data[i] = esp_efuse_utility_read_reg(num_block, i); + } +} + +// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. +// This function reads EFUSE_BLKx_WDATAx_REG registers, applies coding scheme and writes encoded values back to EFUSE_BLKx_WDATAx_REG. +esp_err_t esp_efuse_utility_apply_new_coding_scheme() +{ + uint8_t buf_w_data[COUNT_EFUSE_REG_PER_BLOCK * 4]; + uint8_t buf_r_data[COUNT_EFUSE_REG_PER_BLOCK * 4]; + uint32_t reg[COUNT_EFUSE_REG_PER_BLOCK]; + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) { + esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block); + // check and apply a new coding scheme. + if (scheme != EFUSE_CODING_SCHEME_NONE) { + memset(buf_w_data, 0, sizeof(buf_w_data)); + memset((uint8_t*)reg, 0, sizeof(reg)); + if (read_w_data_and_check_fill(num_block, (uint32_t*)buf_w_data) == true) { + read_r_data(num_block, (uint32_t*)buf_r_data); + if (scheme == EFUSE_CODING_SCHEME_3_4) { + if (*((uint32_t*)buf_w_data + 6) != 0 || *((uint32_t*)buf_w_data + 7) != 0) { + return ESP_ERR_CODING; + } + for (int i = 0; i < 24; ++i) { + if (buf_w_data[i] != 0) { + int st_offset_buf = (i / 6) * 6; + // check that place is free. + for (int n = st_offset_buf; n < st_offset_buf + 6; ++n) { + if (buf_r_data[n] != 0) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + + esp_err_t err = esp_efuse_utility_apply_34_encoding(&buf_w_data[st_offset_buf], reg, 6); + if (err != ESP_OK) { + return err; + } + + int num_reg = (st_offset_buf / 6) * 2; + for (int r = 0; r < 2; r++) { + REG_WRITE(range_write_addr_blocks[num_block].start + (num_reg + r) * 4, reg[r]); + } + i = st_offset_buf + 5; + } + } + } else if (scheme == EFUSE_CODING_SCHEME_REPEAT) { + uint32_t* buf_32 = (uint32_t*)buf_w_data; + for (int i = 4; i < 8; ++i) { + if (*(buf_32 + i) != 0) { + return ESP_ERR_CODING; + } + } + for (int i = 0; i < 4; ++i) { + if (buf_32[i] != 0) { + REG_WRITE(range_write_addr_blocks[num_block].start + i * 4, buf_32[i]); + REG_WRITE(range_write_addr_blocks[num_block].start + (i + 4) * 4, buf_32[i]); + } + } + } + } + } + } + return ESP_OK; +} diff --git a/components/efuse/src/esp32s2beta/esp_efuse_api.c b/components/efuse/src/esp32s2beta/esp_efuse_api.c new file mode 100644 index 000000000..9eaeade7a --- /dev/null +++ b/components/efuse/src/esp32s2beta/esp_efuse_api.c @@ -0,0 +1,83 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "assert.h" +#include "sdkconfig.h" +#include "esp_efuse_table.h" + +const static char *TAG = "efuse"; + +// Sets a write protection for the whole block. +esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk) +{ + if (blk == EFUSE_BLK1) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK1, 1); + } else if (blk == EFUSE_BLK2) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART1, 1); + } else if (blk == EFUSE_BLK3) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_USER_DATA, 1); + } else if (blk == EFUSE_BLK4) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY0, 1); + } else if (blk == EFUSE_BLK5) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY1, 1); + } else if (blk == EFUSE_BLK6) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY2, 1); + } else if (blk == EFUSE_BLK7) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY3, 1); + } else if (blk == EFUSE_BLK8) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY4, 1); + } else if (blk == EFUSE_BLK9) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_KEY5, 1); + } else if (blk == EFUSE_BLK10) { + return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART2, 1); + } + return ESP_ERR_NOT_SUPPORTED; +} + +// read protect for blk. +esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk) +{ + if (blk == EFUSE_BLK4) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY0, 1); + } else if (blk == EFUSE_BLK5) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY1, 1); + } else if (blk == EFUSE_BLK6) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY2, 1); + } else if (blk == EFUSE_BLK7) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY3, 1); + } else if (blk == EFUSE_BLK8) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY4, 1); + } else if (blk == EFUSE_BLK9) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_KEY5, 1); + } else if (blk == EFUSE_BLK10) { + return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_SYS_DATA_PART2, 1); + } + return ESP_ERR_NOT_SUPPORTED; +} + +// get efuse coding_scheme. +esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk) +{ + esp_efuse_coding_scheme_t scheme; + if (blk == EFUSE_BLK0) { + scheme = EFUSE_CODING_SCHEME_NONE; + } else { + scheme = EFUSE_CODING_SCHEME_RS; + } + ESP_LOGD(TAG, "coding scheme %d", scheme); + return scheme; +} diff --git a/components/efuse/src/esp32s2beta/esp_efuse_fields.c b/components/efuse/src/esp32s2beta/esp_efuse_fields.c new file mode 100644 index 000000000..be4f111df --- /dev/null +++ b/components/efuse/src/esp32s2beta/esp_efuse_fields.c @@ -0,0 +1,76 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_table.h" +#include "stdlib.h" +#include "esp_types.h" +#include "esp32/rom/efuse.h" +#include "assert.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/efuse_periph.h" +#include "bootloader_random.h" +#include "sys/param.h" + +const static char *TAG = "efuse"; + +// Contains functions that provide access to efuse fields which are often used in IDF. + +// Returns chip version from efuse +uint8_t esp_efuse_get_chip_ver(void) +{ + uint32_t chip_ver = 0; + // TODO: ESP32S2BETA does not have this field + return chip_ver; +} + +// Returns chip package from efuse +uint32_t esp_efuse_get_pkg_ver(void) +{ + uint32_t pkg_ver = 0; + // TODO: ESP32S2BETA does not have this field + return pkg_ver; +} + +// Disable BASIC ROM Console via efuse +void esp_efuse_disable_basic_rom_console(void) +{ + uint8_t dis_tiny_basic = 0; + uint8_t dis_legacy_spi_boot = 0; + esp_efuse_read_field_blob(ESP_EFUSE_DIS_TINY_BASIC, &dis_tiny_basic, 1); + esp_efuse_read_field_blob(ESP_EFUSE_DIS_LEGACY_SPI_BOOT, &dis_legacy_spi_boot, 1); + if (dis_tiny_basic == 0 || dis_legacy_spi_boot == 0) { + esp_efuse_write_field_cnt(ESP_EFUSE_DIS_TINY_BASIC, 1); + esp_efuse_write_field_cnt(ESP_EFUSE_DIS_LEGACY_SPI_BOOT, 1); + ESP_EARLY_LOGI(TAG, "Disable tiny basic console in ROM and Disable_Legcy_SPI_boot mode..."); + } +} + +void esp_efuse_write_random_key(uint32_t blk_wdata0_reg) +{ + uint32_t buf[8]; + uint8_t raw[24]; + + bootloader_fill_random(buf, sizeof(buf)); + + ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg); + for (int i = 0; i < 8; i++) { + ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]); + REG_WRITE(blk_wdata0_reg + 4*i, buf[i]); + } + bzero(buf, sizeof(buf)); + bzero(raw, sizeof(raw)); +} diff --git a/components/efuse/src/esp32s2beta/esp_efuse_utility.c b/components/efuse/src/esp32s2beta/esp_efuse_utility.c new file mode 100644 index 000000000..d741384f5 --- /dev/null +++ b/components/efuse/src/esp32s2beta/esp_efuse_utility.c @@ -0,0 +1,178 @@ +// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "esp32s2beta/clk.h" +#include "esp_log.h" +#include "assert.h" +#include "sdkconfig.h" +#include +#include "esp32s2beta/rom/efuse.h" + +static const char *TAG = "efuse"; + +#ifdef CONFIG_EFUSE_VIRTUAL +extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK]; +#endif // CONFIG_EFUSE_VIRTUAL + +/*Range addresses to read blocks*/ +const esp_efuse_range_addr_t range_read_addr_blocks[] = { + {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_MAC_SPI_8M_0_REG, EFUSE_RD_MAC_SPI_8M_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M + {EFUSE_RD_SYS_DATA0_REG, EFUSE_RD_SYS_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA + {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 + {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 + {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 + {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 + {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 + {EFUSE_RD_KEY6_DATA0_REG, EFUSE_RD_KEY6_DATA7_REG} // range address of EFUSE_BLK10 KEY6 +}; + +static uint32_t write_mass_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; + +/*Range addresses to write blocks (it is not real regs, it is buffer) */ +const esp_efuse_range_addr_t range_write_addr_blocks[] = { + {(uint32_t)&write_mass_blocks[EFUSE_BLK0][0], (uint32_t)&write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK1][0], (uint32_t)&write_mass_blocks[EFUSE_BLK1][5]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK2][0], (uint32_t)&write_mass_blocks[EFUSE_BLK2][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK3][0], (uint32_t)&write_mass_blocks[EFUSE_BLK3][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK4][0], (uint32_t)&write_mass_blocks[EFUSE_BLK4][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK5][0], (uint32_t)&write_mass_blocks[EFUSE_BLK5][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK6][0], (uint32_t)&write_mass_blocks[EFUSE_BLK6][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK7][0], (uint32_t)&write_mass_blocks[EFUSE_BLK7][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK8][0], (uint32_t)&write_mass_blocks[EFUSE_BLK8][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK9][0], (uint32_t)&write_mass_blocks[EFUSE_BLK9][7]}, + {(uint32_t)&write_mass_blocks[EFUSE_BLK10][0], (uint32_t)&write_mass_blocks[EFUSE_BLK10][7]}, +}; + +#ifndef CONFIG_EFUSE_VIRTUAL +// Update Efuse timing configuration +static esp_err_t esp_efuse_set_timing(void) +{ + uint32_t clock = esp_clk_apb_freq(); + // ets_efuse_set_timing(clock); + uint32_t clk_div, power_on; + //uint32_t power_off; // Support for 7.2.3 chip + uint32_t tsup_a = 1, thp_a = 1, tpgm, tpgm_inact; + uint32_t tsur_a = 1, thr_a = 1, trd; + if (clock == 20000000 || clock == 5000000 || clock == 10000000) { + clk_div = 0x28; + power_on = 0x2880; + //power_off = 0x40; + tpgm = 0xc8; + tpgm_inact = 1; + trd = 1; + } else if (clock == 40000000) { + clk_div = 0x50; + power_on = 0x5100; + //power_off = 0x80; + tpgm = 0x190; + tpgm_inact = 2; + trd = 2; + } else if (clock == 80000000) { + clk_div = 0xa0; + power_on = 0xa200; + //power_off = 0x100; + tpgm = 0x320; + tpgm_inact = 3; + trd = 3; + } else { + ESP_LOGE(TAG, "Efuse does not support this %d Hz APB clock", clock); + return ESP_ERR_NOT_SUPPORTED; + } + REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div); + REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm); + REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact); + REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a); + REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on); + REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a); + //REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off); + REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a); + REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd); + REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a); + return ESP_OK; +} +#endif // ifndef CONFIG_EFUSE_VIRTUAL + +// Efuse read operation: copies data from physical efuses to efuse read registers. +void esp_efuse_utility_clear_program_registers(void) +{ + ets_efuse_read(); + ets_efuse_clear_program_registers(); +} + +// Burn values written to the efuse write registers +void esp_efuse_utility_burn_efuses(void) +{ +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) { + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#else + if (esp_efuse_set_timing() != ESP_OK) { + ESP_LOGE(TAG, "Efuse fields are not burnt"); + } else { + // Permanently update values written to the efuse write registers + for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block) != 0) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + uint8_t block_rs[12]; + ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); + } + int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); + ets_efuse_program(num_block); + break; + } + } + } + } +#endif // CONFIG_EFUSE_VIRTUAL + esp_efuse_utility_reset(); +} + +// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. +// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. +// The RS coding scheme does not require data changes for the encoded data. esp32s2beta has special registers for this. +// They will be filled during the burn operation. +esp_err_t esp_efuse_utility_apply_new_coding_scheme() +{ + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block)) { + int num_reg = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { + if (esp_efuse_utility_read_reg(num_block, num_reg)) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + break; + } + } + } + } + return ESP_OK; +} diff --git a/components/efuse/src/esp_efuse_api.c b/components/efuse/src/esp_efuse_api.c index 57a71970a..0e0ed00b0 100644 --- a/components/efuse/src/esp_efuse_api.c +++ b/components/efuse/src/esp_efuse_api.c @@ -114,32 +114,6 @@ esp_err_t esp_efuse_write_field_cnt(const esp_efuse_desc_t* field[], size_t cnt) return err; } -// Sets a write protection for the whole block. -esp_err_t esp_efuse_set_write_protect(esp_efuse_block_t blk) -{ - if (blk == EFUSE_BLK1) { - return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK1, 1); - } else if (blk == EFUSE_BLK2) { - return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK2, 1); - } else if (blk == EFUSE_BLK3) { - return esp_efuse_write_field_cnt(ESP_EFUSE_WR_DIS_BLK3, 1); - } - return ESP_ERR_NOT_SUPPORTED; -} - -// read protect for blk. -esp_err_t esp_efuse_set_read_protect(esp_efuse_block_t blk) -{ - if (blk == EFUSE_BLK1) { - return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_BLK1, 1); - } else if (blk == EFUSE_BLK2) { - return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_BLK2, 1); - } else if (blk == EFUSE_BLK3) { - return esp_efuse_write_field_cnt(ESP_EFUSE_RD_DIS_BLK3, 1); - } - return ESP_ERR_NOT_SUPPORTED; -} - // get the length of the field in bits int esp_efuse_get_field_size(const esp_efuse_desc_t* field[]) { @@ -180,32 +154,11 @@ esp_err_t esp_efuse_write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint3 return err; } -// get efuse coding_scheme. -esp_efuse_coding_scheme_t esp_efuse_get_coding_scheme(esp_efuse_block_t blk) -{ - esp_efuse_coding_scheme_t scheme; - if (blk == EFUSE_BLK0) { - scheme = EFUSE_CODING_SCHEME_NONE; - } else { - uint32_t coding_scheme = REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); - if (coding_scheme == EFUSE_CODING_SCHEME_VAL_NONE || - coding_scheme == (EFUSE_CODING_SCHEME_VAL_34 | EFUSE_CODING_SCHEME_VAL_REPEAT)) { - scheme = EFUSE_CODING_SCHEME_NONE; - } else if (coding_scheme == EFUSE_CODING_SCHEME_VAL_34) { - scheme = EFUSE_CODING_SCHEME_3_4; - } else { - scheme = EFUSE_CODING_SCHEME_REPEAT; - } - } - ESP_LOGD(TAG, "coding scheme %d", scheme); - return scheme; -} - // This function reads the key from the efuse block, starting at the offset and the required size. esp_err_t esp_efuse_read_block(esp_efuse_block_t blk, void* dst_key, size_t offset_in_bits, size_t size_bits) { esp_err_t err = ESP_OK; - if (blk == EFUSE_BLK0 || blk > EFUSE_BLK3 || dst_key == NULL || size_bits == 0) { + if (blk == EFUSE_BLK0 || blk >= EFUSE_BLK_MAX || dst_key == NULL || size_bits == 0) { err = ESP_ERR_INVALID_ARG; } else { const esp_efuse_desc_t field_desc[] = { @@ -225,7 +178,7 @@ esp_err_t esp_efuse_read_block(esp_efuse_block_t blk, void* dst_key, size_t offs esp_err_t esp_efuse_write_block(esp_efuse_block_t blk, const void* src_key, size_t offset_in_bits, size_t size_bits) { esp_err_t err = ESP_OK; - if (blk == EFUSE_BLK0 || blk > EFUSE_BLK3 || src_key == NULL || size_bits == 0) { + if (blk == EFUSE_BLK0 || blk >= EFUSE_BLK_MAX || src_key == NULL || size_bits == 0) { err = ESP_ERR_INVALID_ARG; } else { const esp_efuse_desc_t field_desc[] = { diff --git a/components/efuse/src/esp_efuse_fields.c b/components/efuse/src/esp_efuse_fields.c index 313bbc611..640098b8f 100644 --- a/components/efuse/src/esp_efuse_fields.c +++ b/components/efuse/src/esp_efuse_fields.c @@ -24,47 +24,7 @@ #include "soc/efuse_periph.h" #include "bootloader_random.h" #include "soc/apb_ctrl_reg.h" - -const static char *TAG = "efuse"; - -// Contains functions that provide access to efuse fields which are often used in IDF. - -// Returns chip version from efuse -uint8_t esp_efuse_get_chip_ver(void) -{ - uint8_t eco_bit0, eco_bit1, eco_bit2; - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1); - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1); - eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 80000000) >> 31; - uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; - uint8_t chip_ver = 0; - switch (combine_value) { - case 0: - chip_ver = 0; - break; - case 1: - chip_ver = 1; - break; - case 3: - chip_ver = 2; - break; - case 7: - chip_ver = 3; - break; - default: - chip_ver = 0; - break; - } - return chip_ver; -} - -// Returns chip package from efuse -uint32_t esp_efuse_get_pkg_ver(void) -{ - uint32_t pkg_ver = 0; - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_PKG, &pkg_ver, 3); - return pkg_ver; -} +#include "sys/param.h" // Permanently update values written to the efuse write registers void esp_efuse_burn_new_values(void) @@ -78,74 +38,15 @@ void esp_efuse_reset(void) esp_efuse_utility_reset(); } -// Disable BASIC ROM Console via efuse -void esp_efuse_disable_basic_rom_console(void) -{ - if (esp_efuse_write_field_cnt(ESP_EFUSE_CONSOLE_DEBUG_DISABLE, 1) == ESP_OK) { - ESP_EARLY_LOGI(TAG, "Disable BASIC ROM Console fallback via efuse..."); - } -} - -esp_err_t esp_efuse_apply_34_encoding(const uint8_t *in_bytes, uint32_t *out_words, size_t in_bytes_len) -{ - if (in_bytes == NULL || out_words == NULL || in_bytes_len % 6 != 0) { - return ESP_ERR_INVALID_ARG; - } - - while (in_bytes_len > 0) { - uint8_t out[8]; - uint8_t xor = 0; - uint8_t mul = 0; - for (int i = 0; i < 6; i++) { - xor ^= in_bytes[i]; - mul += (i + 1) * __builtin_popcount(in_bytes[i]); - } - - memcpy(out, in_bytes, 6); // Data bytes - out[6] = xor; - out[7] = mul; - - memcpy(out_words, out, 8); - - in_bytes_len -= 6; - in_bytes += 6; - out_words += 2; - } - - return ESP_OK; -} - -void esp_efuse_write_random_key(uint32_t blk_wdata0_reg) -{ - uint32_t buf[8]; - uint8_t raw[24]; - uint32_t coding_scheme = REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_CODING_SCHEME_M; - - if (coding_scheme == EFUSE_CODING_SCHEME_VAL_NONE) { - bootloader_fill_random(buf, sizeof(buf)); - } else { // 3/4 Coding Scheme - bootloader_fill_random(raw, sizeof(raw)); - esp_err_t r = esp_efuse_apply_34_encoding(raw, buf, sizeof(raw)); - (void) r; - assert(r == ESP_OK); - } - - ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg); - for (int i = 0; i < 8; i++) { - ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]); - REG_WRITE(blk_wdata0_reg + 4 * i, buf[i]); - } - bzero(buf, sizeof(buf)); - bzero(raw, sizeof(raw)); -} - #ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE #include "../include_bootloader/bootloader_flash.h" #include "esp_flash_encrypt.h" +const static char *TAG = "efuse"; static uint32_t esp_efuse_flash_offset = 0; static uint32_t esp_efuse_flash_size = 0; + void esp_efuse_init(uint32_t offset, uint32_t size) { esp_efuse_flash_offset = offset; @@ -186,24 +87,21 @@ static void emulate_secure_version_write(uint32_t secure_version) } ESP_LOGV(TAG, "Write 0x%08x secure_version into flash", secure_version); } -#endif - -// This efuse register is used whole for secure version (32 bits). -#define EFUSE_BLK_RD_ANTI_ROLLBACK EFUSE_BLK3_RDATA4_REG -#define EFUSE_BLK_WR_ANTI_ROLLBACK EFUSE_BLK3_WDATA4_REG +#endif // CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE uint32_t esp_efuse_read_secure_version(void) { #ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK - uint32_t secure_version; - + uint32_t secure_version = 0; + int size = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION); + size = MIN(CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD, size); #ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE secure_version = emulate_secure_version_read(); #else - secure_version = REG_READ(EFUSE_BLK_RD_ANTI_ROLLBACK); + esp_efuse_read_field_blob(ESP_EFUSE_SECURE_VERSION, &secure_version, size); #endif // CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE - return __builtin_popcount(secure_version & ((1ULL << CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD) - 1)); + return __builtin_popcount(secure_version & ((1ULL << size) - 1)); #else return 0; #endif @@ -212,12 +110,12 @@ uint32_t esp_efuse_read_secure_version(void) #ifdef CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK static void write_anti_rollback(uint32_t new_bits) { + int size = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION); + size = MIN(CONFIG_BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD, size); #ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE emulate_secure_version_write(new_bits); #else - esp_efuse_reset(); - REG_WRITE(EFUSE_BLK_WR_ANTI_ROLLBACK, new_bits); - esp_efuse_burn_new_values(); + esp_efuse_write_field_blob(ESP_EFUSE_SECURE_VERSION, &new_bits, size); #endif } #endif @@ -236,9 +134,9 @@ esp_err_t esp_efuse_update_secure_version(uint32_t secure_version) return ESP_ERR_INVALID_ARG; } #ifndef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE - uint32_t coding_scheme = REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_CODING_SCHEME_M; - if (coding_scheme != EFUSE_CODING_SCHEME_VAL_NONE) { - ESP_LOGE(TAG, "Anti rollback is not supported with a 3/4 coding scheme."); + esp_efuse_coding_scheme_t coding_scheme = esp_efuse_get_coding_scheme(ESP_EFUSE_SECURE_VERSION_NUM_BLOCK); + if (coding_scheme != EFUSE_CODING_SCHEME_NONE) { + ESP_LOGE(TAG, "Anti rollback is not supported with any coding scheme."); return ESP_ERR_NOT_SUPPORTED; } #endif diff --git a/components/efuse/src/esp_efuse_utility.c b/components/efuse/src/esp_efuse_utility.c index 5f61b5cbd..108cba17e 100644 --- a/components/efuse/src/esp_efuse_utility.c +++ b/components/efuse/src/esp_efuse_utility.c @@ -15,7 +15,6 @@ #include "esp_efuse_utility.h" #include "soc/efuse_periph.h" -#include "esp32/clk.h" #include "esp_log.h" #include "assert.h" #include "sdkconfig.h" @@ -23,45 +22,16 @@ static const char *TAG = "efuse"; -#define COUNT_EFUSE_BLOCKS 4 /* The number of blocks. */ -#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ -#define EFUSE_CONF_WRITE 0x5A5A /* eFuse_pgm_op_ena, force no rd/wr disable. */ -#define EFUSE_CONF_READ 0x5AA5 /* eFuse_read_op_ena, release force. */ -#define EFUSE_CMD_PGM 0x02 /* Command to program. */ -#define EFUSE_CMD_READ 0x01 /* Command to read. */ - // Array for emulate efuse registers. #ifdef CONFIG_EFUSE_VIRTUAL -static uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK]; +uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK]; /* Call the update function to seed virtual efuses during initialization */ __attribute__((constructor)) void esp_efuse_utility_update_virt_blocks(void); - #endif -/** - * @brief Structure range address by blocks - */ -typedef struct { - uint32_t start; - uint32_t end; -} esp_efuse_range_addr_t; - -/*Range addresses to read blocks*/ -static const esp_efuse_range_addr_t range_read_addr_blocks[] = { - {EFUSE_BLK0_RDATA0_REG, EFUSE_BLK0_RDATA6_REG}, // range address of EFUSE_BLK0 - {EFUSE_BLK1_RDATA0_REG, EFUSE_BLK1_RDATA7_REG}, // range address of EFUSE_BLK1 - {EFUSE_BLK2_RDATA0_REG, EFUSE_BLK2_RDATA7_REG}, // range address of EFUSE_BLK2 - {EFUSE_BLK3_RDATA0_REG, EFUSE_BLK3_RDATA7_REG} // range address of EFUSE_BLK3 -}; - -/*Range addresses to write blocks*/ -static const esp_efuse_range_addr_t range_write_addr_blocks[] = { - {EFUSE_BLK0_WDATA0_REG, EFUSE_BLK0_WDATA6_REG}, // range address of EFUSE_BLK0 - {EFUSE_BLK1_WDATA0_REG, EFUSE_BLK1_WDATA7_REG}, // range address of EFUSE_BLK1 - {EFUSE_BLK2_WDATA0_REG, EFUSE_BLK2_WDATA7_REG}, // range address of EFUSE_BLK2 - {EFUSE_BLK3_WDATA0_REG, EFUSE_BLK3_WDATA7_REG} // range address of EFUSE_BLK3 -}; +extern const esp_efuse_range_addr_t range_read_addr_blocks[]; +extern const esp_efuse_range_addr_t range_write_addr_blocks[]; static int get_reg_num(int bit_start, int bit_count, int i_reg); static int get_starting_bit_num_in_reg(int bit_start, int i_reg); @@ -174,7 +144,7 @@ esp_err_t esp_efuse_utility_write_cnt(unsigned int num_reg, esp_efuse_block_t ef // Reset efuse write registers void esp_efuse_utility_reset(void) { - REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); + esp_efuse_utility_clear_program_registers(); for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) { for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { REG_WRITE(addr_wr_block, 0); @@ -182,65 +152,6 @@ void esp_efuse_utility_reset(void) } } -// Burn values written to the efuse write registers -void esp_efuse_utility_burn_efuses(void) -{ -#ifdef CONFIG_EFUSE_VIRTUAL - ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); - for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) { - esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block); - if (scheme == EFUSE_CODING_SCHEME_3_4) { - uint8_t buf[COUNT_EFUSE_REG_PER_BLOCK * 4] = { 0 }; - int i = 0; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) { - *((uint32_t*)buf + i) = REG_READ(addr_wr_block); - } - int j = 0; - uint32_t out_buf[COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; - for (int k = 0; k < 4; ++k, ++j) { - memcpy((uint8_t*)out_buf + j * 6, &buf[k * 8], 6); - } - for (int k = 0; k < COUNT_EFUSE_REG_PER_BLOCK; ++k) { - REG_WRITE(range_write_addr_blocks[num_block].start + k * 4, out_buf[k]); - } - } - int subblock = 0; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { - virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); - } - } -#else - // Update Efuse timing configuration - uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; - uint32_t clk_sel0, clk_sel1, dac_clk_div; - if (apb_freq_mhz <= 26) { - clk_sel0 = 250; - clk_sel1 = 255; - dac_clk_div = 52; - } else if (apb_freq_mhz <= 40) { - clk_sel0 = 160; - clk_sel1 = 255; - dac_clk_div = 80; - } else { - clk_sel0 = 80; - clk_sel1 = 128; - dac_clk_div = 100; - } - REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, clk_sel0); - REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, clk_sel1); - // Permanently update values written to the efuse write registers - REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_WRITE); - REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_PGM); - while (REG_READ(EFUSE_CMD_REG) != 0) {}; - REG_WRITE(EFUSE_CONF_REG, EFUSE_CONF_READ); - REG_WRITE(EFUSE_CMD_REG, EFUSE_CMD_READ); - while (REG_READ(EFUSE_CMD_REG) != 0) {}; -#endif - esp_efuse_utility_reset(); -} - - // Erase the virt_blocks array. void esp_efuse_utility_erase_virt_blocks(void) { @@ -314,13 +225,9 @@ esp_err_t esp_efuse_utility_write_reg(esp_efuse_block_t efuse_block, unsigned in // Reading efuse register. uint32_t esp_efuse_utility_read_reg(esp_efuse_block_t blk, unsigned int num_reg) { - assert(blk >= 0 && blk <= 3); - if (blk == 0) { - assert(num_reg <= 6); - } else { - assert(num_reg <= 7); - } - + assert(blk >= 0 && blk < EFUSE_BLK_MAX); + unsigned int max_num_reg = (range_read_addr_blocks[blk].end - range_read_addr_blocks[blk].start) / sizeof(uint32_t); + assert(num_reg <= max_num_reg); uint32_t value; #ifdef CONFIG_EFUSE_VIRTUAL value = virt_blocks[blk][num_reg]; @@ -335,12 +242,9 @@ uint32_t esp_efuse_utility_read_reg(esp_efuse_block_t blk, unsigned int num_reg) // writing efuse register. static void write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t value) { - assert(blk >= 0 && blk <= 3); - if (blk == 0) { - assert(num_reg <= 6); - } else { - assert(num_reg <= 7); - } + assert(blk >= 0 && blk < EFUSE_BLK_MAX); + unsigned int max_num_reg = (range_read_addr_blocks[blk].end - range_read_addr_blocks[blk].start) / sizeof(uint32_t); + assert(num_reg <= max_num_reg); uint32_t addr_wr_reg = range_write_addr_blocks[blk].start + num_reg * 4; uint32_t reg_to_write = REG_READ(addr_wr_reg) | value; // The register can be written in parts so we combine the new value with the one already available. @@ -440,97 +344,11 @@ static uint32_t set_cnt_in_reg(int bit_start_in_reg, int bit_count_used_in_reg, // check range of bits for any coding scheme. static bool check_range_of_bits(esp_efuse_block_t blk, int offset_in_bits, int size_bits) { - esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(blk); int max_num_bit = offset_in_bits + size_bits; - if ((scheme == EFUSE_CODING_SCHEME_NONE && max_num_bit > 256) || - (scheme == EFUSE_CODING_SCHEME_3_4 && max_num_bit > 192) || - (scheme == EFUSE_CODING_SCHEME_REPEAT && max_num_bit > 128)) { + if (max_num_bit > 256) { return false; + } else { + ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(blk, max_num_bit); } return true; } - -static bool read_w_data_and_check_fill(esp_efuse_block_t num_block, uint32_t *buf_w_data) -{ - bool blk_is_filled = false; - int i = 0; - for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, ++i) { - buf_w_data[i] = REG_READ(addr_wr_block); - if (buf_w_data[i] != 0) { - REG_WRITE(addr_wr_block, 0); - blk_is_filled = true; - } - } - return blk_is_filled; -} - -static void read_r_data(esp_efuse_block_t num_block, uint32_t* buf_r_data) -{ - int i = 0; - for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++i) { - buf_r_data[i] = REG_READ(addr_rd_block); - } -} - -// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. -// This function reads EFUSE_BLKx_WDATAx_REG registers, applies coding scheme and writes encoded values back to EFUSE_BLKx_WDATAx_REG. -esp_err_t esp_efuse_utility_apply_new_coding_scheme(void) -{ - uint8_t buf_w_data[COUNT_EFUSE_REG_PER_BLOCK * 4]; - uint8_t buf_r_data[COUNT_EFUSE_REG_PER_BLOCK * 4]; - uint32_t reg[COUNT_EFUSE_REG_PER_BLOCK]; - // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. - for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) { - esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(num_block); - // check and apply a new coding scheme. - if (scheme != EFUSE_CODING_SCHEME_NONE) { - memset(buf_w_data, 0, sizeof(buf_w_data)); - memset((uint8_t*)reg, 0, sizeof(reg)); - if (read_w_data_and_check_fill(num_block, (uint32_t*)buf_w_data) == true) { - read_r_data(num_block, (uint32_t*)buf_r_data); - if (scheme == EFUSE_CODING_SCHEME_3_4) { - if (*((uint32_t*)buf_w_data + 6) != 0 || *((uint32_t*)buf_w_data + 7) != 0) { - return ESP_ERR_CODING; - } - for (int i = 0; i < 24; ++i) { - if (buf_w_data[i] != 0) { - int st_offset_buf = (i / 6) * 6; - // check that place is free. - for (int n = st_offset_buf; n < st_offset_buf + 6; ++n) { - if (buf_r_data[n] != 0) { - ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); - return ESP_ERR_CODING; - } - } - - esp_err_t err = esp_efuse_apply_34_encoding(&buf_w_data[st_offset_buf], reg, 6); - if (err != ESP_OK) { - return err; - } - - int num_reg = (st_offset_buf / 6) * 2; - for (int r = 0; r < 2; r++) { - REG_WRITE(range_write_addr_blocks[num_block].start + (num_reg + r) * 4, reg[r]); - } - i = st_offset_buf + 5; - } - } - } else if (scheme == EFUSE_CODING_SCHEME_REPEAT) { - uint32_t* buf_32 = (uint32_t*)buf_w_data; - for (int i = 4; i < 8; ++i) { - if (*(buf_32 + i) != 0) { - return ESP_ERR_CODING; - } - } - for (int i = 0; i < 4; ++i) { - if (buf_32[i] != 0) { - REG_WRITE(range_write_addr_blocks[num_block].start + i * 4, buf_32[i]); - REG_WRITE(range_write_addr_blocks[num_block].start + (i + 4) * 4, buf_32[i]); - } - } - } - } - } - } - return ESP_OK; -} diff --git a/components/efuse/test/CMakeLists.txt b/components/efuse/test/CMakeLists.txt index 9524509ea..dcb4d58c7 100644 --- a/components/efuse/test/CMakeLists.txt +++ b/components/efuse/test/CMakeLists.txt @@ -1,6 +1,5 @@ -if(IDF_TARGET STREQUAL "esp32") - idf_component_register(SRC_DIRS . - INCLUDE_DIRS . include - REQUIRES unity test_utils efuse bootloader_support - ) -endif() +idf_component_register(SRC_DIRS "." ${IDF_TARGET} + INCLUDE_DIRS "." "include" + PRIV_INCLUDE_DIRS "../private_include" + REQUIRES unity test_utils efuse bootloader_support + ) \ No newline at end of file diff --git a/components/efuse/test/component.mk b/components/efuse/test/component.mk index 5dda86047..e1f27bc79 100644 --- a/components/efuse/test/component.mk +++ b/components/efuse/test/component.mk @@ -2,5 +2,7 @@ #Component Makefile # COMPONENT_ADD_INCLUDEDIRS := include +COMPONENT_SRCDIRS := . ${IDF_TARGET} +COMPONENT_PRIV_INCLUDEDIRS = "../private_include" COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive diff --git a/components/efuse/test/esp32/test_efuse.c b/components/efuse/test/esp32/test_efuse.c new file mode 100644 index 000000000..027a339f3 --- /dev/null +++ b/components/efuse/test/esp32/test_efuse.c @@ -0,0 +1,67 @@ +#include +#include +#include +#include +#include +#include "unity.h" +#include "esp_log.h" +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_test_table.h" +#include "esp32/rom/efuse.h" +#include "bootloader_random.h" +#include "sdkconfig.h" + + +#ifdef CONFIG_EFUSE_VIRTUAL +TEST_CASE("Test a write/read protection", "[efuse]") +{ + esp_efuse_utility_reset(); + esp_efuse_utility_erase_virt_blocks(); + + esp_efuse_utility_debug_dump_blocks(); + + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_write_protect(EFUSE_BLK0)); + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_read_protect(EFUSE_BLK0)); + + size_t out_cnt; + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt); + TEST_ASSERT_EQUAL_INT(0, out_cnt); + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK1)); + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_write_protect(EFUSE_BLK1)); + + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK2)); + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK2, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK3)); + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK3, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + esp_efuse_utility_debug_dump_blocks(); + + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK1, &out_cnt); + TEST_ASSERT_EQUAL_INT(0, out_cnt); + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK1)); + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK1, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_read_protect(EFUSE_BLK1)); + + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK2)); + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK2, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK3)); + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK3, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + esp_efuse_utility_debug_dump_blocks(); + esp_efuse_utility_reset(); + esp_efuse_utility_erase_virt_blocks(); +} + +#endif // #ifdef CONFIG_EFUSE_VIRTUAL diff --git a/components/efuse/test/test_efuse_coding_scheme.c b/components/efuse/test/esp32/test_efuse_coding_scheme.c similarity index 95% rename from components/efuse/test/test_efuse_coding_scheme.c rename to components/efuse/test/esp32/test_efuse_coding_scheme.c index cccacb5d6..6485f2a7e 100644 --- a/components/efuse/test/test_efuse_coding_scheme.c +++ b/components/efuse/test/esp32/test_efuse_coding_scheme.c @@ -1,7 +1,7 @@ #include #include #include "esp_efuse.h" -#include "../src/esp_efuse_utility.h" +#include "esp_efuse_utility.h" #include "soc/efuse_periph.h" #include "unity.h" #include "bootloader_random.h" @@ -82,20 +82,21 @@ TEST_CASE("Test 3/4 Coding Scheme Algorithm", "[efuse]") const coding_scheme_test_t *t = &coding_scheme_data[i]; printf("Test case %d...\n", i); - esp_err_t r = esp_efuse_apply_34_encoding(t->unencoded, result, sizeof(t->unencoded)); + esp_err_t r = esp_efuse_utility_apply_34_encoding(t->unencoded, result, sizeof(t->unencoded)); TEST_ASSERT_EQUAL_HEX(ESP_OK, r); TEST_ASSERT_EQUAL_HEX32_ARRAY(t->encoded, result, 8); // Do the same, 6 bytes at a time for (int offs = 0; offs < sizeof(t->unencoded); offs += 6) { bzero(result, sizeof(result)); - r = esp_efuse_apply_34_encoding(t->unencoded + offs, result, 6); + r = esp_efuse_utility_apply_34_encoding(t->unencoded + offs, result, 6); TEST_ASSERT_EQUAL_HEX(ESP_OK, r); TEST_ASSERT_EQUAL_HEX32_ARRAY(t->encoded + (offs / 6 * 2), result, 2); } } } +#if CONFIG_IDF_TARGET_ESP32 TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]") { int count_useful_reg = 0; @@ -117,6 +118,7 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]") useful_data_in_byte = count_useful_reg * 4; for (int i = 0; i < 10; ++i) { + esp_efuse_utility_erase_virt_blocks(); printf("Test case %d...\n", i); memset(buf, 0, sizeof(buf)); memset(encoded, 0, sizeof(encoded)); @@ -140,7 +142,7 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]") if (coding_scheme == EFUSE_CODING_SCHEME_NONE) { memcpy((uint8_t*)encoded, buf, sizeof(buf)); } else if (coding_scheme == EFUSE_CODING_SCHEME_3_4) { - TEST_ESP_OK(esp_efuse_apply_34_encoding(buf, encoded, useful_data_in_byte)); + TEST_ESP_OK(esp_efuse_utility_apply_34_encoding(buf, encoded, useful_data_in_byte)); } else if (coding_scheme == EFUSE_CODING_SCHEME_REPEAT) { for (int j = 0; j < count_useful_reg; ++j) { encoded[j] = *((uint32_t*)buf + j); @@ -172,7 +174,9 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]") esp_efuse_utility_reset(); bootloader_random_disable(); } +#endif +#if CONFIG_IDF_TARGET_ESP32 TEST_CASE("Test data does not match the coding scheme", "[efuse]") { int count_useful_reg = 0; @@ -202,3 +206,4 @@ TEST_CASE("Test data does not match the coding scheme", "[efuse]") esp_efuse_utility_reset(); } +#endif diff --git a/components/efuse/test/esp32s2beta/test_efuse.c b/components/efuse/test/esp32s2beta/test_efuse.c new file mode 100644 index 000000000..80e310188 --- /dev/null +++ b/components/efuse/test/esp32s2beta/test_efuse.c @@ -0,0 +1,130 @@ +#include +#include +#include +#include +#include +#include "unity.h" +#include "esp_log.h" +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_test_table.h" +#include "esp32/rom/efuse.h" +#include "bootloader_random.h" +#include "sdkconfig.h" + + +//#define MANUAL_FPGA_TEST + +#if defined(MANUAL_FPGA_TEST) && defined(CONFIG_IDF_TARGET_ESP32S2BETA) && !defined(CONFIG_EFUSE_VIRTUAL) +TEST_CASE("Test a real write (FPGA)", "[efuse]") +{ + ESP_LOGI(TAG, "1. Write MAC address"); + esp_efuse_utility_debug_dump_blocks(); + uint8_t mac[6]; + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, &mac, sizeof(mac) * 8)); + ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + uint8_t new_mac[6]; + if (mac[0] == 0) { + new_mac[0] = 0x71; + new_mac[1] = 0x62; + new_mac[2] = 0x53; + new_mac[3] = 0x44; + new_mac[4] = 0x35; + new_mac[5] = 0x26; + TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_MAC_FACTORY, &new_mac, sizeof(new_mac) * 8)); + ESP_LOGI(TAG, "new MAC: %02x:%02x:%02x:%02x:%02x:%02x", new_mac[0], new_mac[1], new_mac[2], new_mac[3], new_mac[4], new_mac[5]); + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, &mac, sizeof(mac) * 8)); + TEST_ASSERT_EQUAL_HEX8_ARRAY(new_mac, mac, sizeof(new_mac)); + esp_efuse_utility_debug_dump_blocks(); + } + + ESP_LOGI(TAG, "2. Write KEY3"); + uint8_t key[32] = {0}; + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256)); + for (int i = 0; i < sizeof(key); ++i) { + TEST_ASSERT_EQUAL_INT(0, key[i]); + } + uint8_t new_key[32] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 12, 14, 15, 16, 17, 18, 19, + 20, 21, 22, 22, 24, 25, 26, 27, 28, 29, + 30, 31}; + TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_KEY3, &new_key, 256)); + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256)); + TEST_ASSERT_EQUAL_HEX8_ARRAY(new_key, key, sizeof(new_mac)); + esp_efuse_utility_debug_dump_blocks(); + + ESP_LOGI(TAG, "3. Set a read protection for KEY3"); + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK7)); + TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256)); + for (int i = 0; i < sizeof(key); ++i) { + TEST_ASSERT_EQUAL_INT(0, key[i]); + } + esp_efuse_utility_debug_dump_blocks(); + + ESP_LOGI(TAG, "4. Write SECURE_VERSION"); + int max_bits = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION); + size_t read_sec_version; + esp_efuse_utility_debug_dump_blocks(); + for (int i = 0; i < max_bits; ++i) { + ESP_LOGI(TAG, "# %d", i); + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_SECURE_VERSION, 1)); + TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_SECURE_VERSION, &read_sec_version)); + esp_efuse_utility_debug_dump_blocks(); + TEST_ASSERT_EQUAL_INT(i + 1, read_sec_version); + } +} + +#endif + +#ifdef CONFIG_EFUSE_VIRTUAL +TEST_CASE("Test a write/read protection", "[efuse]") +{ + esp_efuse_utility_reset(); + esp_efuse_utility_erase_virt_blocks(); + + esp_efuse_utility_debug_dump_blocks(); + + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_write_protect(EFUSE_BLK0)); + TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_read_protect(EFUSE_BLK0)); + + size_t out_cnt; + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt); + TEST_ASSERT_EQUAL_INT(0, out_cnt); + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK1)); + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_write_protect(EFUSE_BLK1)); + + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK2)); + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART1, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK3)); + esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_USER_DATA, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + esp_efuse_utility_debug_dump_blocks(); + + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY0, &out_cnt); + TEST_ASSERT_EQUAL_INT(0, out_cnt); + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK4)); + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY0, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_read_protect(EFUSE_BLK4)); + + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK5)); + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY1, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK6)); + esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY2, &out_cnt); + TEST_ASSERT_EQUAL_INT(1, out_cnt); + + esp_efuse_utility_debug_dump_blocks(); + esp_efuse_utility_reset(); + esp_efuse_utility_erase_virt_blocks(); +} + +#endif // #ifdef CONFIG_EFUSE_VIRTUAL diff --git a/components/efuse/test/esp32s2beta/test_efuse_coding_scheme.c b/components/efuse/test/esp32s2beta/test_efuse_coding_scheme.c new file mode 100644 index 000000000..e69de29bb diff --git a/components/efuse/test/test_efuse.c b/components/efuse/test/test_efuse.c index 7ea283077..fdcfa88f1 100644 --- a/components/efuse/test/test_efuse.c +++ b/components/efuse/test/test_efuse.c @@ -8,7 +8,7 @@ #include #include "esp_efuse.h" #include "esp_efuse_table.h" -#include "../src/esp_efuse_utility.h" +#include "esp_efuse_utility.h" #include "esp_efuse_test_table.h" #include "esp32/rom/efuse.h" #include "bootloader_random.h" @@ -29,10 +29,12 @@ static void test_read_blob(void) TEST_ASSERT_EQUAL_INT(sizeof(mac) * 8, esp_efuse_get_field_size(ESP_EFUSE_MAC_FACTORY)); ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); +#if CONFIG_IDF_TARGET_ESP32 ESP_LOGI(TAG, "2. Check CRC by MAC"); uint8_t crc; TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &crc, 8)); TEST_ASSERT_EQUAL_HEX8(crc, esp_crc8(mac, sizeof(mac))); +#endif // CONFIG_IDF_TARGET_ESP32 ESP_LOGI(TAG, "3. Test check args"); uint32_t test_var; @@ -85,6 +87,7 @@ TEST_CASE("efuse test read_field_cnt", "[efuse]") #ifdef CONFIG_EFUSE_VIRTUAL static void test_write_blob(void) { + esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(EFUSE_BLK1); esp_efuse_utility_erase_virt_blocks(); esp_efuse_utility_debug_dump_blocks(); @@ -103,12 +106,25 @@ static void test_write_blob(void) TEST_ASSERT_EQUAL_HEX16(test1_len_8&((1 << 7) - 1), val_read1); uint16_t test1_len_8_hi = test1_len_8 & ~((1 << 7) - 1); - TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_TEST1_LEN_8, &test1_len_8_hi, 8)); + if (scheme == EFUSE_CODING_SCHEME_NONE) { + TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_TEST1_LEN_8, &test1_len_8_hi, 8)); + } else { + TEST_ESP_ERR(ESP_ERR_CODING, esp_efuse_write_field_blob(ESP_EFUSE_TEST1_LEN_8, &test1_len_8_hi, 8)); + } + TEST_ESP_ERR(ESP_ERR_EFUSE_REPEATED_PROG, esp_efuse_write_field_blob(ESP_EFUSE_TEST1_LEN_8, &test1_len_8, 8)); val_read1 = 0; TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_TEST1_LEN_8, &val_read1, 16)); - TEST_ASSERT_EQUAL_HEX16(test1_len_8&0x00FF, val_read1); + if (scheme == EFUSE_CODING_SCHEME_NONE) { + TEST_ASSERT_EQUAL_HEX16(test1_len_8&0x00FF, val_read1); + } else { + TEST_ASSERT_EQUAL_HEX16(test1_len_8&0x007F, val_read1); + } + if (scheme != EFUSE_CODING_SCHEME_NONE) { + esp_efuse_utility_erase_virt_blocks(); + ESP_LOGI(TAG, "erase virt blocks"); + } uint16_t test2_len_16 = 0xAA55; uint32_t val_32 = test2_len_16; TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_TEST2_LEN_16, &val_32, 17)); @@ -145,6 +161,7 @@ TEST_CASE("efuse test write_field_blob", "[efuse]") static void test_write_cnt(void) { + esp_efuse_coding_scheme_t scheme = esp_efuse_get_coding_scheme(EFUSE_BLK1); esp_efuse_utility_erase_virt_blocks(); esp_efuse_utility_debug_dump_blocks(); @@ -162,11 +179,23 @@ static void test_write_cnt(void) TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_TEST3_LEN_6, &test3_len_6)); TEST_ASSERT_EQUAL_INT(1, test3_len_6); - TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST3_LEN_6, 1)); + if (scheme == EFUSE_CODING_SCHEME_NONE) { + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST3_LEN_6, 1)); + } else { + esp_efuse_utility_erase_virt_blocks(); + ESP_LOGI(TAG, "erase virt blocks"); + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST3_LEN_6, 2)); + } TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_TEST3_LEN_6, &test3_len_6)); TEST_ASSERT_EQUAL_INT(2, test3_len_6); - TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST3_LEN_6, 3)); + if (scheme == EFUSE_CODING_SCHEME_NONE) { + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST3_LEN_6, 3)); + } else { + esp_efuse_utility_erase_virt_blocks(); + ESP_LOGI(TAG, "erase virt blocks"); + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST3_LEN_6, 5)); + } TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_TEST3_LEN_6, &test3_len_6)); TEST_ASSERT_EQUAL_INT(5, test3_len_6); @@ -178,7 +207,12 @@ static void test_write_cnt(void) esp_efuse_utility_debug_dump_blocks(); for (int i = 0; i < max_bits / 26; ++i) { ESP_LOGD(TAG, "# %d", i); - TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST4_LEN_182, 26)); + if (scheme == EFUSE_CODING_SCHEME_NONE) { + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST4_LEN_182, 26)); + } else { + esp_efuse_utility_erase_virt_blocks(); + TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST4_LEN_182, (i + 1) * 26)); + } TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_TEST4_LEN_182, &test4_len_182)); esp_efuse_utility_debug_dump_blocks(); TEST_ASSERT_EQUAL_INT((i + 1) * 26, test4_len_182); @@ -196,6 +230,11 @@ static void test_write_cnt(void) TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_TEST5_LEN_1, &test5_len_1, 1)); TEST_ASSERT_EQUAL_HEX8(0, test5_len_1); + if (scheme != EFUSE_CODING_SCHEME_NONE) { + esp_efuse_utility_erase_virt_blocks(); + ESP_LOGI(TAG, "erase virt blocks"); + } + test5_len_1 = 1; TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_TEST5_LEN_1, test5_len_1)); @@ -441,7 +480,12 @@ void check_efuse_table_test(int cycle) TEST_CASE("efuse esp_efuse_table_test", "[efuse]") { - check_efuse_table_test(2); + esp_efuse_coding_scheme_t coding_scheme = esp_efuse_get_coding_scheme(EFUSE_BLK2); + if (coding_scheme == EFUSE_CODING_SCHEME_NONE) { + check_efuse_table_test(2); + } else { + ESP_LOGI(TAG, "This test is applicable only to the EFUSE_CODING_SCHEME_NONE. Skip this test."); + } } @@ -452,13 +496,21 @@ TEST_CASE("Test esp_efuse_read_block esp_efuse_write_block functions", "[efuse]" if (coding_scheme == EFUSE_CODING_SCHEME_NONE) { printf("EFUSE_CODING_SCHEME_NONE\n"); count_useful_reg = 8; - } else if (coding_scheme == EFUSE_CODING_SCHEME_3_4) { + } +#if CONFIG_IDF_TARGET_ESP32 + if (coding_scheme == EFUSE_CODING_SCHEME_3_4) { printf("EFUSE_CODING_SCHEME_3_4\n"); count_useful_reg = 6; } else if (coding_scheme == EFUSE_CODING_SCHEME_REPEAT) { printf("EFUSE_CODING_SCHEME_REPEAT\n"); count_useful_reg = 4; } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + if (coding_scheme == EFUSE_CODING_SCHEME_RS) { + printf("EFUSE_CODING_SCHEME_RS\n"); + count_useful_reg = 8; + } +#endif esp_efuse_utility_reset(); esp_efuse_utility_erase_virt_blocks(); @@ -507,13 +559,25 @@ TEST_CASE("Test Bits are not empty. Write operation is forbidden", "[efuse]") printf("EFUSE_CODING_SCHEME_NONE. The test is not applicable.\n"); count_useful_reg = 8; return; - } else if (coding_scheme == EFUSE_CODING_SCHEME_3_4) { + } +#if CONFIG_IDF_TARGET_ESP32 + if (coding_scheme == EFUSE_CODING_SCHEME_3_4) { printf("EFUSE_CODING_SCHEME_3_4\n"); count_useful_reg = 6; } else if (coding_scheme == EFUSE_CODING_SCHEME_REPEAT) { printf("EFUSE_CODING_SCHEME_REPEAT\n"); count_useful_reg = 4; } +#elif CONFIG_IDF_TARGET_ESP32S2BETA + if (coding_scheme == EFUSE_CODING_SCHEME_RS) { + printf("EFUSE_CODING_SCHEME_RS\n"); + if (num_block == EFUSE_BLK1) { + count_useful_reg = 6; + } else { + count_useful_reg = 8; + } + } +#endif TEST_ESP_OK(esp_efuse_read_block(num_block, r_buff, 0, count_useful_reg * 32)); for (int i = 0; i < count_useful_reg * 4; ++i) { if (r_buff[i] != 0) { @@ -544,51 +608,4 @@ TEST_CASE("Test Bits are not empty. Write operation is forbidden", "[efuse]") } } -TEST_CASE("Test a write/read protection", "[efuse]") -{ - esp_efuse_utility_reset(); - esp_efuse_utility_erase_virt_blocks(); - - esp_efuse_utility_debug_dump_blocks(); - - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_write_protect(EFUSE_BLK0)); - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_read_protect(EFUSE_BLK0)); - - size_t out_cnt; - esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt); - TEST_ASSERT_EQUAL_INT(0, out_cnt); - TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK1)); - esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt); - TEST_ASSERT_EQUAL_INT(1, out_cnt); - TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_write_protect(EFUSE_BLK1)); - - TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK2)); - esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK2, &out_cnt); - TEST_ASSERT_EQUAL_INT(1, out_cnt); - - TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK3)); - esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK3, &out_cnt); - TEST_ASSERT_EQUAL_INT(1, out_cnt); - - esp_efuse_utility_debug_dump_blocks(); - - esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK1, &out_cnt); - TEST_ASSERT_EQUAL_INT(0, out_cnt); - TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK1)); - esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK1, &out_cnt); - TEST_ASSERT_EQUAL_INT(1, out_cnt); - TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_read_protect(EFUSE_BLK1)); - - TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK2)); - esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK2, &out_cnt); - TEST_ASSERT_EQUAL_INT(1, out_cnt); - - TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK3)); - esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK3, &out_cnt); - TEST_ASSERT_EQUAL_INT(1, out_cnt); - - esp_efuse_utility_debug_dump_blocks(); - esp_efuse_utility_reset(); - esp_efuse_utility_erase_virt_blocks(); -} #endif // #ifdef CONFIG_EFUSE_VIRTUAL diff --git a/components/efuse/test_efuse_host/efuse_tests.py b/components/efuse/test_efuse_host/efuse_tests.py index b94092451..1e4b9d338 100755 --- a/components/efuse/test_efuse_host/efuse_tests.py +++ b/components/efuse/test_efuse_host/efuse_tests.py @@ -236,7 +236,7 @@ name4, EFUSE_BLK2, 30, name1, EFUSE_BLK5, 0, 5, Use for test name 1 name2, EFUSE_BLK3, 5, 4, Use for test name 2 """ - with self.assertRaisesRegex(efuse_table_gen.InputError, "'efuse_block' should consist from EFUSE_BLK0..EFUSE_BLK3"): + with self.assertRaisesRegex(efuse_table_gen.InputError, "'efuse_block' should be one of EFUSE_BLK0..EFUSE_BLK3"): efuse_table_gen.FuseTable.from_csv(csv) def test_field_size_is_ok(self): diff --git a/tools/ci/config/host-test.yml b/tools/ci/config/host-test.yml index aeeac4541..e730d1360 100644 --- a/tools/ci/config/host-test.yml +++ b/tools/ci/config/host-test.yml @@ -217,7 +217,7 @@ test_esp_err_to_name_on_host: - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh -p 3.4.8 ./gen_esp_err_to_name.py - git diff --exit-code -- ../components/esp_common/src/esp_err_to_name.c || { echo 'Differences found between running under Python 2 and 3.'; exit 1; } -test_esp_efuse_table_on_host: +test_esp32_efuse_table_on_host: extends: .host_test_template artifacts: when: on_failure @@ -227,12 +227,28 @@ test_esp_efuse_table_on_host: script: - cd ${IDF_PATH}/components/efuse/ - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh -p 2.7.15 ./efuse_table_gen.py ${IDF_PATH}/components/efuse/esp32/esp_efuse_table.csv - - git diff --exit-code -- esp32/esp_efuse_table.c || { echo 'Differences found. Please run make efuse_common_table or idf.py efuse_common_table and commit the changes.'; exit 1; } + - git diff --exit-code -- esp32/esp_efuse_table.c || { echo 'Differences found for esp32 target. Please run make efuse_common_table or idf.py efuse_common_table and commit the changes.'; exit 1; } - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh -p 3.4.8 ./efuse_table_gen.py ${IDF_PATH}/components/efuse/esp32/esp_efuse_table.csv - git diff --exit-code -- esp32/esp_efuse_table.c || { echo 'Differences found between running under Python 2 and 3.'; exit 1; } - cd ${IDF_PATH}/components/efuse/test_efuse_host - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh ./efuse_tests.py +test_esp32s2beta_efuse_table_on_host: + extends: .host_test_template + artifacts: + when: on_failure + paths: + - components/efuse/esp32s2beta/esp_efuse_table.c + expire_in: 1 week + script: + - cd ${IDF_PATH}/components/efuse/ + - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh -p 2.7.15 ./efuse_table_gen.py -t "esp32s2beta" ${IDF_PATH}/components/efuse/esp32s2beta/esp_efuse_table.csv + - git diff --exit-code -- esp32s2beta/esp_efuse_table.c || { echo 'Differences found for esp32s2beta target. Please run make efuse_common_table or idf.py efuse_common_table and commit the changes.'; exit 1; } + - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh -p 3.4.8 ./efuse_table_gen.py -t "esp32s2beta" ${IDF_PATH}/components/efuse/esp32s2beta/esp_efuse_table.csv + - git diff --exit-code -- esp32s2beta/esp_efuse_table.c || { echo 'Differences found between running under Python 2 and 3.'; exit 1; } + - cd ${IDF_PATH}/components/efuse/test_efuse_host + - ${IDF_PATH}/tools/ci/multirun_with_pyenv.sh ./efuse_tests.py + test_espcoredump: extends: .host_test_template artifacts: