From 30be5f6eb5926e89a1b72988a1e3a6a1c1d3b517 Mon Sep 17 00:00:00 2001 From: liuhan Date: Fri, 5 Aug 2016 17:40:32 +0800 Subject: [PATCH 01/57] [t6001]: chip Use hardware acceleration of Encryption --- components/mbedtls/include/port/aes_alt.h | 260 +++ components/mbedtls/include/port/bignum_alt.h | 707 ++++++ components/mbedtls/include/port/sha1_alt.h | 93 + components/mbedtls/include/port/sha256_alt.h | 95 + components/mbedtls/include/port/sha512_alt.h | 92 + components/mbedtls/port/aes_alt.c | 306 +++ components/mbedtls/port/bignum_alt.c | 2100 ++++++++++++++++++ components/mbedtls/port/sha1_alt.c | 102 + components/mbedtls/port/sha256_alt.c | 107 + components/mbedtls/port/sha512_alt.c | 103 + 10 files changed, 3965 insertions(+) create mode 100644 components/mbedtls/include/port/aes_alt.h create mode 100644 components/mbedtls/include/port/bignum_alt.h create mode 100644 components/mbedtls/include/port/sha1_alt.h create mode 100644 components/mbedtls/include/port/sha256_alt.h create mode 100644 components/mbedtls/include/port/sha512_alt.h create mode 100644 components/mbedtls/port/aes_alt.c create mode 100644 components/mbedtls/port/bignum_alt.c create mode 100644 components/mbedtls/port/sha1_alt.c create mode 100644 components/mbedtls/port/sha256_alt.c create mode 100644 components/mbedtls/port/sha512_alt.c diff --git a/components/mbedtls/include/port/aes_alt.h b/components/mbedtls/include/port/aes_alt.h new file mode 100644 index 000000000..d56c76ce4 --- /dev/null +++ b/components/mbedtls/include/port/aes_alt.h @@ -0,0 +1,260 @@ +/** + * \file aes_alt.h + * + * \brief AES block cipher + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef AES_ALT_H +#define AES_ALT_H + +#include "c_types.h" +#include "rom/ets_sys.h" +#include "rom/aes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP_AES_C + +/* padlock.c and aesni.c rely on these values! */ +#define AES_ENCRYPT 1 +#define AES_DECRYPT 0 + +#define ERR_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ + +/** + * \brief AES context structure + * + * \note buf is able to hold 32 extra bytes, which can be used: + * - for alignment purposes if VIA padlock is used, and/or + * - to simplify key expansion in the 256-bit case by + * generating an extra round key + */ +typedef struct +{ + int nr; /*!< number of rounds */ + uint32_t *rk; /*!< AES round keys */ + uint32_t buf[68]; /*!< unaligned data */ +}aes_context; + +typedef aes_context AES_CTX; + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void aes_init( AES_CTX *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void aes_free( AES_CTX *ctx ); + +/** + * \brief AES key schedule (encryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); + +/** + * \brief AES key schedule (decryption) + * + * \param ctx AES context to be initialized + * \param key decryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int aes_crypt_ecb( AES_CTX *ctx,int mode,const unsigned char input[16],unsigned char output[16] ); + +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH + */ +int aes_crypt_cbc( AES_CTX *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int aes_crypt_cfb128( AES_CTX *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int aes_crypt_cfb8( AES_CTX *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int aes_crypt_ctr( AES_CTX *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +void aes_encrypt( AES_CTX *ctx, const unsigned char input[16],unsigned char output[16] ); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +void aes_decrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ); + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/components/mbedtls/include/port/bignum_alt.h b/components/mbedtls/include/port/bignum_alt.h new file mode 100644 index 000000000..64d492a98 --- /dev/null +++ b/components/mbedtls/include/port/bignum_alt.h @@ -0,0 +1,707 @@ +/** + * \file bignum_alt.h + * + * \brief Multi-precision integer library + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef BIGNUM_ALT_H +#define BIGNUM_ALT_H + +#include "c_types.h" +#include "rom/ets_sys.h" +#include "rom/bigint.h" + +#define ESP_BIGNUM_ALT +#define MPI_DEBUG_ALT +#if defined(ESP_BIGNUM_ALT) + +#define ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error occurred while reading from or writing to a file. */ +#define ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input parameters to function. */ +#define ERR_MPI_INVALID_CHARACTER -0x0006 /**< There is an invalid character in the digit string. */ +#define ERR_MPI_BUFFER_TOO_SMALL -0x0008 /**< The buffer is too small to write to. */ +#define ERR_MPI_NEGATIVE_VALUE -0x000A /**< The input arguments are negative or result in illegal output. */ +#define ERR_MPI_DIVISION_BY_ZERO -0x000C /**< The input argument for division is zero, which is not allowed. */ +#define ERR_MPI_NOT_ACCEPTABLE -0x000E /**< The input arguments are not acceptable. */ +#define ERR_MPI_ALLOC_FAILED -0x0010 /**< Memory allocation failed. */ + +#define MPI_CHK(f) do { if( ( ret = f ) != 0 ) goto cleanup; } while( 0 ) +#if defined(MPI_DEBUG_ALT) +#define mpi_printf ets_printf +#else +#define mpi_printf +#endif +/* + * Maximum size MPIs are allowed to grow to in number of limbs. + */ +#define MPI_MAX_LIMBS 10000 + +#if !defined(MPI_WINDOW_SIZE) +/* + * Maximum window size used for modular exponentiation. Default: 6 + * Minimum value: 1. Maximum value: 6. + * + * Result is an array of ( 2 << MPI_WINDOW_SIZE ) MPIs used + * for the sliding window calculation. (So 64 by default) + * + * Reduction in size, reduces speed. + */ +#define MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ +#endif /* !MPI_WINDOW_SIZE */ + +#if !defined(MPI_MAX_SIZE) +/* + * Maximum size of MPIs allowed in bits and bytes for user-MPIs. + * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits ) + * + * Note: Calculations can results temporarily in larger MPIs. So the number + * of limbs required (MPI_MAX_LIMBS) is higher. + */ +#define MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ +#endif /* !MPI_MAX_SIZE */ + +#define MPI_MAX_BITS ( 8 * MPI_MAX_SIZE ) /**< Maximum number of bits for usable MPIs. */ + +/* + * When reading from files with mpi_read_file() and writing to files with + * mpi_write_file() the buffer should have space + * for a (short) label, the MPI (in the provided radix), the newline + * characters and the '\0'. + * + * By default we assume at least a 10 char label, a minimum radix of 10 + * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars). + * Autosized at compile time for at least a 10 char label, a minimum radix + * of 10 (decimal) for a number of MPI_MAX_BITS size. + * + * This used to be statically sized to 1250 for a maximum of 4096 bit + * numbers (1234 decimal chars). + * + * Calculate using the formula: + * MPI_RW_BUFFER_SIZE = ceil(MPI_MAX_BITS / ln(10) * ln(2)) + + * LabelSize + 6 + */ +#define MPI_MAX_BITS_SCALE100 ( 100 * MPI_MAX_BITS ) +#define LN_2_DIV_LN_10_SCALE100 332 +#define MPI_RW_BUFFER_SIZE ( ((MPI_MAX_BITS_SCALE100 + LN_2_DIV_LN_10_SCALE100 - 1) / LN_2_DIV_LN_10_SCALE100) + 10 + 6 ) + +/* + * Define the base integer type, architecture-wise. + * + * 32-bit integers can be forced on 64-bit arches (eg. for testing purposes) + * by defining HAVE_INT32 and undefining HAVE_ASM + */ +#if ( ! defined(HAVE_INT32) && \ + defined(_MSC_VER) && defined(_M_AMD64) ) + #define HAVE_INT64 + typedef int64_t mpi_sint; + typedef uint64_t mpi_uint; +#else + #if ( ! defined(HAVE_INT32) && \ + defined(__GNUC__) && ( \ + defined(__amd64__) || defined(__x86_64__) || \ + defined(__ppc64__) || defined(__powerpc64__) || \ + defined(__ia64__) || defined(__alpha__) || \ + (defined(__sparc__) && defined(__arch64__)) || \ + defined(__s390x__) || defined(__mips64) ) ) + #define HAVE_INT64 + typedef int64_t mpi_sint; + typedef uint64_t mpi_uint; + /* t_udbl defined as 128-bit unsigned int */ + typedef unsigned int t_udbl __attribute__((mode(TI))); + #define HAVE_UDBL + #else + #define HAVE_INT32 + typedef int32_t mpi_sint; + typedef uint32_t mpi_uint; + typedef uint64_t t_udbl; + #define HAVE_UDBL + #endif /* !HAVE_INT32 && __GNUC__ && 64-bit platform */ +#endif /* !HAVE_INT32 && _MSC_VER && _M_AMD64 */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief MPI structure + */ +typedef struct +{ + int s; /*!< integer sign */ + size_t n; /*!< total # of limbs */ + mpi_uint *p; /*!< pointer to limbs */ +} +mpi; + +/** + * \brief Initialize one MPI (make internal references valid) + * This just makes it ready to be set or freed, + * but does not define a value for the MPI. + * + * \param X One MPI to initialize. + */ +void mpi_init( mpi *X ); + +/** + * \brief Unallocate one MPI + * + * \param X One MPI to unallocate. + */ +void mpi_free( mpi *X ); + +/** + * \brief Enlarge to the specified number of limbs + * + * \param X MPI to grow + * \param nblimbs The target number of limbs + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_grow( mpi *X, size_t nblimbs ); + +/** + * \brief Resize down, keeping at least the specified number of limbs + * + * \param X MPI to shrink + * \param nblimbs The minimum number of limbs to keep + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_shrink( mpi *X, size_t nblimbs ); + +/** + * \brief Copy the contents of Y into X + * + * \param X Destination MPI + * \param Y Source MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_copy( mpi *X, const mpi *Y ); + +/** + * \brief Swap the contents of X and Y + * + * \param X First MPI value + * \param Y Second MPI value + */ +void mpi_swap( mpi *X, mpi *Y ); + +/** + * \brief Safe conditional assignement X = Y if assign is 1 + * + * \param X MPI to conditionally assign to + * \param Y Value to be assigned + * \param assign 1: perform the assignment, 0: keep X's original value + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * + * \note This function is equivalent to + * if( assign ) mpi_copy( X, Y ); + * except that it avoids leaking any information about whether + * the assignment was done or not (the above code may leak + * information through branch prediction and/or memory access + * patterns analysis). + */ +int mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ); + +/** + * \brief Safe conditional swap X <-> Y if swap is 1 + * + * \param X First mpi value + * \param Y Second mpi value + * \param assign 1: perform the swap, 0: keep X and Y's original values + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * + * \note This function is equivalent to + * if( assign ) mpi_swap( X, Y ); + * except that it avoids leaking any information about whether + * the assignment was done or not (the above code may leak + * information through branch prediction and/or memory access + * patterns analysis). + */ +int mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char assign ); + +/** + * \brief Set value from integer + * + * \param X MPI to set + * \param z Value to use + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_lset( mpi *X, mpi_sint z ); + +/** + * \brief Get a specific bit from X + * + * \param X MPI to use + * \param pos Zero-based index of the bit in X + * + * \return Either a 0 or a 1 + */ +int mpi_get_bit( const mpi *X, size_t pos ); + +/** + * \brief Set a bit of X to a specific value of 0 or 1 + * + * \note Will grow X if necessary to set a bit to 1 in a not yet + * existing limb. Will not grow if bit should be set to 0 + * + * \param X MPI to use + * \param pos Zero-based index of the bit in X + * \param val The value to set the bit to (0 or 1) + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_BAD_INPUT_DATA if val is not 0 or 1 + */ +int mpi_set_bit( mpi *X, size_t pos, unsigned char val ); + +/** + * \brief Return the number of zero-bits before the least significant + * '1' bit + * + * Note: Thus also the zero-based index of the least significant '1' bit + * + * \param X MPI to use + */ +size_t mpi_lsb( const mpi *X ); + +/** + * \brief Return the number of bits up to and including the most + * significant '1' bit' + * + * Note: Thus also the one-based index of the most significant '1' bit + * + * \param X MPI to use + */ +size_t mpi_bitlen( const mpi *X ); + +/** + * \brief Return the total size in bytes + * + * \param X MPI to use + */ +size_t mpi_size( const mpi *X ); + +/** + * \brief Import from an ASCII string + * + * \param X Destination MPI + * \param radix Input numeric base + * \param s Null-terminated string buffer + * + * \return 0 if successful, or a ERR_MPI_XXX error code + */ +int mpi_read_string( mpi *X, int radix, const char *s ); + +/** + * \brief Export into an ASCII string + * + * \param X Source MPI + * \param radix Output numeric base + * \param buf Buffer to write the string to + * \param buflen Length of buf + * \param olen Length of the string written, including final NUL byte + * + * \return 0 if successful, or a ERR_MPI_XXX error code. + * *olen is always updated to reflect the amount + * of data that has (or would have) been written. + * + * \note Call this function with buflen = 0 to obtain the + * minimum required buffer size in *olen. + */ +int mpi_write_string( const mpi *X, int radix, + char *buf, size_t buflen, size_t *olen ); + +#if defined(FS_IO) +/** + * \brief Read X from an opened file + * + * \param X Destination MPI + * \param radix Input numeric base + * \param fin Input file handle + * + * \return 0 if successful, ERR_MPI_BUFFER_TOO_SMALL if + * the file read buffer is too small or a + * ERR_MPI_XXX error code + */ +int mpi_read_file( mpi *X, int radix, FILE *fin ); + +/** + * \brief Write X into an opened file, or stdout if fout is NULL + * + * \param p Prefix, can be NULL + * \param X Source MPI + * \param radix Output numeric base + * \param fout Output file handle (can be NULL) + * + * \return 0 if successful, or a ERR_MPI_XXX error code + * + * \note Set fout == NULL to print X on the console. + */ +int mpi_write_file( const char *p, const mpi *X, int radix, FILE *fout ); +#endif /* FS_IO */ + +/** + * \brief Import X from unsigned binary data, big endian + * + * \param X Destination MPI + * \param buf Input buffer + * \param buflen Input buffer size + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ); + +/** + * \brief Export X into unsigned binary data, big endian. + * Always fills the whole buffer, which will start with zeros + * if the number is smaller. + * + * \param X Source MPI + * \param buf Output buffer + * \param buflen Output buffer size + * + * \return 0 if successful, + * ERR_MPI_BUFFER_TOO_SMALL if buf isn't large enough + */ +int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ); + +/** + * \brief Left-shift: X <<= count + * + * \param X MPI to shift + * \param count Amount to shift + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_shift_l( mpi *X, size_t count ); + +/** + * \brief Right-shift: X >>= count + * + * \param X MPI to shift + * \param count Amount to shift + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_shift_r( mpi *X, size_t count ); + +/** + * \brief Compare unsigned values + * + * \param X Left-hand MPI + * \param Y Right-hand MPI + * + * \return 1 if |X| is greater than |Y|, + * -1 if |X| is lesser than |Y| or + * 0 if |X| is equal to |Y| + */ +int mpi_cmp_abs( const mpi *X, const mpi *Y ); + +/** + * \brief Compare signed values + * + * \param X Left-hand MPI + * \param Y Right-hand MPI + * + * \return 1 if X is greater than Y, + * -1 if X is lesser than Y or + * 0 if X is equal to Y + */ +int mpi_cmp_mpi( const mpi *X, const mpi *Y ); + +/** + * \brief Compare signed values + * + * \param X Left-hand MPI + * \param z The integer value to compare to + * + * \return 1 if X is greater than z, + * -1 if X is lesser than z or + * 0 if X is equal to z + */ +int mpi_cmp_int( const mpi *X, mpi_sint z ); + +/** + * \brief Unsigned addition: X = |A| + |B| + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ); + +/** + * \brief Unsigned subtraction: X = |A| - |B| + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_NEGATIVE_VALUE if B is greater than A + */ +int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ); + +/** + * \brief Signed addition: X = A + B + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ); + +/** + * \brief Signed subtraction: X = A - B + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ); + +/** + * \brief Signed addition: X = A + b + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param b The integer value to add + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_add_int( mpi *X, const mpi *A, mpi_sint b ); + +/** + * \brief Signed subtraction: X = A - b + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param b The integer value to subtract + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_sub_int( mpi *X, const mpi *A, mpi_sint b ); + +/** + * \brief Baseline multiplication: X = A * B + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ); + +/** + * \brief Baseline multiplication: X = A * b + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param b The unsigned integer value to multiply with + * + * \note b is unsigned + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_mul_int( mpi *X, const mpi *A, mpi_uint b ); + +/** + * \brief Division by mpi: A = Q * B + R + * + * \param Q Destination MPI for the quotient + * \param R Destination MPI for the rest value + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_DIVISION_BY_ZERO if B == 0 + * + * \note Either Q or R can be NULL. + */ +int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ); + +/** + * \brief Division by int: A = Q * b + R + * + * \param Q Destination MPI for the quotient + * \param R Destination MPI for the rest value + * \param A Left-hand MPI + * \param b Integer to divide by + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_DIVISION_BY_ZERO if b == 0 + * + * \note Either Q or R can be NULL. + */ +int mpi_div_int( mpi *Q, mpi *R, const mpi *A, mpi_sint b ); + +/** + * \brief Modulo: R = A mod B + * + * \param R Destination MPI for the rest value + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_DIVISION_BY_ZERO if B == 0, + * ERR_MPI_NEGATIVE_VALUE if B < 0 + */ +int mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ); + +/** + * \brief Modulo: r = A mod b + * + * \param r Destination mpi_uint + * \param A Left-hand MPI + * \param b Integer to divide by + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_DIVISION_BY_ZERO if b == 0, + * ERR_MPI_NEGATIVE_VALUE if b < 0 + */ +int mpi_mod_int( mpi_uint *r, const mpi *A, mpi_sint b ); + +/** + * \brief Sliding-window exponentiation: X = A^E mod N + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param E Exponent MPI + * \param N Modular MPI + * \param _RR Speed-up MPI used for recalculations + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_BAD_INPUT_DATA if N is negative or even or + * if E is negative + * + * \note _RR is used to avoid re-computing R*R mod N across + * multiple calls, which speeds up things a bit. It can + * be set to NULL if the extra performance is unneeded. + */ +int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ); + +/** + * \brief Fill an MPI X with size bytes of random + * + * \param X Destination MPI + * \param size Size in bytes + * \param f_rng RNG function + * \param p_rng RNG parameter + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_fill_random( mpi *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief Greatest common divisor: G = gcd(A, B) + * + * \param G Destination MPI + * \param A Left-hand MPI + * \param B Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed + */ +int mpi_gcd( mpi *G, const mpi *A, const mpi *B ); + +/** + * \brief Modular inverse: X = A^-1 mod N + * + * \param X Destination MPI + * \param A Left-hand MPI + * \param N Right-hand MPI + * + * \return 0 if successful, + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_BAD_INPUT_DATA if N is negative or nil + ERR_MPI_NOT_ACCEPTABLE if A has no inverse mod N + */ +int mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ); + +/** + * \brief Miller-Rabin primality test + * + * \param X MPI to check + * \param f_rng RNG function + * \param p_rng RNG parameter + * + * \return 0 if successful (probably prime), + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_NOT_ACCEPTABLE if X is not prime + */ +int mpi_is_prime( const mpi *X, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); + +/** + * \brief Prime number generation + * + * \param X Destination MPI + * \param nbits Required size of X in bits + * ( 3 <= nbits <= MPI_MAX_BITS ) + * \param dh_flag If 1, then (X-1)/2 will be prime too + * \param f_rng RNG function + * \param p_rng RNG parameter + * + * \return 0 if successful (probably prime), + * ERR_MPI_ALLOC_FAILED if memory allocation failed, + * ERR_MPI_BAD_INPUT_DATA if nbits is < 3 + */ +int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ); +#endif + +#endif + diff --git a/components/mbedtls/include/port/sha1_alt.h b/components/mbedtls/include/port/sha1_alt.h new file mode 100644 index 000000000..918798627 --- /dev/null +++ b/components/mbedtls/include/port/sha1_alt.h @@ -0,0 +1,93 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ +#ifndef _SHA1_H_ +#define _SHA1_H_ + +#include "c_types.h" +#include "rom/ets_sys.h" +#include "rom/sha.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP_SHA1_C + +#define SHA1 0 + +/** + * \brief SHA-1 context structure + */ +typedef struct{ + SHA_CTX context; + int context_type; +} sha1_context; + +typedef sha1_context SHA1_CTX; + +/** + * \brief Initialize SHA-1 context + * + * \param ctx SHA-1 context to be initialized + */ +void sha1_init( SHA1_CTX *ctx ); + +/** + * \brief Clear SHA-1 context + * + * \param ctx SHA-1 context to be cleared + */ +void sha1_free( SHA1_CTX *ctx ); + +/** + * \brief Clone (the state of) a SHA-1 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ); + +void sha1_process(SHA1_CTX *ctx, const unsigned char data[64]); + +/** + * \brief SHA-1 context setup + * + * \param ctx context to be initialized + */ +void sha1_starts( SHA1_CTX *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ); + +/** + * \brief Output = SHA-1( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + */ +void sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/components/mbedtls/include/port/sha256_alt.h b/components/mbedtls/include/port/sha256_alt.h new file mode 100644 index 000000000..bc661d393 --- /dev/null +++ b/components/mbedtls/include/port/sha256_alt.h @@ -0,0 +1,95 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ + +#ifndef _SHA256_H_ +#define _SHA256_H_ + +#include "c_types.h" +#include "rom/ets_sys.h" +#include "rom/sha.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP_SHA256_C + +#define SHA256 SHA2_256 +#define SHA224 4 + +/** + * \brief SHA-256 context structure + */ +typedef struct{ + SHA_CTX context; + int context_type; +}sha256_context; + +typedef sha256_context SHA256_CTX; + +/** + * \brief Initialize SHA-256 context + * + * \param ctx SHA-256 context to be initialized + */ +void sha256_init( SHA256_CTX *ctx ); + +/** + * \brief Clear SHA-256 context + * + * \param ctx SHA-256 context to be cleared + */ +void sha256_free( SHA256_CTX *ctx ); +void sha256_process(SHA256_CTX *ctx, const unsigned char data[64]); + +/** + * \brief Clone (the state of) a SHA-256 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ); + +/** + * \brief SHA-256 context setup + * + * \param ctx context to be initialized + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void sha256_starts( SHA256_CTX *ctx, int is224 ); + +/** + * \brief SHA-256 process buffer + * + * \param ctx SHA-256 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-256 final digest + * + * \param ctx SHA-256 context + * \param output SHA-224/256 checksum result + */ +void sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ); + +/** + * \brief Output = SHA-256( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-224/256 checksum result + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ); + +#ifdef __cplusplus +} +#endif + +#endif /* sha256.h */ diff --git a/components/mbedtls/include/port/sha512_alt.h b/components/mbedtls/include/port/sha512_alt.h new file mode 100644 index 000000000..a3e1c50c6 --- /dev/null +++ b/components/mbedtls/include/port/sha512_alt.h @@ -0,0 +1,92 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ + +#ifndef _SHA512_H_ +#define _SHA512_H_ + +#include "c_types.h" +#include "rom/ets_sys.h" +#include "rom/sha.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ESP_SHA512_C + +/** + * \brief SHA-512 context structure + */ +typedef struct{ + SHA_CTX context; + int context_type; +}sha512_context; + +typedef sha512_context SHA512_CTX; + +/** + * \brief Initialize SHA-512 context + * + * \param ctx SHA-512 context to be initialized + */ +void sha512_init( SHA512_CTX *ctx ); + +/** + * \brief Clear SHA-512 context + * + * \param ctx SHA-512 context to be cleared + */ +void sha512_free( SHA512_CTX *ctx ); + +/** + * \brief Clone (the state of) a SHA-512 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ); + +/** + * \brief SHA-512 context setup + * + * \param ctx context to be initialized + * \param is384 0 = use SHA512, 1 = use SHA384 + */ +void sha512_starts( SHA512_CTX *ctx, int is384 ); + +/** + * \brief SHA-512 process buffer + * + * \param ctx SHA-512 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-512 final digest + * + * \param ctx SHA-512 context + * \param output SHA-384/512 checksum result + */ +void sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ); + +/** + * \brief Output = SHA-512( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-384/512 checksum result + * \param is384 0 = use SHA512, 1 = use SHA384 + */ +void sha512_output( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ); + + +#ifdef __cplusplus +} +#endif + +#endif /* sha512.h */ diff --git a/components/mbedtls/port/aes_alt.c b/components/mbedtls/port/aes_alt.c new file mode 100644 index 000000000..26699d82f --- /dev/null +++ b/components/mbedtls/port/aes_alt.c @@ -0,0 +1,306 @@ + +/* + * FIPS-197 compliant AES implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include "port/aes_alt.h" + +#if defined(ESP_AES_C) + +#include + +/* Implementation that should never be optimized out by the compiler */ +static void aes_zeroize( void *v, size_t n ) { + volatile unsigned char *p = v; while( n-- ) *p++ = 0; +} + +void aes_init( AES_CTX *ctx ) +{ + memset( ctx, 0, sizeof( AES_CTX ) ); + ets_aes_enable(); +} + +void aes_free( AES_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + aes_zeroize( ctx, sizeof( AES_CTX ) ); + ets_aes_disable(); +} + +/* + * AES key schedule (encryption) + */ +int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, + unsigned int keybits ) +{ + enum AES_BITS keybit; + switch (keybits){ + case 128: + keybit = AES128; + break; + case 192: + keybit = AES192; + break; + case 256: + keybit = AES256; + break; + default : return( ERR_AES_INVALID_KEY_LENGTH ); + } + ets_aes_setkey_enc(key, keybit); + return 0; +} + +/* + * AES key schedule (decryption) + */ +int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, + unsigned int keybits ) +{ + enum AES_BITS keybit; + switch (keybits){ + case 128: + keybit = AES128; + break; + case 192: + keybit = AES192; + break; + case 256: + keybit = AES256; + break; + default : return( ERR_AES_INVALID_KEY_LENGTH ); + } + ets_aes_setkey_dec(key, keybit); + return 0; + +} + +/* + * AES-ECB block encryption + */ + +void aes_encrypt( AES_CTX *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + ets_aes_crypt(input, output); + return ; +} + + +/* + * AES-ECB block decryption + */ + +void aes_decrypt( AES_CTX *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + ets_aes_crypt(input, output); + return ; +} + + +/* + * AES-ECB block encryption/decryption + */ +int aes_crypt_ecb( AES_CTX *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + if( mode == AES_ENCRYPT ) + aes_encrypt( ctx, input, output ); + else + aes_decrypt( ctx, input, output ); + return 0; +} + + +/* + * AES-CBC buffer encryption/decryption + */ +int aes_crypt_cbc( AES_CTX *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int i; + unsigned char temp[16]; + + if( length % 16 ) + return( ERR_AES_INVALID_INPUT_LENGTH ); + + if( mode == AES_DECRYPT ) + { + while( length > 0 ) + { + memcpy( temp, input, 16 ); + aes_crypt_ecb( ctx, mode, input, output ); + + for( i = 0; i < 16; i++ ) + output[i] = (unsigned char)( output[i] ^ iv[i] ); + + memcpy( iv, temp, 16 ); + + input += 16; + output += 16; + length -= 16; + } + } + else + { + while( length > 0 ) + { + for( i = 0; i < 16; i++ ) + output[i] = (unsigned char)( input[i] ^ iv[i] ); + + aes_crypt_ecb( ctx, mode, output, output ); + memcpy( iv, output, 16 ); + + input += 16; + output += 16; + length -= 16; + } + } + return 0; +} + +/* + * AES-CFB128 buffer encryption/decryption + */ +int aes_crypt_cfb128( AES_CTX *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int c; + size_t n = *iv_off; + + if( mode == AES_DECRYPT ) + { + while( length-- ) + { + if( n == 0 ) + aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + + n = ( n + 1 ) & 0x0F; + } + } + else + { + while( length-- ) + { + if( n == 0 ) + aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + + n = ( n + 1 ) & 0x0F; + } + } + + *iv_off = n; + + return 0; +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int aes_crypt_cfb8( AES_CTX *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + + while( length-- ) + { + memcpy( ov, iv, 16 ); + aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + + if( mode == AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return 0; +} + +/* + * AES-CTR buffer encryption/decryption + */ +int aes_crypt_ctr( AES_CTX *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + int c, i; + size_t n = *nc_off; + + while( length-- ) + { + if( n == 0 ) { + aes_crypt_ecb( ctx, AES_ENCRYPT, nonce_counter, stream_block ); + + for( i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; + } + c = *input++; + *output++ = (unsigned char)( c ^ stream_block[n] ); + + n = ( n + 1 ) & 0x0F; + } + + *nc_off = n; + return 0; +} + +#endif /* AES_ALT_C */ + diff --git a/components/mbedtls/port/bignum_alt.c b/components/mbedtls/port/bignum_alt.c new file mode 100644 index 000000000..88901671c --- /dev/null +++ b/components/mbedtls/port/bignum_alt.c @@ -0,0 +1,2100 @@ +/* + * Multi-precision integer library + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * The following sources were referenced in the design of this Multi-precision + * Integer library: + * + * [1] Handbook of Applied Cryptography - 1997 + * Menezes, van Oorschot and Vanstone + * + * [2] Multi-Precision Math + * Tom St Denis + * https://github.com/libtom/libtommath/blob/develop/tommath.pdf + * + * [3] GNU Multi-Precision Arithmetic Library + * https://gmplib.org/manual/index.html + * + */ +#include "port/bignum_alt.h" + +#if defined(ESP_BIGNUM_ALT) +#include +#include + +/* Implementation that should never be optimized out by the compiler */ +static void mpi_zeroize( void *v, size_t n ) { + volatile unsigned char *p = v; while( n-- ) *p++ = 0; +} + +#define ciL (sizeof(mpi_uint)) /* chars in limb */ +#define biL (ciL << 3) /* bits in limb */ +#define biH (ciL << 2) /* half limb size */ + +#define MPI_SIZE_T_MAX ( (size_t) -1 ) /* SIZE_T_MAX is not standard */ + +/* + * Convert between bits/chars and number of limbs + * Divide first in order to avoid potential overflows + */ +#define BITS_TO_LIMBS(i) ( (i) / biL + ( (i) % biL != 0 ) ) +#define CHARS_TO_LIMBS(i) ( (i) / ciL + ( (i) % ciL != 0 ) ) + +/* + * Initialize one MPI + */ +void mpi_init( mpi *X ) +{ + if( X == NULL ) + return; + + X->s = 1; + X->n = 0; + X->p = NULL; + ets_bigint_enable(); +} + +/* + * Unallocate one MPI + */ +void mpi_free( mpi *X ) +{ + if( X == NULL ) + return; + + if( X->p != NULL ) + { + mpi_zeroize( X->p, X->n * ciL ); + free( X->p ); + } + + X->s = 1; + X->n = 0; + X->p = NULL; + ets_bigint_disable(); +} + +/* + * Enlarge to the specified number of limbs + */ +int mpi_grow( mpi *X, size_t nblimbs ) +{ + mpi_uint *p; + + if( nblimbs > MPI_MAX_LIMBS ) + return( ERR_MPI_ALLOC_FAILED ); + + if( X->n < nblimbs ) + { + if( ( p = calloc( nblimbs, ciL ) ) == NULL ) + return( ERR_MPI_ALLOC_FAILED ); + + if( X->p != NULL ) + { + memcpy( p, X->p, X->n * ciL ); + mpi_zeroize( X->p, X->n * ciL ); + free( X->p ); + } + + X->n = nblimbs; + X->p = p; + } + + return( 0 ); +} + +/* + * Resize down as much as possible, + * while keeping at least the specified number of limbs + */ +int mpi_shrink( mpi *X, size_t nblimbs ) +{ + mpi_uint *p; + size_t i; + + /* Actually resize up in this case */ + if( X->n <= nblimbs ) + return( mpi_grow( X, nblimbs ) ); + + for( i = X->n - 1; i > 0; i-- ) + if( X->p[i] != 0 ) + break; + i++; + + if( i < nblimbs ) + i = nblimbs; + + if( ( p = calloc( i, ciL ) ) == NULL ) + return( ERR_MPI_ALLOC_FAILED ); + + if( X->p != NULL ) + { + memcpy( p, X->p, i * ciL ); + mpi_zeroize( X->p, X->n * ciL ); + free( X->p ); + } + + X->n = i; + X->p = p; + + return( 0 ); +} + +/* + * Copy the contents of Y into X + */ +int mpi_copy( mpi *X, const mpi *Y ) +{ + int ret; + size_t i; + + if( X == Y ) + return( 0 ); + + if( Y->p == NULL ) + { + mpi_free( X ); + return( 0 ); + } + + for( i = Y->n - 1; i > 0; i-- ) + if( Y->p[i] != 0 ) + break; + i++; + + X->s = Y->s; + + MPI_CHK( mpi_grow( X, i ) ); + + memset( X->p, 0, X->n * ciL ); + memcpy( X->p, Y->p, i * ciL ); + +cleanup: + + return( ret ); +} + +/* + * Swap the contents of X and Y + */ +void mpi_swap( mpi *X, mpi *Y ) +{ + mpi T; + + memcpy( &T, X, sizeof( mpi ) ); + memcpy( X, Y, sizeof( mpi ) ); + memcpy( Y, &T, sizeof( mpi ) ); +} + +/* + * Conditionally assign X = Y, without leaking information + * about whether the assignment was made or not. + * (Leaking information about the respective sizes of X and Y is ok however.) + */ +int mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ) +{ + int ret = 0; + size_t i; + + /* make sure assign is 0 or 1 in a time-constant manner */ + assign = (assign | (unsigned char)-assign) >> 7; + + MPI_CHK( mpi_grow( X, Y->n ) ); + + X->s = X->s * ( 1 - assign ) + Y->s * assign; + + for( i = 0; i < Y->n; i++ ) + X->p[i] = X->p[i] * ( 1 - assign ) + Y->p[i] * assign; + + for( ; i < X->n; i++ ) + X->p[i] *= ( 1 - assign ); + +cleanup: + return( ret ); +} + +/* + * Conditionally swap X and Y, without leaking information + * about whether the swap was made or not. + * Here it is not ok to simply swap the pointers, which whould lead to + * different memory access patterns when X and Y are used afterwards. + */ +int mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char swap ) +{ + int ret, s; + size_t i; + mpi_uint tmp; + + if( X == Y ) + return( 0 ); + + /* make sure swap is 0 or 1 in a time-constant manner */ + swap = (swap | (unsigned char)-swap) >> 7; + + MPI_CHK( mpi_grow( X, Y->n ) ); + MPI_CHK( mpi_grow( Y, X->n ) ); + + s = X->s; + X->s = X->s * ( 1 - swap ) + Y->s * swap; + Y->s = Y->s * ( 1 - swap ) + s * swap; + + + for( i = 0; i < X->n; i++ ) + { + tmp = X->p[i]; + X->p[i] = X->p[i] * ( 1 - swap ) + Y->p[i] * swap; + Y->p[i] = Y->p[i] * ( 1 - swap ) + tmp * swap; + } + +cleanup: + return( ret ); +} + +/* + * Set value from integer + */ +int mpi_lset( mpi *X, mpi_sint z ) +{ + int ret; + + MPI_CHK( mpi_grow( X, 1 ) ); + memset( X->p, 0, X->n * ciL ); + + X->p[0] = ( z < 0 ) ? -z : z; + X->s = ( z < 0 ) ? -1 : 1; + +cleanup: + + return( ret ); +} + +/* + * Get a specific bit + */ +int mpi_get_bit( const mpi *X, size_t pos ) +{ + if( X->n * biL <= pos ) + return( 0 ); + + return( ( X->p[pos / biL] >> ( pos % biL ) ) & 0x01 ); +} + +/* + * Set a bit to a specific value of 0 or 1 + */ +int mpi_set_bit( mpi *X, size_t pos, unsigned char val ) +{ + int ret = 0; + size_t off = pos / biL; + size_t idx = pos % biL; + + if( val != 0 && val != 1 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + if( X->n * biL <= pos ) + { + if( val == 0 ) + return( 0 ); + + MPI_CHK( mpi_grow( X, off + 1 ) ); + } + + X->p[off] &= ~( (mpi_uint) 0x01 << idx ); + X->p[off] |= (mpi_uint) val << idx; + +cleanup: + + return( ret ); +} + +/* + * Return the number of less significant zero-bits + */ +size_t mpi_lsb( const mpi *X ) +{ + size_t i, j, count = 0; + + for( i = 0; i < X->n; i++ ) + for( j = 0; j < biL; j++, count++ ) + if( ( ( X->p[i] >> j ) & 1 ) != 0 ) + return( count ); + + return( 0 ); +} + +/* + * Count leading zero bits in a given integer + */ +static size_t clz( const mpi_uint x ) +{ + size_t j; + mpi_uint mask = (mpi_uint) 1 << (biL - 1); + + for( j = 0; j < biL; j++ ) + { + if( x & mask ) break; + + mask >>= 1; + } + + return j; +} + +/* + * Return the number of bits + */ +size_t mpi_bitlen( const mpi *X ) +{ + size_t i, j; + + if( X->n == 0 ) + return( 0 ); + + for( i = X->n - 1; i > 0; i-- ) + if( X->p[i] != 0 ) + break; + + j = biL - clz( X->p[i] ); + + return( ( i * biL ) + j ); +} + +/* + * Return the total size in bytes + */ +size_t mpi_size( const mpi *X ) +{ + return( ( mpi_bitlen( X ) + 7 ) >> 3 ); +} + +/* + * Convert an ASCII character to digit value + */ +static int mpi_get_digit( mpi_uint *d, int radix, char c ) +{ + *d = 255; + + if( c >= 0x30 && c <= 0x39 ) *d = c - 0x30; + if( c >= 0x41 && c <= 0x46 ) *d = c - 0x37; + if( c >= 0x61 && c <= 0x66 ) *d = c - 0x57; + + if( *d >= (mpi_uint) radix ) + return( ERR_MPI_INVALID_CHARACTER ); + + return( 0 ); +} + +/* + * Import from an ASCII string + */ +int mpi_read_string( mpi *X, int radix, const char *s ) +{ + int ret; + size_t i, j, slen, n; + mpi_uint d; + mpi T; + + if( radix < 2 || radix > 16 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + mpi_init( &T ); + + slen = strlen( s ); + + if( radix == 16 ) + { + if( slen > MPI_SIZE_T_MAX >> 2 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + n = BITS_TO_LIMBS( slen << 2 ); + + MPI_CHK( mpi_grow( X, n ) ); + MPI_CHK( mpi_lset( X, 0 ) ); + + for( i = slen, j = 0; i > 0; i--, j++ ) + { + if( i == 1 && s[i - 1] == '-' ) + { + X->s = -1; + break; + } + + MPI_CHK( mpi_get_digit( &d, radix, s[i - 1] ) ); + X->p[j / ( 2 * ciL )] |= d << ( ( j % ( 2 * ciL ) ) << 2 ); + } + } + else + { + MPI_CHK( mpi_lset( X, 0 ) ); + + for( i = 0; i < slen; i++ ) + { + if( i == 0 && s[i] == '-' ) + { + X->s = -1; + continue; + } + + MPI_CHK( mpi_get_digit( &d, radix, s[i] ) ); + MPI_CHK( mpi_mul_int( &T, X, radix ) ); + + if( X->s == 1 ) + { + MPI_CHK( mpi_add_int( X, &T, d ) ); + } + else + { + MPI_CHK( mpi_sub_int( X, &T, d ) ); + } + } + } + +cleanup: + + mpi_free( &T ); + + return( ret ); +} + +/* + * Helper to write the digits high-order first + */ +static int mpi_write_hlp( mpi *X, int radix, char **p ) +{ + int ret; + mpi_uint r; + + if( radix < 2 || radix > 16 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + MPI_CHK( mpi_mod_int( &r, X, radix ) ); + MPI_CHK( mpi_div_int( X, NULL, X, radix ) ); + + if( mpi_cmp_int( X, 0 ) != 0 ) + MPI_CHK( mpi_write_hlp( X, radix, p ) ); + + if( r < 10 ) + *(*p)++ = (char)( r + 0x30 ); + else + *(*p)++ = (char)( r + 0x37 ); + +cleanup: + + return( ret ); +} + +/* + * Export into an ASCII string + */ +int mpi_write_string( const mpi *X, int radix, + char *buf, size_t buflen, size_t *olen ) +{ + int ret = 0; + size_t n; + char *p; + mpi T; + + if( radix < 2 || radix > 16 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + n = mpi_bitlen( X ); + if( radix >= 4 ) n >>= 1; + if( radix >= 16 ) n >>= 1; + n += 3; + + if( buflen < n ) + { + *olen = n; + return( ERR_MPI_BUFFER_TOO_SMALL ); + } + + p = buf; + mpi_init( &T ); + + if( X->s == -1 ) + *p++ = '-'; + + if( radix == 16 ) + { + int c; + size_t i, j, k; + + for( i = X->n, k = 0; i > 0; i-- ) + { + for( j = ciL; j > 0; j-- ) + { + c = ( X->p[i - 1] >> ( ( j - 1 ) << 3) ) & 0xFF; + + if( c == 0 && k == 0 && ( i + j ) != 2 ) + continue; + + *(p++) = "0123456789ABCDEF" [c / 16]; + *(p++) = "0123456789ABCDEF" [c % 16]; + k = 1; + } + } + } + else + { + MPI_CHK( mpi_copy( &T, X ) ); + + if( T.s == -1 ) + T.s = 1; + + MPI_CHK( mpi_write_hlp( &T, radix, &p ) ); + } + + *p++ = '\0'; + *olen = p - buf; + +cleanup: + + mpi_free( &T ); + + return( ret ); +} + +/* + * Import X from unsigned binary data, big endian + */ +int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ) +{ + int ret; + size_t i, j, n; + + for( n = 0; n < buflen; n++ ) + if( buf[n] != 0 ) + break; + + MPI_CHK( mpi_grow( X, CHARS_TO_LIMBS( buflen - n ) ) ); + MPI_CHK( mpi_lset( X, 0 ) ); + + for( i = buflen, j = 0; i > n; i--, j++ ) + X->p[j / ciL] |= ((mpi_uint) buf[i - 1]) << ((j % ciL) << 3); + +cleanup: + + return( ret ); +} + +/* + * Export X into unsigned binary data, big endian + */ +int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ) +{ + size_t i, j, n; + + n = mpi_size( X ); + + if( buflen < n ) + return( ERR_MPI_BUFFER_TOO_SMALL ); + + memset( buf, 0, buflen ); + + for( i = buflen - 1, j = 0; n > 0; i--, j++, n-- ) + buf[i] = (unsigned char)( X->p[j / ciL] >> ((j % ciL) << 3) ); + + return( 0 ); +} + +/* + * Left-shift: X <<= count + */ +int mpi_shift_l( mpi *X, size_t count ) +{ + int ret; + size_t i, v0, t1; + mpi_uint r0 = 0, r1; + + v0 = count / (biL ); + t1 = count & (biL - 1); + + i = mpi_bitlen( X ) + count; + + if( X->n * biL < i ) + MPI_CHK( mpi_grow( X, BITS_TO_LIMBS( i ) ) ); + + ret = 0; + + /* + * shift by count / limb_size + */ + if( v0 > 0 ) + { + for( i = X->n; i > v0; i-- ) + X->p[i - 1] = X->p[i - v0 - 1]; + + for( ; i > 0; i-- ) + X->p[i - 1] = 0; + } + + /* + * shift by count % limb_size + */ + if( t1 > 0 ) + { + for( i = v0; i < X->n; i++ ) + { + r1 = X->p[i] >> (biL - t1); + X->p[i] <<= t1; + X->p[i] |= r0; + r0 = r1; + } + } + +cleanup: + + return( ret ); +} + +/* + * Right-shift: X >>= count + */ +int mpi_shift_r( mpi *X, size_t count ) +{ + size_t i, v0, v1; + mpi_uint r0 = 0, r1; + + v0 = count / biL; + v1 = count & (biL - 1); + + if( v0 > X->n || ( v0 == X->n && v1 > 0 ) ) + return mpi_lset( X, 0 ); + + /* + * shift by count / limb_size + */ + if( v0 > 0 ) + { + for( i = 0; i < X->n - v0; i++ ) + X->p[i] = X->p[i + v0]; + + for( ; i < X->n; i++ ) + X->p[i] = 0; + } + + /* + * shift by count % limb_size + */ + if( v1 > 0 ) + { + for( i = X->n; i > 0; i-- ) + { + r1 = X->p[i - 1] << (biL - v1); + X->p[i - 1] >>= v1; + X->p[i - 1] |= r0; + r0 = r1; + } + } + + return( 0 ); +} + +/* + * Compare unsigned values + */ +int mpi_cmp_abs( const mpi *X, const mpi *Y ) +{ + size_t i, j; + + for( i = X->n; i > 0; i-- ) + if( X->p[i - 1] != 0 ) + break; + + for( j = Y->n; j > 0; j-- ) + if( Y->p[j - 1] != 0 ) + break; + + if( i == 0 && j == 0 ) + return( 0 ); + + if( i > j ) return( 1 ); + if( j > i ) return( -1 ); + + for( ; i > 0; i-- ) + { + if( X->p[i - 1] > Y->p[i - 1] ) return( 1 ); + if( X->p[i - 1] < Y->p[i - 1] ) return( -1 ); + } + + return( 0 ); +} + +/* + * Compare signed values + */ +int mpi_cmp_mpi( const mpi *X, const mpi *Y ) +{ + size_t i, j; + + for( i = X->n; i > 0; i-- ) + if( X->p[i - 1] != 0 ) + break; + + for( j = Y->n; j > 0; j-- ) + if( Y->p[j - 1] != 0 ) + break; + + if( i == 0 && j == 0 ) + return( 0 ); + + if( i > j ) return( X->s ); + if( j > i ) return( -Y->s ); + + if( X->s > 0 && Y->s < 0 ) return( 1 ); + if( Y->s > 0 && X->s < 0 ) return( -1 ); + + for( ; i > 0; i-- ) + { + if( X->p[i - 1] > Y->p[i - 1] ) return( X->s ); + if( X->p[i - 1] < Y->p[i - 1] ) return( -X->s ); + } + + return( 0 ); +} + +/* + * Compare signed values + */ +int mpi_cmp_int( const mpi *X, mpi_sint z ) +{ + mpi Y; + mpi_uint p[1]; + + *p = ( z < 0 ) ? -z : z; + Y.s = ( z < 0 ) ? -1 : 1; + Y.n = 1; + Y.p = p; + + return( mpi_cmp_mpi( X, &Y ) ); +} + +/* + * Unsigned addition: X = |A| + |B| (HAC 14.7) + */ +int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) +{ + int ret; + size_t i, j; + mpi_uint *o, *p, c; + + if( X == B ) + { + const mpi *T = A; A = X; B = T; + } + + if( X != A ) + MPI_CHK( mpi_copy( X, A ) ); + + /* + * X should always be positive as a result of unsigned additions. + */ + X->s = 1; + + for( j = B->n; j > 0; j-- ) + if( B->p[j - 1] != 0 ) + break; + + MPI_CHK( mpi_grow( X, j ) ); + + o = B->p; p = X->p; c = 0; + + for( i = 0; i < j; i++, o++, p++ ) + { + *p += c; c = ( *p < c ); + *p += *o; c += ( *p < *o ); + } + + while( c != 0 ) + { + if( i >= X->n ) + { + MPI_CHK( mpi_grow( X, i + 1 ) ); + p = X->p + i; + } + + *p += c; c = ( *p < c ); i++; p++; + } + +cleanup: + + return( ret ); +} + +/* + * Helper for mpi subtraction + */ +static void mpi_sub_hlp( size_t n, mpi_uint *s, mpi_uint *d ) +{ + size_t i; + mpi_uint c, z; + + for( i = c = 0; i < n; i++, s++, d++ ) + { + z = ( *d < c ); *d -= c; + c = ( *d < *s ) + z; *d -= *s; + } + + while( c != 0 ) + { + z = ( *d < c ); *d -= c; + c = z; i++; d++; + } +} + +/* + * Unsigned subtraction: X = |A| - |B| (HAC 14.9) + */ +int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ) +{ + mpi TB; + int ret; + size_t n; + + if( mpi_cmp_abs( A, B ) < 0 ) + return( ERR_MPI_NEGATIVE_VALUE ); + + mpi_init( &TB ); + + if( X == B ) + { + MPI_CHK( mpi_copy( &TB, B ) ); + B = &TB; + } + + if( X != A ) + MPI_CHK( mpi_copy( X, A ) ); + + /* + * X should always be positive as a result of unsigned subtractions. + */ + X->s = 1; + + ret = 0; + + for( n = B->n; n > 0; n-- ) + if( B->p[n - 1] != 0 ) + break; + + mpi_sub_hlp( n, B->p, X->p ); + +cleanup: + + mpi_free( &TB ); + + return( ret ); +} + +/* + * Signed addition: X = A + B + */ +int mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ) +{ + int ret, s = A->s; + + if( A->s * B->s < 0 ) + { + if( mpi_cmp_abs( A, B ) >= 0 ) + { + MPI_CHK( mpi_sub_abs( X, A, B ) ); + X->s = s; + } + else + { + MPI_CHK( mpi_sub_abs( X, B, A ) ); + X->s = -s; + } + } + else + { + MPI_CHK( mpi_add_abs( X, A, B ) ); + X->s = s; + } + +cleanup: + + return( ret ); +} + +/* + * Signed subtraction: X = A - B + */ +int mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ) +{ + int ret, s = A->s; + + if( A->s * B->s > 0 ) + { + if( mpi_cmp_abs( A, B ) >= 0 ) + { + MPI_CHK( mpi_sub_abs( X, A, B ) ); + X->s = s; + } + else + { + MPI_CHK( mpi_sub_abs( X, B, A ) ); + X->s = -s; + } + } + else + { + MPI_CHK( mpi_add_abs( X, A, B ) ); + X->s = s; + } + +cleanup: + + return( ret ); +} + +/* + * Signed addition: X = A + b + */ +int mpi_add_int( mpi *X, const mpi *A, mpi_sint b ) +{ + mpi _B; + mpi_uint p[1]; + + p[0] = ( b < 0 ) ? -b : b; + _B.s = ( b < 0 ) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return( mpi_add_mpi( X, A, &_B ) ); +} + +/* + * Signed subtraction: X = A - b + */ +int mpi_sub_int( mpi *X, const mpi *A, mpi_sint b ) +{ + mpi _B; + mpi_uint p[1]; + + p[0] = ( b < 0 ) ? -b : b; + _B.s = ( b < 0 ) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return( mpi_sub_mpi( X, A, &_B ) ); +} + +/* + * Helper for mpi multiplication + */ +static void mpi_mul_hlp( size_t i, mpi_uint *s, mpi_uint *d, mpi_uint b ) +{ + +} + +/* + * Baseline multiplication: X = A * B (HAC 14.12) + */ +int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) +{ + int ret; + size_t i, j; + size_t n = 0; + + mpi TA, TB; + + mpi_init( &TA ); mpi_init( &TB ); + + if( X == A ) { MPI_CHK( mpi_copy( &TA, A ) ); A = &TA; } + if( X == B ) { MPI_CHK( mpi_copy( &TB, B ) ); B = &TB; } + + for( i = A->n; i > 0; i-- ) + if( A->p[i - 1] != 0 ) + break; + + for( j = B->n; j > 0; j-- ) + if( B->p[j - 1] != 0 ) + break; + + MPI_CHK( mpi_grow( X, i + j ) ); + MPI_CHK( mpi_lset( X, 0 ) ); + + n = j; +// for( i++; j > 0; j-- ) + mpi_mul_hlp( i - 1, A->p, X->p + j - 1, B->p[j - 1] ); + + if (ets_bigint_mult_prepare(A->p, B->p, n)){ + ets_bigint_wait_finish(); + ets_bigint_mult_getz(X->p, n); + } else{ + mpi_printf("Baseline multiplication failed\n"); + } + + X->s = A->s * B->s; + +cleanup: + + mpi_free( &TB ); mpi_free( &TA ); + + return( ret ); +} + +/* + * Baseline multiplication: X = A * b + */ +int mpi_mul_int( mpi *X, const mpi *A, mpi_uint b ) +{ + mpi _B; + mpi_uint p[1]; + + _B.s = 1; + _B.n = 1; + _B.p = p; + p[0] = b; + + return( mpi_mul_mpi( X, A, &_B ) ); +} + +/* + * Unsigned integer divide - double mpi_uint dividend, u1/u0, and + * mpi_uint divisor, d + */ +static mpi_uint int_div_int( mpi_uint u1, + mpi_uint u0, mpi_uint d, mpi_uint *r ) +{ +#if defined(HAVE_UDBL) + t_udbl dividend, quotient; +#else + const mpi_uint radix = (mpi_uint) 1 << biH; + const mpi_uint uint_halfword_mask = ( (mpi_uint) 1 << biH ) - 1; + mpi_uint d0, d1, q0, q1, rAX, r0, quotient; + mpi_uint u0_msw, u0_lsw; + size_t s; +#endif + + /* + * Check for overflow + */ + if( 0 == d || u1 >= d ) + { + if (r != NULL) *r = ~0; + + return ( ~0 ); + } + +#if defined(HAVE_UDBL) + dividend = (t_udbl) u1 << biL; + dividend |= (t_udbl) u0; + quotient = dividend / d; + if( quotient > ( (t_udbl) 1 << biL ) - 1 ) + quotient = ( (t_udbl) 1 << biL ) - 1; + + if( r != NULL ) + *r = (mpi_uint)( dividend - (quotient * d ) ); + + return (mpi_uint) quotient; +#else + + /* + * Algorithm D, Section 4.3.1 - The Art of Computer Programming + * Vol. 2 - Seminumerical Algorithms, Knuth + */ + + /* + * Normalize the divisor, d, and dividend, u0, u1 + */ + s = clz( d ); + d = d << s; + + u1 = u1 << s; + u1 |= ( u0 >> ( biL - s ) ) & ( -(mpi_sint)s >> ( biL - 1 ) ); + u0 = u0 << s; + + d1 = d >> biH; + d0 = d & uint_halfword_mask; + + u0_msw = u0 >> biH; + u0_lsw = u0 & uint_halfword_mask; + + /* + * Find the first quotient and remainder + */ + q1 = u1 / d1; + r0 = u1 - d1 * q1; + + while( q1 >= radix || ( q1 * d0 > radix * r0 + u0_msw ) ) + { + q1 -= 1; + r0 += d1; + + if ( r0 >= radix ) break; + } + + rAX = ( u1 * radix ) + ( u0_msw - q1 * d ); + q0 = rAX / d1; + r0 = rAX - q0 * d1; + + while( q0 >= radix || ( q0 * d0 > radix * r0 + u0_lsw ) ) + { + q0 -= 1; + r0 += d1; + + if ( r0 >= radix ) break; + } + + if (r != NULL) + *r = ( rAX * radix + u0_lsw - q0 * d ) >> s; + + quotient = q1 * radix + q0; + + return quotient; +#endif +} + +/* + * Division by mpi: A = Q * B + R (HAC 14.20) + */ +int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ) +{ + int ret; + size_t i, n, t, k; + mpi X, Y, Z, T1, T2; + + if( mpi_cmp_int( B, 0 ) == 0 ) + return( ERR_MPI_DIVISION_BY_ZERO ); + + mpi_init( &X ); mpi_init( &Y ); mpi_init( &Z ); + mpi_init( &T1 ); mpi_init( &T2 ); + + if( mpi_cmp_abs( A, B ) < 0 ) + { + if( Q != NULL ) MPI_CHK( mpi_lset( Q, 0 ) ); + if( R != NULL ) MPI_CHK( mpi_copy( R, A ) ); + return( 0 ); + } + + MPI_CHK( mpi_copy( &X, A ) ); + MPI_CHK( mpi_copy( &Y, B ) ); + X.s = Y.s = 1; + + MPI_CHK( mpi_grow( &Z, A->n + 2 ) ); + MPI_CHK( mpi_lset( &Z, 0 ) ); + MPI_CHK( mpi_grow( &T1, 2 ) ); + MPI_CHK( mpi_grow( &T2, 3 ) ); + + k = mpi_bitlen( &Y ) % biL; + if( k < biL - 1 ) + { + k = biL - 1 - k; + MPI_CHK( mpi_shift_l( &X, k ) ); + MPI_CHK( mpi_shift_l( &Y, k ) ); + } + else k = 0; + + n = X.n - 1; + t = Y.n - 1; + MPI_CHK( mpi_shift_l( &Y, biL * ( n - t ) ) ); + + while( mpi_cmp_mpi( &X, &Y ) >= 0 ) + { + Z.p[n - t]++; + MPI_CHK( mpi_sub_mpi( &X, &X, &Y ) ); + } + MPI_CHK( mpi_shift_r( &Y, biL * ( n - t ) ) ); + + for( i = n; i > t ; i-- ) + { + if( X.p[i] >= Y.p[t] ) + Z.p[i - t - 1] = ~0; + else + { + Z.p[i - t - 1] = int_div_int( X.p[i], X.p[i - 1], + Y.p[t], NULL); + } + + Z.p[i - t - 1]++; + do + { + Z.p[i - t - 1]--; + + MPI_CHK( mpi_lset( &T1, 0 ) ); + T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1]; + T1.p[1] = Y.p[t]; + MPI_CHK( mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) ); + + MPI_CHK( mpi_lset( &T2, 0 ) ); + T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2]; + T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1]; + T2.p[2] = X.p[i]; + } + while( mpi_cmp_mpi( &T1, &T2 ) > 0 ); + + MPI_CHK( mpi_mul_int( &T1, &Y, Z.p[i - t - 1] ) ); + MPI_CHK( mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); + MPI_CHK( mpi_sub_mpi( &X, &X, &T1 ) ); + + if( mpi_cmp_int( &X, 0 ) < 0 ) + { + MPI_CHK( mpi_copy( &T1, &Y ) ); + MPI_CHK( mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); + MPI_CHK( mpi_add_mpi( &X, &X, &T1 ) ); + Z.p[i - t - 1]--; + } + } + + if( Q != NULL ) + { + MPI_CHK( mpi_copy( Q, &Z ) ); + Q->s = A->s * B->s; + } + + if( R != NULL ) + { + MPI_CHK( mpi_shift_r( &X, k ) ); + X.s = A->s; + MPI_CHK( mpi_copy( R, &X ) ); + + if( mpi_cmp_int( R, 0 ) == 0 ) + R->s = 1; + } + +cleanup: + + mpi_free( &X ); mpi_free( &Y ); mpi_free( &Z ); + mpi_free( &T1 ); mpi_free( &T2 ); + + return( ret ); +} + +/* + * Division by int: A = Q * b + R + */ +int mpi_div_int( mpi *Q, mpi *R, const mpi *A, mpi_sint b ) +{ + mpi _B; + mpi_uint p[1]; + + p[0] = ( b < 0 ) ? -b : b; + _B.s = ( b < 0 ) ? -1 : 1; + _B.n = 1; + _B.p = p; + + return( mpi_div_mpi( Q, R, A, &_B ) ); +} + +/* + * Modulo: R = A mod B + */ +int mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ) +{ + int ret; + + if( mpi_cmp_int( B, 0 ) < 0 ) + return( ERR_MPI_NEGATIVE_VALUE ); + + MPI_CHK( mpi_div_mpi( NULL, R, A, B ) ); + + while( mpi_cmp_int( R, 0 ) < 0 ) + MPI_CHK( mpi_add_mpi( R, R, B ) ); + + while( mpi_cmp_mpi( R, B ) >= 0 ) + MPI_CHK( mpi_sub_mpi( R, R, B ) ); + +cleanup: + + return( ret ); +} + +/* + * Modulo: r = A mod b + */ +int mpi_mod_int( mpi_uint *r, const mpi *A, mpi_sint b ) +{ + size_t i; + mpi_uint x, y, z; + + if( b == 0 ) + return( ERR_MPI_DIVISION_BY_ZERO ); + + if( b < 0 ) + return( ERR_MPI_NEGATIVE_VALUE ); + + /* + * handle trivial cases + */ + if( b == 1 ) + { + *r = 0; + return( 0 ); + } + + if( b == 2 ) + { + *r = A->p[0] & 1; + return( 0 ); + } + + /* + * general case + */ + for( i = A->n, y = 0; i > 0; i-- ) + { + x = A->p[i - 1]; + y = ( y << biH ) | ( x >> biH ); + z = y / b; + y -= z * b; + + x <<= biH; + y = ( y << biH ) | ( x >> biH ); + z = y / b; + y -= z * b; + } + + /* + * If A is negative, then the current y represents a negative value. + * Flipping it to the positive side. + */ + if( A->s < 0 && y != 0 ) + y = b - y; + + *r = y; + + return( 0 ); +} + +/* + * Fast Montgomery initialization (thanks to Tom St Denis) + */ +static void mpi_montg_init( mpi_uint *mm, const mpi *N ) +{ + mpi_uint x, m0 = N->p[0]; + unsigned int i; + + x = m0; + x += ( ( m0 + 2 ) & 4 ) << 1; + + for( i = biL; i >= 8; i /= 2 ) + x *= ( 2 - ( m0 * x ) ); + + *mm = ~x + 1; +} + +/* + * Montgomery multiplication: A = A * B * R^-1 mod N (HAC 14.36) + */ +static void mpi_montmul( mpi *A, const mpi *B, const mpi *N, mpi_uint mm, + const mpi *T ) +{ + size_t n, m; + mpi_uint *d = NULL; + + memset( T->p, 0, T->n * ciL ); + + d = T->p; + n = N->n; + m = ( B->n < n ) ? B->n : n; + + if (ets_bigint_montgomery_mult_prepare(N->p, B->p, d, m, n, false)) { + ets_bigint_wait_finish(); + + ets_bigint_montgomery_mult_getz(A->p, n); + } else{ + mpi_printf("Montgomery multiplication failed\n"); + } + +} + +/* + * Montgomery reduction: A = A * R^-1 mod N + */ +static void mpi_montred( mpi *A, const mpi *N, mpi_uint mm, const mpi *T ) +{ + mpi_uint z = 1; + mpi U; + + U.n = U.s = (int) z; + U.p = &z; + + mpi_montmul( A, &U, N, mm, T ); +} + +/* + * Sliding-window exponentiation: X = A^E mod N (HAC 14.85) + */ +int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) +{ + int ret; + size_t wbits, wsize, one = 1; + size_t i, j, nblimbs; + size_t bufsize, nbits; + mpi_uint ei, mm, state; + mpi RR, T, W[ 2 << MPI_WINDOW_SIZE ], Apos; + int neg; + + if( mpi_cmp_int( N, 0 ) < 0 || ( N->p[0] & 1 ) == 0 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + if( mpi_cmp_int( E, 0 ) < 0 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + /* + * Init temps and window size + */ + mpi_montg_init( &mm, N ); + mpi_init( &RR ); mpi_init( &T ); + mpi_init( &Apos ); + memset( W, 0, sizeof( W ) ); + + i = mpi_bitlen( E ); + + wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 : + ( i > 79 ) ? 4 : ( i > 23 ) ? 3 : 1; + + if( wsize > MPI_WINDOW_SIZE ) + wsize = MPI_WINDOW_SIZE; + + j = N->n + 1; + MPI_CHK( mpi_grow( X, j ) ); + MPI_CHK( mpi_grow( &W[1], j ) ); + MPI_CHK( mpi_grow( &T, j * 2 ) ); + + /* + * Compensate for negative A (and correct at the end) + */ + neg = ( A->s == -1 ); + if( neg ) + { + MPI_CHK( mpi_copy( &Apos, A ) ); + Apos.s = 1; + A = &Apos; + } + + /* + * If 1st call, pre-compute R^2 mod N + */ + if( _RR == NULL || _RR->p == NULL ) + { + MPI_CHK( mpi_lset( &RR, 1 ) ); + MPI_CHK( mpi_shift_l( &RR, N->n * 2 * biL ) ); + MPI_CHK( mpi_mod_mpi( &RR, &RR, N ) ); + + if( _RR != NULL ) + memcpy( _RR, &RR, sizeof( mpi ) ); + } + else + memcpy( &RR, _RR, sizeof( mpi ) ); + + /* + * W[1] = A * R^2 * R^-1 mod N = A * R mod N + */ + if( mpi_cmp_mpi( A, N ) >= 0 ) + MPI_CHK( mpi_mod_mpi( &W[1], A, N ) ); + else + MPI_CHK( mpi_copy( &W[1], A ) ); + + mpi_montmul( &W[1], &RR, N, mm, &T ); + + /* + * X = R^2 * R^-1 mod N = R mod N + */ + MPI_CHK( mpi_copy( X, &RR ) ); + mpi_montred( X, N, mm, &T ); + + if( wsize > 1 ) + { + /* + * W[1 << (wsize - 1)] = W[1] ^ (wsize - 1) + */ + j = one << ( wsize - 1 ); + + MPI_CHK( mpi_grow( &W[j], N->n + 1 ) ); + MPI_CHK( mpi_copy( &W[j], &W[1] ) ); + + for( i = 0; i < wsize - 1; i++ ) + mpi_montmul( &W[j], &W[j], N, mm, &T ); + + /* + * W[i] = W[i - 1] * W[1] + */ + for( i = j + 1; i < ( one << wsize ); i++ ) + { + MPI_CHK( mpi_grow( &W[i], N->n + 1 ) ); + MPI_CHK( mpi_copy( &W[i], &W[i - 1] ) ); + + mpi_montmul( &W[i], &W[1], N, mm, &T ); + } + } + + nblimbs = E->n; + bufsize = 0; + nbits = 0; + wbits = 0; + state = 0; + + while( 1 ) + { + if( bufsize == 0 ) + { + if( nblimbs == 0 ) + break; + + nblimbs--; + + bufsize = sizeof( mpi_uint ) << 3; + } + + bufsize--; + + ei = (E->p[nblimbs] >> bufsize) & 1; + + /* + * skip leading 0s + */ + if( ei == 0 && state == 0 ) + continue; + + if( ei == 0 && state == 1 ) + { + /* + * out of window, square X + */ + mpi_montmul( X, X, N, mm, &T ); + continue; + } + + /* + * add ei to current window + */ + state = 2; + + nbits++; + wbits |= ( ei << ( wsize - nbits ) ); + + if( nbits == wsize ) + { + /* + * X = X^wsize R^-1 mod N + */ + for( i = 0; i < wsize; i++ ) + mpi_montmul( X, X, N, mm, &T ); + + /* + * X = X * W[wbits] R^-1 mod N + */ + mpi_montmul( X, &W[wbits], N, mm, &T ); + + state--; + nbits = 0; + wbits = 0; + } + } + + /* + * process the remaining bits + */ + for( i = 0; i < nbits; i++ ) + { + mpi_montmul( X, X, N, mm, &T ); + + wbits <<= 1; + + if( ( wbits & ( one << wsize ) ) != 0 ) + mpi_montmul( X, &W[1], N, mm, &T ); + } + + /* + * X = A^E * R * R^-1 mod N = A^E mod N + */ + mpi_montred( X, N, mm, &T ); + + if( neg ) + { + X->s = -1; + MPI_CHK( mpi_add_mpi( X, N, X ) ); + } + +cleanup: + + for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ ) + mpi_free( &W[i] ); + + mpi_free( &W[1] ); mpi_free( &T ); mpi_free( &Apos ); + + if( _RR == NULL || _RR->p == NULL ) + mpi_free( &RR ); + + return( ret ); +} + +/* + * Greatest common divisor: G = gcd(A, B) (HAC 14.54) + */ +int mpi_gcd( mpi *G, const mpi *A, const mpi *B ) +{ + int ret; + size_t lz, lzt; + mpi TG, TA, TB; + + mpi_init( &TG ); mpi_init( &TA ); mpi_init( &TB ); + + MPI_CHK( mpi_copy( &TA, A ) ); + MPI_CHK( mpi_copy( &TB, B ) ); + + lz = mpi_lsb( &TA ); + lzt = mpi_lsb( &TB ); + + if( lzt < lz ) + lz = lzt; + + MPI_CHK( mpi_shift_r( &TA, lz ) ); + MPI_CHK( mpi_shift_r( &TB, lz ) ); + + TA.s = TB.s = 1; + + while( mpi_cmp_int( &TA, 0 ) != 0 ) + { + MPI_CHK( mpi_shift_r( &TA, mpi_lsb( &TA ) ) ); + MPI_CHK( mpi_shift_r( &TB, mpi_lsb( &TB ) ) ); + + if( mpi_cmp_mpi( &TA, &TB ) >= 0 ) + { + MPI_CHK( mpi_sub_abs( &TA, &TA, &TB ) ); + MPI_CHK( mpi_shift_r( &TA, 1 ) ); + } + else + { + MPI_CHK( mpi_sub_abs( &TB, &TB, &TA ) ); + MPI_CHK( mpi_shift_r( &TB, 1 ) ); + } + } + + MPI_CHK( mpi_shift_l( &TB, lz ) ); + MPI_CHK( mpi_copy( G, &TB ) ); + +cleanup: + + mpi_free( &TG ); mpi_free( &TA ); mpi_free( &TB ); + + return( ret ); +} + +/* + * Fill X with size bytes of random. + * + * Use a temporary bytes representation to make sure the result is the same + * regardless of the platform endianness (useful when f_rng is actually + * deterministic, eg for tests). + */ +int mpi_fill_random( mpi *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + unsigned char buf[MPI_MAX_SIZE]; + + if( size > MPI_MAX_SIZE ) + return( ERR_MPI_BAD_INPUT_DATA ); + + MPI_CHK( f_rng( p_rng, buf, size ) ); + MPI_CHK( mpi_read_binary( X, buf, size ) ); + +cleanup: + return( ret ); +} + +/* + * Modular inverse: X = A^-1 mod N (HAC 14.61 / 14.64) + */ +int mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ) +{ + int ret; + mpi G, TA, TU, U1, U2, TB, TV, V1, V2; + + if( mpi_cmp_int( N, 0 ) <= 0 ) + return( ERR_MPI_BAD_INPUT_DATA ); + + mpi_init( &TA ); mpi_init( &TU ); mpi_init( &U1 ); mpi_init( &U2 ); + mpi_init( &G ); mpi_init( &TB ); mpi_init( &TV ); + mpi_init( &V1 ); mpi_init( &V2 ); + + MPI_CHK( mpi_gcd( &G, A, N ) ); + + if( mpi_cmp_int( &G, 1 ) != 0 ) + { + ret = ERR_MPI_NOT_ACCEPTABLE; + goto cleanup; + } + + MPI_CHK( mpi_mod_mpi( &TA, A, N ) ); + MPI_CHK( mpi_copy( &TU, &TA ) ); + MPI_CHK( mpi_copy( &TB, N ) ); + MPI_CHK( mpi_copy( &TV, N ) ); + + MPI_CHK( mpi_lset( &U1, 1 ) ); + MPI_CHK( mpi_lset( &U2, 0 ) ); + MPI_CHK( mpi_lset( &V1, 0 ) ); + MPI_CHK( mpi_lset( &V2, 1 ) ); + + do + { + while( ( TU.p[0] & 1 ) == 0 ) + { + MPI_CHK( mpi_shift_r( &TU, 1 ) ); + + if( ( U1.p[0] & 1 ) != 0 || ( U2.p[0] & 1 ) != 0 ) + { + MPI_CHK( mpi_add_mpi( &U1, &U1, &TB ) ); + MPI_CHK( mpi_sub_mpi( &U2, &U2, &TA ) ); + } + + MPI_CHK( mpi_shift_r( &U1, 1 ) ); + MPI_CHK( mpi_shift_r( &U2, 1 ) ); + } + + while( ( TV.p[0] & 1 ) == 0 ) + { + MPI_CHK( mpi_shift_r( &TV, 1 ) ); + + if( ( V1.p[0] & 1 ) != 0 || ( V2.p[0] & 1 ) != 0 ) + { + MPI_CHK( mpi_add_mpi( &V1, &V1, &TB ) ); + MPI_CHK( mpi_sub_mpi( &V2, &V2, &TA ) ); + } + + MPI_CHK( mpi_shift_r( &V1, 1 ) ); + MPI_CHK( mpi_shift_r( &V2, 1 ) ); + } + + if( mpi_cmp_mpi( &TU, &TV ) >= 0 ) + { + MPI_CHK( mpi_sub_mpi( &TU, &TU, &TV ) ); + MPI_CHK( mpi_sub_mpi( &U1, &U1, &V1 ) ); + MPI_CHK( mpi_sub_mpi( &U2, &U2, &V2 ) ); + } + else + { + MPI_CHK( mpi_sub_mpi( &TV, &TV, &TU ) ); + MPI_CHK( mpi_sub_mpi( &V1, &V1, &U1 ) ); + MPI_CHK( mpi_sub_mpi( &V2, &V2, &U2 ) ); + } + } + while( mpi_cmp_int( &TU, 0 ) != 0 ); + + while( mpi_cmp_int( &V1, 0 ) < 0 ) + MPI_CHK( mpi_add_mpi( &V1, &V1, N ) ); + + while( mpi_cmp_mpi( &V1, N ) >= 0 ) + MPI_CHK( mpi_sub_mpi( &V1, &V1, N ) ); + + MPI_CHK( mpi_copy( X, &V1 ) ); + +cleanup: + + mpi_free( &TA ); mpi_free( &TU ); mpi_free( &U1 ); mpi_free( &U2 ); + mpi_free( &G ); mpi_free( &TB ); mpi_free( &TV ); + mpi_free( &V1 ); mpi_free( &V2 ); + + return( ret ); +} + +static const int small_prime[] = +{ + 3, 5, 7, 11, 13, 17, 19, 23, + 29, 31, 37, 41, 43, 47, 53, 59, + 61, 67, 71, 73, 79, 83, 89, 97, + 101, 103, 107, 109, 113, 127, 131, 137, + 139, 149, 151, 157, 163, 167, 173, 179, + 181, 191, 193, 197, 199, 211, 223, 227, + 229, 233, 239, 241, 251, 257, 263, 269, + 271, 277, 281, 283, 293, 307, 311, 313, + 317, 331, 337, 347, 349, 353, 359, 367, + 373, 379, 383, 389, 397, 401, 409, 419, + 421, 431, 433, 439, 443, 449, 457, 461, + 463, 467, 479, 487, 491, 499, 503, 509, + 521, 523, 541, 547, 557, 563, 569, 571, + 577, 587, 593, 599, 601, 607, 613, 617, + 619, 631, 641, 643, 647, 653, 659, 661, + 673, 677, 683, 691, 701, 709, 719, 727, + 733, 739, 743, 751, 757, 761, 769, 773, + 787, 797, 809, 811, 821, 823, 827, 829, + 839, 853, 857, 859, 863, 877, 881, 883, + 887, 907, 911, 919, 929, 937, 941, 947, + 953, 967, 971, 977, 983, 991, 997, -103 +}; + +/* + * Small divisors test (X must be positive) + * + * Return values: + * 0: no small factor (possible prime, more tests needed) + * 1: certain prime + * ERR_MPI_NOT_ACCEPTABLE: certain non-prime + * other negative: error + */ +static int mpi_check_small_factors( const mpi *X ) +{ + int ret = 0; + size_t i; + mpi_uint r; + + if( ( X->p[0] & 1 ) == 0 ) + return( ERR_MPI_NOT_ACCEPTABLE ); + + for( i = 0; small_prime[i] > 0; i++ ) + { + if( mpi_cmp_int( X, small_prime[i] ) <= 0 ) + return( 1 ); + + MPI_CHK( mpi_mod_int( &r, X, small_prime[i] ) ); + + if( r == 0 ) + return( ERR_MPI_NOT_ACCEPTABLE ); + } + +cleanup: + return( ret ); +} + +/* + * Miller-Rabin pseudo-primality test (HAC 4.24) + */ +static int mpi_miller_rabin( const mpi *X, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret, count; + size_t i, j, k, n, s; + mpi W, R, T, A, RR; + + mpi_init( &W ); mpi_init( &R ); mpi_init( &T ); mpi_init( &A ); + mpi_init( &RR ); + + /* + * W = |X| - 1 + * R = W >> lsb( W ) + */ + MPI_CHK( mpi_sub_int( &W, X, 1 ) ); + s = mpi_lsb( &W ); + MPI_CHK( mpi_copy( &R, &W ) ); + MPI_CHK( mpi_shift_r( &R, s ) ); + + i = mpi_bitlen( X ); + /* + * HAC, table 4.4 + */ + n = ( ( i >= 1300 ) ? 2 : ( i >= 850 ) ? 3 : + ( i >= 650 ) ? 4 : ( i >= 350 ) ? 8 : + ( i >= 250 ) ? 12 : ( i >= 150 ) ? 18 : 27 ); + + for( i = 0; i < n; i++ ) + { + /* + * pick a random A, 1 < A < |X| - 1 + */ + MPI_CHK( mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); + + if( mpi_cmp_mpi( &A, &W ) >= 0 ) + { + j = mpi_bitlen( &A ) - mpi_bitlen( &W ); + MPI_CHK( mpi_shift_r( &A, j + 1 ) ); + } + A.p[0] |= 3; + + count = 0; + do { + MPI_CHK( mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); + + j = mpi_bitlen( &A ); + k = mpi_bitlen( &W ); + if (j > k) { + MPI_CHK( mpi_shift_r( &A, j - k ) ); + } + + if (count++ > 30) { + return ERR_MPI_NOT_ACCEPTABLE; + } + + } while ( mpi_cmp_mpi( &A, &W ) >= 0 || + mpi_cmp_int( &A, 1 ) <= 0 ); + + /* + * A = A^R mod |X| + */ + MPI_CHK( mpi_exp_mod( &A, &A, &R, X, &RR ) ); + + if( mpi_cmp_mpi( &A, &W ) == 0 || + mpi_cmp_int( &A, 1 ) == 0 ) + continue; + + j = 1; + while( j < s && mpi_cmp_mpi( &A, &W ) != 0 ) + { + /* + * A = A * A mod |X| + */ + MPI_CHK( mpi_mul_mpi( &T, &A, &A ) ); + MPI_CHK( mpi_mod_mpi( &A, &T, X ) ); + + if( mpi_cmp_int( &A, 1 ) == 0 ) + break; + + j++; + } + + /* + * not prime if A != |X| - 1 or A == 1 + */ + if( mpi_cmp_mpi( &A, &W ) != 0 || + mpi_cmp_int( &A, 1 ) == 0 ) + { + ret = ERR_MPI_NOT_ACCEPTABLE; + break; + } + } + +cleanup: + mpi_free( &W ); mpi_free( &R ); mpi_free( &T ); mpi_free( &A ); + mpi_free( &RR ); + + return( ret ); +} + +/* + * Pseudo-primality test: small factors, then Miller-Rabin + */ +int mpi_is_prime( const mpi *X, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + mpi XX; + + XX.s = 1; + XX.n = X->n; + XX.p = X->p; + + if( mpi_cmp_int( &XX, 0 ) == 0 || + mpi_cmp_int( &XX, 1 ) == 0 ) + return( ERR_MPI_NOT_ACCEPTABLE ); + + if( mpi_cmp_int( &XX, 2 ) == 0 ) + return( 0 ); + + if( ( ret = mpi_check_small_factors( &XX ) ) != 0 ) + { + if( ret == 1 ) + return( 0 ); + + return( ret ); + } + + return( mpi_miller_rabin( &XX, f_rng, p_rng ) ); +} + +/* + * Prime number generation + */ +int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + size_t k, n; + mpi_uint r; + mpi Y; + + if( nbits < 3 || nbits > MPI_MAX_BITS ) + return( ERR_MPI_BAD_INPUT_DATA ); + + mpi_init( &Y ); + + n = BITS_TO_LIMBS( nbits ); + + MPI_CHK( mpi_fill_random( X, n * ciL, f_rng, p_rng ) ); + + k = mpi_bitlen( X ); + if( k > nbits ) MPI_CHK( mpi_shift_r( X, k - nbits + 1 ) ); + + mpi_set_bit( X, nbits-1, 1 ); + + X->p[0] |= 1; + + if( dh_flag == 0 ) + { + while( ( ret = mpi_is_prime( X, f_rng, p_rng ) ) != 0 ) + { + if( ret != ERR_MPI_NOT_ACCEPTABLE ) + goto cleanup; + + MPI_CHK( mpi_add_int( X, X, 2 ) ); + } + } + else + { + /* + * An necessary condition for Y and X = 2Y + 1 to be prime + * is X = 2 mod 3 (which is equivalent to Y = 2 mod 3). + * Make sure it is satisfied, while keeping X = 3 mod 4 + */ + + X->p[0] |= 2; + + MPI_CHK( mpi_mod_int( &r, X, 3 ) ); + if( r == 0 ) + MPI_CHK( mpi_add_int( X, X, 8 ) ); + else if( r == 1 ) + MPI_CHK( mpi_add_int( X, X, 4 ) ); + + /* Set Y = (X-1) / 2, which is X / 2 because X is odd */ + MPI_CHK( mpi_copy( &Y, X ) ); + MPI_CHK( mpi_shift_r( &Y, 1 ) ); + + while( 1 ) + { + /* + * First, check small factors for X and Y + * before doing Miller-Rabin on any of them + */ + if( ( ret = mpi_check_small_factors( X ) ) == 0 && + ( ret = mpi_check_small_factors( &Y ) ) == 0 && + ( ret = mpi_miller_rabin( X, f_rng, p_rng ) ) == 0 && + ( ret = mpi_miller_rabin( &Y, f_rng, p_rng ) ) == 0 ) + { + break; + } + + if( ret != ERR_MPI_NOT_ACCEPTABLE ) + goto cleanup; + + /* + * Next candidates. We want to preserve Y = (X-1) / 2 and + * Y = 1 mod 2 and Y = 2 mod 3 (eq X = 3 mod 4 and X = 2 mod 3) + * so up Y by 6 and X by 12. + */ + MPI_CHK( mpi_add_int( X, X, 12 ) ); + MPI_CHK( mpi_add_int( &Y, &Y, 6 ) ); + } + } + +cleanup: + + mpi_free( &Y ); + + return( ret ); +} + + +#endif /* ESP_BIGNUM_ALT */ + diff --git a/components/mbedtls/port/sha1_alt.c b/components/mbedtls/port/sha1_alt.c new file mode 100644 index 000000000..32a970704 --- /dev/null +++ b/components/mbedtls/port/sha1_alt.c @@ -0,0 +1,102 @@ +/* + * FIPS-180-1 compliant SHA-1 implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ + +#include "port/sha1_alt.h" + +#if defined(ESP_SHA1_C) +#include + +/* Implementation that should never be optimized out by the compiler */ +static void sha1_zeroize( void *v, size_t n ) { + volatile unsigned char *p = v; while( n-- ) *p++ = 0; +} + +void sha1_init( SHA1_CTX *ctx ) +{ + memset( ctx, 0, sizeof( SHA1_CTX ) ); + ets_sha_enable(); +} + +void sha1_free( SHA1_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + sha1_zeroize( ctx, sizeof( SHA1_CTX ) ); + ets_sha_disable(); +} + +void sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) +{ + *dst = *src; +} + +void sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) +{ + +} + +/* + * SHA-1 context setup + */ +void sha1_starts( SHA1_CTX *ctx ) +{ + ets_sha_init(&ctx->context); + ctx->context_type = SHA1; +} + +/* + * SHA-1 process buffer + */ +void sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) +{ + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); +} + +/* + * SHA-1 final digest + */ +void sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) +{ + ets_sha_finish(&ctx->context, ctx->context_type, output); +} + +/* + * output = SHA-1( input buffer ) + */ +void sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ) +{ + SHA1_CTX ctx; + + sha1_init( &ctx ); + sha1_starts( &ctx ); + sha1_update( &ctx, input, ilen ); + sha1_finish( &ctx, output ); + sha1_free( &ctx ); +} + +#endif /* _SHA1_C */ + + diff --git a/components/mbedtls/port/sha256_alt.c b/components/mbedtls/port/sha256_alt.c new file mode 100644 index 000000000..781cfa7a1 --- /dev/null +++ b/components/mbedtls/port/sha256_alt.c @@ -0,0 +1,107 @@ +/* + * FIPS-180-2 compliant SHA-256 implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The SHA-256 Secure Hash Standard was published by NIST in 2002. + * + * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ + +#include "port/sha256_alt.h" + +#if defined(ESP_SHA256_C) +#include + +/* Implementation that should never be optimized out by the compiler */ +static void sha256_zeroize( void *v, size_t n ) { + volatile unsigned char *p = v; while( n-- ) *p++ = 0; +} + +void sha256_init( SHA256_CTX *ctx ) +{ + memset( ctx, 0, sizeof( SHA256_CTX ) ); + ets_sha_enable(); +} + +void sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) +{ + +} + +void sha256_free( SHA256_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + sha256_zeroize( ctx, sizeof( SHA256_CTX ) ); + ets_sha_disable(); +} + +void sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) +{ + *dst = *src; +} + +/* + * SHA-256 context setup + */ +void sha256_starts( SHA256_CTX *ctx, int is224 ) +{ + ets_sha_init(&ctx->context); + if( is224 == 0 ) + { + /* SHA-256 */ + ctx->context_type = SHA256; + }else{ + /* SHA-224 */ + ctx->context_type = SHA224; + } +} + +/* + * SHA-256 process buffer + */ +void sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) +{ + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); +} + +/* + * SHA-256 final digest + */ +void sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) +{ + ets_sha_finish(&ctx->context, ctx->context_type, output); +} + +/* + * output = SHA-256( input buffer ) + */ +void sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ) +{ + SHA256_CTX ctx; + + sha256_init( &ctx ); + sha256_starts( &ctx, is224 ); + sha256_update( &ctx, input, ilen ); + sha256_finish( &ctx, output ); + sha256_free( &ctx ); +} + +#endif /* SHA256_C */ diff --git a/components/mbedtls/port/sha512_alt.c b/components/mbedtls/port/sha512_alt.c new file mode 100644 index 000000000..9884dd8d1 --- /dev/null +++ b/components/mbedtls/port/sha512_alt.c @@ -0,0 +1,103 @@ +/* + * FIPS-180-2 compliant SHA-384/512 implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The SHA-512 Secure Hash Standard was published by NIST in 2002. + * + * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ +#include "port/sha512_alt.h" + +#if defined(ESP_SHA512_C) +#include + +/* Implementation that should never be optimized out by the compiler */ +static void sha512_zeroize( void *v, size_t n ) { + volatile unsigned char *p = v; while( n-- ) *p++ = 0; +} + +void sha512_init( SHA512_CTX *ctx ) +{ + memset( ctx, 0, sizeof( SHA512_CTX ) ); + ets_sha_enable(); +} + +void sha512_free( SHA512_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + sha512_zeroize( ctx, sizeof( SHA512_CTX ) ); + ets_sha_disable(); +} + +void sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) +{ + *dst = *src; +} + +/* + * SHA-512 context setup + */ +void sha512_starts( SHA512_CTX *ctx, int is384 ) +{ + ets_sha_init(&ctx->context); + if( is384 == 0 ) + { + /* SHA-512 */ + ctx->context_type = SHA2_512; + } + else + { + /* SHA-384 */ + ctx->context_type = SHA2_384; + } +} + +/* + * SHA-512 process buffer + */ +void sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) +{ + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); +} + +/* + * SHA-512 final digest + */ +void sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) +{ + ets_sha_finish(&ctx->context, ctx->context_type, output); +} + +/* + * output = SHA-512( input buffer ) + */ +void sha512_output( const unsigned char *input, size_t ilen,unsigned char output[64], int is384 ) +{ + SHA512_CTX ctx; + + sha512_init( &ctx ); + sha512_starts( &ctx, is384 ); + sha512_update( &ctx, input, ilen ); + sha512_finish( &ctx, output ); + sha512_free( &ctx ); +} + +#endif /* SHA512_C */ From d9b660f6d405c9faf5e43489bb025e67418684b6 Mon Sep 17 00:00:00 2001 From: liuhan Date: Mon, 8 Aug 2016 13:56:36 +0800 Subject: [PATCH 02/57] 1. add lock function for every function 2. modify some function for crypto --- components/mbedtls/include/mbedtls/aes.h | 22 ++- components/mbedtls/include/mbedtls/bignum.h | 50 ++++++ .../mbedtls/include/mbedtls/esp_config.h | 148 +++++++++--------- components/mbedtls/include/mbedtls/sha1.h | 12 +- components/mbedtls/include/mbedtls/sha256.h | 12 +- components/mbedtls/include/mbedtls/sha512.h | 12 +- components/mbedtls/include/port/aes_alt.h | 9 +- .../mbedtls/include/port/multi_thread.h | 63 ++++++++ components/mbedtls/library/bignum.c | 3 + components/mbedtls/port/aes_alt.c | 74 ++++++++- components/mbedtls/port/bignum_alt.c | 14 +- components/mbedtls/port/multi_thread.c | 53 +++++++ components/mbedtls/port/sha1_alt.c | 17 +- components/mbedtls/port/sha256_alt.c | 17 +- components/mbedtls/port/sha512_alt.c | 16 +- 15 files changed, 436 insertions(+), 86 deletions(-) create mode 100644 components/mbedtls/include/port/multi_thread.h create mode 100644 components/mbedtls/port/multi_thread.c diff --git a/components/mbedtls/include/mbedtls/aes.h b/components/mbedtls/include/mbedtls/aes.h index a36e825a2..f5e1600b3 100644 --- a/components/mbedtls/include/mbedtls/aes.h +++ b/components/mbedtls/include/mbedtls/aes.h @@ -276,7 +276,27 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, #endif #else /* MBEDTLS_AES_ALT */ -#include "aes_alt.h" +#include "port/aes_alt.h" + +typedef AES_CTX mbedtls_aes_context; + +#define mbedtls_aes_init aes_init +#define mbedtls_aes_free aes_free +#define mbedtls_aes_setkey_enc aes_setkey_enc +#define mbedtls_aes_setkey_dec aes_setkey_dec +#define mbedtls_aes_crypt_ecb aes_crypt_ecb +#if defined(MBEDTLS_CIPHER_MODE_CBC) +#define mbedtls_aes_crypt_cbc aes_crypt_cbc +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) +#define mbedtls_aes_crypt_cfb128 aes_crypt_cfb128 +#define mbedtls_aes_crypt_cfb8 aes_crypt_cfb8 +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) +#define mbedtls_aes_crypt_ctr aes_crypt_ctr +#endif +#define mbedtls_aes_encrypt aes_encrypt +#define mbedtls_aes_decrypt aes_decrypt #endif /* MBEDTLS_AES_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/mbedtls/bignum.h b/components/mbedtls/include/mbedtls/bignum.h index aa51556a5..d062a7511 100644 --- a/components/mbedtls/include/mbedtls/bignum.h +++ b/components/mbedtls/include/mbedtls/bignum.h @@ -100,6 +100,8 @@ #define MBEDTLS_LN_2_DIV_LN_10_SCALE100 332 #define MBEDTLS_MPI_RW_BUFFER_SIZE ( ((MBEDTLS_MPI_MAX_BITS_SCALE100 + MBEDTLS_LN_2_DIV_LN_10_SCALE100 - 1) / MBEDTLS_LN_2_DIV_LN_10_SCALE100) + 10 + 6 ) +#if !defined(MBEDTLS_BIGNUM_ALT) + /* * Define the base integer type, architecture-wise. * @@ -702,6 +704,54 @@ int mbedtls_mpi_is_prime( const mbedtls_mpi *X, int mbedtls_mpi_gen_prime( mbedtls_mpi *X, size_t nbits, int dh_flag, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); +#else /* MBEDTLS_BIGNUM_ALT */ +#include "port/bignum_alt.h" + +typedef mpi mbedtls_mpi; + +#define mbedtls_mpi_init mpi_init +#define mbedtls_mpi_free mpi_free +#define mbedtls_mpi_grow mpi_grow +#define mbedtls_mpi_shrink mpi_shrink +#define mbedtls_mpi_copy mpi_copy +#define mbedtls_mpi_swap mpi_swap +#define mbedtls_mpi_safe_cond_assign mpi_safe_cond_assign +#define mbedtls_mpi_safe_cond_swap mpi_safe_cond_swap +#define mbedtls_mpi_lset mpi_lset +#define mbedtls_mpi_get_bit mpi_get_bit +#define mbedtls_mpi_set_bit mpi_set_bit +#define mbedtls_mpi_lsb mpi_lsb +#define mbedtls_mpi_bitlen mpi_bitlen +#define mbedtls_mpi_size mpi_size +#define mbedtls_mpi_read_string mpi_read_string +#define mbedtls_mpi_write_string mpi_write_string +#define mbedtls_mpi_read_binary mpi_read_binary +#define mbedtls_mpi_write_binary mpi_write_binary +#define mbedtls_mpi_shift_l mpi_shift_l +#define mbedtls_mpi_shift_r mpi_shift_r +#define mbedtls_mpi_cmp_abs mpi_cmp_abs +#define mbedtls_mpi_cmp_mpi mpi_cmp_mpi +#define mbedtls_mpi_cmp_int mpi_cmp_int +#define mbedtls_mpi_add_abs mpi_add_abs +#define mbedtls_mpi_sub_abs mpi_sub_abs +#define mbedtls_mpi_add_mpi mpi_add_mpi +#define mbedtls_mpi_sub_mpi mpi_sub_mpi +#define mbedtls_mpi_add_int mpi_add_int +#define mbedtls_mpi_sub_int mpi_sub_int +#define mbedtls_mpi_mul_mpi mpi_mul_mpi +#define mbedtls_mpi_mul_int mpi_mul_int +#define mbedtls_mpi_div_mpi mpi_div_mpi +#define mbedtls_mpi_div_int mpi_div_int +#define mbedtls_mpi_mod_mpi mpi_mod_mpi +#define mbedtls_mpi_mod_int mpi_mod_int +#define mbedtls_mpi_exp_mod mpi_exp_mod +#define mbedtls_mpi_fill_random mpi_fill_random +#define mbedtls_mpi_gcd mpi_gcd +#define mbedtls_mpi_inv_mod mpi_inv_mod +#define mbedtls_mpi_is_prime mpi_is_prime +#define mbedtls_mpi_gen_prime mpi_gen_prime + +#endif /* MBEDTLS_BIGNUM_ALT */ /** * \brief Checkup routine diff --git a/components/mbedtls/include/mbedtls/esp_config.h b/components/mbedtls/include/mbedtls/esp_config.h index 50c3ee2af..614e8018b 100644 --- a/components/mbedtls/include/mbedtls/esp_config.h +++ b/components/mbedtls/include/mbedtls/esp_config.h @@ -225,7 +225,7 @@ * Uncomment a macro to enable alternate implementation of the corresponding * module. */ -//#define MBEDTLS_AES_ALT +#define MBEDTLS_AES_ALT //#define MBEDTLS_ARC4_ALT //#define MBEDTLS_BLOWFISH_ALT //#define MBEDTLS_CAMELLIA_ALT @@ -235,10 +235,11 @@ //#define MBEDTLS_MD4_ALT //#define MBEDTLS_MD5_ALT //#define MBEDTLS_RIPEMD160_ALT -//#define MBEDTLS_SHA1_ALT -//#define MBEDTLS_SHA256_ALT -//#define MBEDTLS_SHA512_ALT +#define MBEDTLS_SHA1_ALT +#define MBEDTLS_SHA256_ALT +#define MBEDTLS_SHA512_ALT +#define MBEDTLS_BIGNUM_ALT /** * \def MBEDTLS_MD2_PROCESS_ALT * @@ -297,7 +298,7 @@ * * Uncomment this macro to store the AES tables in ROM. */ -//#define MBEDTLS_AES_ROM_TABLES +#define MBEDTLS_AES_ROM_TABLES /** * \def MBEDTLS_CAMELLIA_SMALL_MEMORY @@ -373,10 +374,10 @@ * * Enable padding modes in the cipher layer. */ -#define MBEDTLS_CIPHER_PADDING_PKCS7 -#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS -#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN -#define MBEDTLS_CIPHER_PADDING_ZEROS +//#define MBEDTLS_CIPHER_PADDING_PKCS7 +//#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +//#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +//#define MBEDTLS_CIPHER_PADDING_ZEROS /** * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES @@ -414,18 +415,18 @@ * * Comment macros to disable the curve and functions for it */ -#define MBEDTLS_ECP_DP_SECP192R1_ENABLED -#define MBEDTLS_ECP_DP_SECP224R1_ENABLED -#define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#define MBEDTLS_ECP_DP_SECP384R1_ENABLED -#define MBEDTLS_ECP_DP_SECP521R1_ENABLED -#define MBEDTLS_ECP_DP_SECP192K1_ENABLED -#define MBEDTLS_ECP_DP_SECP224K1_ENABLED -#define MBEDTLS_ECP_DP_SECP256K1_ENABLED -#define MBEDTLS_ECP_DP_BP256R1_ENABLED -#define MBEDTLS_ECP_DP_BP384R1_ENABLED -#define MBEDTLS_ECP_DP_BP512R1_ENABLED -#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +//#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +//#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +//#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +//#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +//#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +//#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +//#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +//#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +//#define MBEDTLS_ECP_DP_BP256R1_ENABLED +//#define MBEDTLS_ECP_DP_BP384R1_ENABLED +//#define MBEDTLS_ECP_DP_BP512R1_ENABLED +//#define MBEDTLS_ECP_DP_CURVE25519_ENABLED /** * \def MBEDTLS_ECP_NIST_OPTIM @@ -436,7 +437,7 @@ * * Comment this macro to disable NIST curves optimisation. */ -#define MBEDTLS_ECP_NIST_OPTIM +//#define MBEDTLS_ECP_NIST_OPTIM /** * \def MBEDTLS_ECDSA_DETERMINISTIC @@ -450,7 +451,7 @@ * * Comment this macro to disable deterministic ECDSA. */ -#define MBEDTLS_ECDSA_DETERMINISTIC +//#define MBEDTLS_ECDSA_DETERMINISTIC /** * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED @@ -472,7 +473,7 @@ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA */ -#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED @@ -496,7 +497,7 @@ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA */ -#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED @@ -516,7 +517,7 @@ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA */ -#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED @@ -595,7 +596,7 @@ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA */ -#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED @@ -620,7 +621,7 @@ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA */ -#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED @@ -644,7 +645,7 @@ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA */ -#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED @@ -668,7 +669,7 @@ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 */ -#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED @@ -692,7 +693,7 @@ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 */ -#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED +//#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED @@ -945,7 +946,7 @@ * * Comment this macro to disable support for Encrypt-then-MAC */ -#define MBEDTLS_SSL_ENCRYPT_THEN_MAC +//#define MBEDTLS_SSL_ENCRYPT_THEN_MAC /** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET * @@ -963,7 +964,7 @@ * * Comment this macro to disable support for Extended Master Secret. */ -#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET +//#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET /** * \def MBEDTLS_SSL_FALLBACK_SCSV @@ -980,7 +981,7 @@ * * Comment this macro to disable support for FALLBACK_SCSV */ -#define MBEDTLS_SSL_FALLBACK_SCSV +//#define MBEDTLS_SSL_FALLBACK_SCSV /** * \def MBEDTLS_SSL_HW_RECORD_ACCEL @@ -1017,7 +1018,7 @@ * * Comment this to disable support for renegotiation. */ -#define MBEDTLS_SSL_RENEGOTIATION +//#define MBEDTLS_SSL_RENEGOTIATION /** * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO @@ -1046,7 +1047,7 @@ * * Comment this macro to disable support for the max_fragment_length extension */ -#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +//#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH /** * \def MBEDTLS_SSL_PROTO_SSL3 @@ -1058,7 +1059,7 @@ * * Comment this macro to disable support for SSL 3.0 */ -#define MBEDTLS_SSL_PROTO_SSL3 +//#define MBEDTLS_SSL_PROTO_SSL3 /** * \def MBEDTLS_SSL_PROTO_TLS1 @@ -1109,7 +1110,7 @@ * * Comment this macro to disable support for DTLS */ -#define MBEDTLS_SSL_PROTO_DTLS +//#define MBEDTLS_SSL_PROTO_DTLS /** * \def MBEDTLS_SSL_ALPN @@ -1118,7 +1119,7 @@ * * Comment this macro to disable support for ALPN. */ -#define MBEDTLS_SSL_ALPN +//#define MBEDTLS_SSL_ALPN /** * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY @@ -1133,7 +1134,7 @@ * * Comment this to disable anti-replay in DTLS. */ -#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +//#define MBEDTLS_SSL_DTLS_ANTI_REPLAY /** * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY @@ -1151,7 +1152,7 @@ * * Comment this to disable support for HelloVerifyRequest. */ -#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +//#define MBEDTLS_SSL_DTLS_HELLO_VERIFY /** * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE @@ -1167,7 +1168,7 @@ * * Comment this to disable support for clients reusing the source port. */ -#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +//#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE /** * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT @@ -1178,7 +1179,7 @@ * * Requires: MBEDTLS_SSL_PROTO_DTLS */ -#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT +//#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT /** * \def MBEDTLS_SSL_SESSION_TICKETS @@ -1192,7 +1193,7 @@ * * Comment this macro to disable support for SSL session tickets */ -#define MBEDTLS_SSL_SESSION_TICKETS +//#define MBEDTLS_SSL_SESSION_TICKETS /** * \def MBEDTLS_SSL_EXPORT_KEYS @@ -1202,7 +1203,7 @@ * * Comment this macro to disable support for key export */ -#define MBEDTLS_SSL_EXPORT_KEYS +//#define MBEDTLS_SSL_EXPORT_KEYS /** * \def MBEDTLS_SSL_SERVER_NAME_INDICATION @@ -1222,7 +1223,7 @@ * * Comment this macro to disable support for truncated HMAC in SSL */ -#define MBEDTLS_SSL_TRUNCATED_HMAC +//#define MBEDTLS_SSL_TRUNCATED_HMAC /** * \def MBEDTLS_THREADING_ALT @@ -1257,7 +1258,7 @@ * * Comment this to disable run-time checking and save ROM space */ -#define MBEDTLS_VERSION_FEATURES +//#define MBEDTLS_VERSION_FEATURES /** * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3 @@ -1293,7 +1294,7 @@ * * Comment to skip keyUsage checking for both CA and leaf certificates. */ -#define MBEDTLS_X509_CHECK_KEY_USAGE +//#define MBEDTLS_X509_CHECK_KEY_USAGE /** * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE @@ -1306,7 +1307,7 @@ * * Comment to skip extendedKeyUsage checking for certificates. */ -#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE +//#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE /** * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT @@ -1316,7 +1317,7 @@ * * Comment this macro to disallow using RSASSA-PSS in certificates. */ -#define MBEDTLS_X509_RSASSA_PSS_SUPPORT +//#define MBEDTLS_X509_RSASSA_PSS_SUPPORT /** * \def MBEDTLS_ZLIB_SUPPORT @@ -1458,7 +1459,7 @@ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA */ -#define MBEDTLS_ARC4_C +//#define MBEDTLS_ARC4_C /** * \def MBEDTLS_ASN1_PARSE_C @@ -1523,7 +1524,7 @@ * * Module: library/blowfish.c */ -#define MBEDTLS_BLOWFISH_C +//#define MBEDTLS_BLOWFISH_C /** * \def MBEDTLS_CAMELLIA_C @@ -1578,7 +1579,7 @@ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 */ -#define MBEDTLS_CAMELLIA_C +//#define MBEDTLS_CAMELLIA_C /** * \def MBEDTLS_CCM_C @@ -1592,7 +1593,7 @@ * This module enables the AES-CCM ciphersuites, if other requisites are * enabled as well. */ -#define MBEDTLS_CCM_C +//#define MBEDTLS_CCM_C /** * \def MBEDTLS_CERTS_C @@ -1604,7 +1605,7 @@ * * This module is used for testing (ssl_client/server). */ -#define MBEDTLS_CERTS_C +//#define MBEDTLS_CERTS_C /** * \def MBEDTLS_CIPHER_C @@ -1644,7 +1645,7 @@ * * This module provides debugging functions. */ -#define MBEDTLS_DEBUG_C +//#define MBEDTLS_DEBUG_C /** * \def MBEDTLS_DES_C @@ -1670,7 +1671,7 @@ * * PEM_PARSE uses DES/3DES for decrypting encrypted keys. */ -#define MBEDTLS_DES_C +//#define MBEDTLS_DES_C /** * \def MBEDTLS_DHM_C @@ -1684,7 +1685,7 @@ * This module is used by the following key exchanges: * DHE-RSA, DHE-PSK */ -#define MBEDTLS_DHM_C +//#define MBEDTLS_DHM_C /** * \def MBEDTLS_ECDH_C @@ -1700,7 +1701,7 @@ * * Requires: MBEDTLS_ECP_C */ -#define MBEDTLS_ECDH_C +//#define MBEDTLS_ECDH_C /** * \def MBEDTLS_ECDSA_C @@ -1715,7 +1716,7 @@ * * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C */ -#define MBEDTLS_ECDSA_C +//#define MBEDTLS_ECDSA_C /** * \def MBEDTLS_ECJPAKE_C @@ -1748,7 +1749,7 @@ * * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED */ -#define MBEDTLS_ECP_C +//#define MBEDTLS_ECP_C /** * \def MBEDTLS_ENTROPY_C @@ -1774,7 +1775,7 @@ * * This module enables mbedtls_strerror(). */ -#define MBEDTLS_ERROR_C +//#define MBEDTLS_ERROR_C /** * \def MBEDTLS_GCM_C @@ -1788,7 +1789,7 @@ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other * requisites are enabled as well. */ -#define MBEDTLS_GCM_C +//#define MBEDTLS_GCM_C //764 Byte /** * \def MBEDTLS_HAVEGE_C @@ -1825,7 +1826,7 @@ * * Uncomment to enable the HMAC_DRBG random number geerator. */ -#define MBEDTLS_HMAC_DRBG_C +//#define MBEDTLS_HMAC_DRBG_C /** * \def MBEDTLS_MD_C @@ -1940,7 +1941,7 @@ * * This modules adds support for the VIA PadLock on x86. */ -#define MBEDTLS_PADLOCK_C +//#define MBEDTLS_PADLOCK_C /** * \def MBEDTLS_PEM_PARSE_C @@ -2032,7 +2033,7 @@ * * This module adds support for the PKCS#5 functions. */ -#define MBEDTLS_PKCS5_C +//#define MBEDTLS_PKCS5_C /** * \def MBEDTLS_PKCS11_C @@ -2063,7 +2064,7 @@ * * This module enables PKCS#12 functions. */ -#define MBEDTLS_PKCS12_C +//#define MBEDTLS_PKCS12_C /** * \def MBEDTLS_PLATFORM_C @@ -2083,7 +2084,7 @@ * * This module enables abstraction of common (libc) functions. */ -#define MBEDTLS_PLATFORM_C +//#define MBEDTLS_PLATFORM_C /** * \def MBEDTLS_RIPEMD160_C @@ -2094,7 +2095,7 @@ * Caller: library/mbedtls_md.c * */ -#define MBEDTLS_RIPEMD160_C +//#define MBEDTLS_RIPEMD160_C /** * \def MBEDTLS_RSA_C @@ -2172,7 +2173,7 @@ * * Requires: MBEDTLS_SSL_CACHE_C */ -#define MBEDTLS_SSL_CACHE_C +//#define MBEDTLS_SSL_CACHE_C /** * \def MBEDTLS_SSL_COOKIE_C @@ -2182,7 +2183,7 @@ * Module: library/ssl_cookie.c * Caller: */ -#define MBEDTLS_SSL_COOKIE_C +//#define MBEDTLS_SSL_COOKIE_C /** * \def MBEDTLS_SSL_TICKET_C @@ -2194,7 +2195,7 @@ * * Requires: MBEDTLS_CIPHER_C */ -#define MBEDTLS_SSL_TICKET_C +//#define MBEDTLS_SSL_TICKET_C /** * \def MBEDTLS_SSL_CLI_C @@ -2465,7 +2466,8 @@ //#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ /* SSL options */ -//#define MBEDTLS_SSL_MAX_CONTENT_LEN 16384 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */ +extern unsigned int max_content_len; +#define MBEDTLS_SSL_MAX_CONTENT_LEN max_content_len /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */ //#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */ //#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */ //#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ diff --git a/components/mbedtls/include/mbedtls/sha1.h b/components/mbedtls/include/mbedtls/sha1.h index 7a67c6c1f..2d85a59f7 100644 --- a/components/mbedtls/include/mbedtls/sha1.h +++ b/components/mbedtls/include/mbedtls/sha1.h @@ -106,7 +106,17 @@ void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[6 #endif #else /* MBEDTLS_SHA1_ALT */ -#include "sha1_alt.h" +#include "port/sha1_alt.h" + +typedef SHA1_CTX mbedtls_sha1_context; + +#define mbedtls_sha1_init sha1_init +#define mbedtls_sha1_starts sha1_starts +#define mbedtls_sha1_clone sha1_clone +#define mbedtls_sha1_update sha1_update +#define mbedtls_sha1_finish sha1_finish +#define mbedtls_sha1_free sha1_free +#define mbedtls_sha1_process sha1_process #endif /* MBEDTLS_SHA1_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/mbedtls/sha256.h b/components/mbedtls/include/mbedtls/sha256.h index f8041adf0..4ab444e8d 100644 --- a/components/mbedtls/include/mbedtls/sha256.h +++ b/components/mbedtls/include/mbedtls/sha256.h @@ -109,7 +109,17 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da #endif #else /* MBEDTLS_SHA256_ALT */ -#include "sha256_alt.h" +#include "port/sha256_alt.h" + +typedef SHA256_CTX mbedtls_sha256_context; + +#define mbedtls_sha256_init sha256_init +#define mbedtls_sha256_clone sha256_clone +#define mbedtls_sha256_starts sha256_starts +#define mbedtls_sha256_update sha256_update +#define mbedtls_sha256_finish sha256_finish +#define mbedtls_sha256_free sha256_free +#define mbedtls_sha256_process sha256_process #endif /* MBEDTLS_SHA256_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/mbedtls/sha512.h b/components/mbedtls/include/mbedtls/sha512.h index 627694f42..0ebc092f4 100644 --- a/components/mbedtls/include/mbedtls/sha512.h +++ b/components/mbedtls/include/mbedtls/sha512.h @@ -106,7 +106,17 @@ void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, unsigned char output[64 #endif #else /* MBEDTLS_SHA512_ALT */ -#include "sha512_alt.h" +#include "port/sha512_alt.h" + +typedef SHA512_CTX mbedtls_sha512_context; + +#define mbedtls_sha512_init sha512_init +#define mbedtls_sha512_clone sha512_clone +#define mbedtls_sha512_starts sha512_starts +#define mbedtls_sha512_update sha512_update +#define mbedtls_sha512_finish sha512_finish +#define mbedtls_sha512_free sha512_free + #endif /* MBEDTLS_SHA512_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/port/aes_alt.h b/components/mbedtls/include/port/aes_alt.h index d56c76ce4..a02f32f29 100644 --- a/components/mbedtls/include/port/aes_alt.h +++ b/components/mbedtls/include/port/aes_alt.h @@ -41,6 +41,12 @@ extern "C" { #define ERR_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ #define ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ +typedef struct{ + bool flag; + uint16 keybites; + uint8 key[32]; +}key_context, KEY_CTX; + /** * \brief AES context structure * @@ -53,7 +59,8 @@ typedef struct { int nr; /*!< number of rounds */ uint32_t *rk; /*!< AES round keys */ - uint32_t buf[68]; /*!< unaligned data */ + KEY_CTX enc; + KEY_CTX dec; }aes_context; typedef aes_context AES_CTX; diff --git a/components/mbedtls/include/port/multi_thread.h b/components/mbedtls/include/port/multi_thread.h new file mode 100644 index 000000000..6732eedde --- /dev/null +++ b/components/mbedtls/include/port/multi_thread.h @@ -0,0 +1,63 @@ +#ifndef _MULTI_THREAD_H_ +#define _MULTI_THREAD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + AES_MUTEX = 0, + BIGNUM_MUTEX, + SHA_MUTEX, + + MUTEX_MAX_NUM, +}; + +int multi_thread_init(void); + +void multi_thread_lock(unsigned int num); +void multi_thread_unlock(unsigned int num); + +void multi_thread_take(unsigned int num); +void multi_thread_give(unsigned int num); +bool multi_thread_is_used(num); + +#define MUTEX_LOCK(num) multi_thread_lock(num) +#define MUTEX_UNLOCK(num) multi_thread_unlock(num) + +#define SIG_TAKE(num) multi_thread_take(num) +#define SIG_GIVE(num) multi_thread_give(num) +#define SIG_IS_USED(num) multi_thread_is_used(num) + +#define AES_LOCK() MUTEX_LOCK(AES_MUTEX) +#define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) +#define BIGNUM_LOCK() MUTEX_LOCK(BIGNUM_MUTEX) +#define BIGNUM_UNLOCK() MUTEX_UNLOCK(BIGNUM_MUTEX) +#define SHA1_LOCK() MUTEX_LOCK(SHA_MUTEX) +#define SHA1_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) +#define SHA256_LOCK() MUTEX_LOCK(SHA_MUTEX) +#define SHA256_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) +#define SHA512_LOCK() MUTEX_LOCK(SHA_MUTEX) +#define SHA512_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) + +#define AES_TAKE() SIG_TAKE(AES_MUTEX) +#define AES_GIVE() SIG_GIVE(AES_MUTEX) +#define AES_IS_USED() SIG_IS_USED(AES_MUTEX) +#define BIGNUM_TAKE() SIG_TAKE(BIGNUM_MUTEX) +#define BIGNUM_GIVE() SIG_GIVE(BIGNUM_MUTEX) +#define BIGNUM_IS_USED() SIG_IS_USED(BIGNUM_MUTEX) +#define SHA1_TAKE() SIG_TAKE(SHA_MUTEX) +#define SHA1_GIVE() SIG_GIVE(SHA_MUTEX) +#define SHA1_IS_USED() SIG_IS_USED(SHA_MUTEX) +#define SHA256_TAKE() SIG_TAKE(SHA_MUTEX) +#define SHA256_GIVE() SIG_GIVE(SHA_MUTEX) +#define SHA256_IS_USED() SIG_IS_USED(SHA_MUTEX) +#define SHA512_TAKE() SIG_TAKE(SHA_MUTEX) +#define SHA512_GIVE() SIG_GIVE(SHA_MUTEX) +#define SHA512_IS_USED() SIG_IS_USED(SHA_MUTEX) + +#ifdef __cplusplus +} +#endif + +#endif /* multi_thread.h */ diff --git a/components/mbedtls/library/bignum.c b/components/mbedtls/library/bignum.c index 4c99e04d6..e438fdddb 100644 --- a/components/mbedtls/library/bignum.c +++ b/components/mbedtls/library/bignum.c @@ -58,6 +58,8 @@ #define mbedtls_free free #endif +#if !defined(MBEDTLS_BIGNUM_ALT) + /* Implementation that should never be optimized out by the compiler */ static void mbedtls_mpi_zeroize( mbedtls_mpi_uint *v, size_t n ) { volatile mbedtls_mpi_uint *p = v; while( n-- ) *p++ = 0; @@ -2264,6 +2266,7 @@ cleanup: } #endif /* MBEDTLS_GENPRIME */ +#endif /* MBEDTLS_BIGNUM_ALT */ #if defined(MBEDTLS_SELF_TEST) diff --git a/components/mbedtls/port/aes_alt.c b/components/mbedtls/port/aes_alt.c index 26699d82f..504a2a7db 100644 --- a/components/mbedtls/port/aes_alt.c +++ b/components/mbedtls/port/aes_alt.c @@ -30,6 +30,7 @@ #if defined(ESP_AES_C) #include +#include "multi_thread.h" /* Implementation that should never be optimized out by the compiler */ static void aes_zeroize( void *v, size_t n ) { @@ -39,7 +40,11 @@ static void aes_zeroize( void *v, size_t n ) { void aes_init( AES_CTX *ctx ) { memset( ctx, 0, sizeof( AES_CTX ) ); + + AES_LOCK(); + AES_TAKE(); ets_aes_enable(); + AES_UNLOCK(); } void aes_free( AES_CTX *ctx ) @@ -48,7 +53,12 @@ void aes_free( AES_CTX *ctx ) return; aes_zeroize( ctx, sizeof( AES_CTX ) ); - ets_aes_disable(); + + AES_LOCK(); + AES_GIVE(); + if (false == AES_IS_USED()) + ets_aes_disable(); + AES_UNLOCK(); } /* @@ -58,6 +68,7 @@ int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { enum AES_BITS keybit; + uint16 keybyte = keybits / 8; switch (keybits){ case 128: keybit = AES128; @@ -70,6 +81,12 @@ int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, break; default : return( ERR_AES_INVALID_KEY_LENGTH ); } + if (ctx->enc.flag == false){ + ctx->enc.flag = true; + ctx->enc.keybites = keybits; + memset(ctx->enc.key, 0, sizeof(ctx->enc.key)); + memcpy(ctx->enc.key, key, keybyte); + } ets_aes_setkey_enc(key, keybit); return 0; } @@ -81,6 +98,7 @@ int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { enum AES_BITS keybit; + uint16 keybyte = keybits / 8; switch (keybits){ case 128: keybit = AES128; @@ -93,11 +111,32 @@ int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, break; default : return( ERR_AES_INVALID_KEY_LENGTH ); } + if (ctx->dec.flag == false){ + ctx->dec.flag = true; + ctx->dec.keybites = keybits; + memset(ctx->dec.key, 0, sizeof(ctx->dec.key)); + memcpy(ctx->dec.key, key, keybyte); + } ets_aes_setkey_dec(key, keybit); return 0; } +static void aes_process_enable(AES_CTX *ctx, int mode) +{ + if( mode == AES_ENCRYPT ){ + aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybites); + }else{ + aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybites); + } + return; +} + +static void aes_process_disable(AES_CTX *ctx, int mode) +{ + +} + /* * AES-ECB block encryption */ @@ -155,7 +194,10 @@ int aes_crypt_cbc( AES_CTX *ctx, if( length % 16 ) return( ERR_AES_INVALID_INPUT_LENGTH ); - + + AES_LOCK(); + + aes_process_enable(ctx, mode); if( mode == AES_DECRYPT ) { while( length > 0 ) @@ -188,6 +230,10 @@ int aes_crypt_cbc( AES_CTX *ctx, length -= 16; } } + aes_process_disable(ctx, mode); + + AES_UNLOCK(); + return 0; } @@ -204,7 +250,10 @@ int aes_crypt_cfb128( AES_CTX *ctx, { int c; size_t n = *iv_off; - + + AES_LOCK(); + + aes_process_enable(ctx, mode); if( mode == AES_DECRYPT ) { while( length-- ) @@ -233,6 +282,9 @@ int aes_crypt_cfb128( AES_CTX *ctx, } *iv_off = n; + aes_process_disable(ctx, mode); + + AES_UNLOCK(); return 0; } @@ -249,7 +301,10 @@ int aes_crypt_cfb8( AES_CTX *ctx, { unsigned char c; unsigned char ov[17]; - + + AES_LOCK(); + + aes_process_enable(ctx, mode); while( length-- ) { memcpy( ov, iv, 16 ); @@ -265,6 +320,9 @@ int aes_crypt_cfb8( AES_CTX *ctx, memcpy( iv, ov + 1, 16 ); } + aes_process_disable(ctx, mode); + + AES_UNLOCK(); return 0; } @@ -283,6 +341,10 @@ int aes_crypt_ctr( AES_CTX *ctx, int c, i; size_t n = *nc_off; + AES_LOCK(); + + aes_process_enable(ctx, AES_ENCRYPT); + while( length-- ) { if( n == 0 ) { @@ -299,6 +361,10 @@ int aes_crypt_ctr( AES_CTX *ctx, } *nc_off = n; + aes_process_disable(ctx, AES_ENCRYPT); + + AES_UNLOCK(); + return 0; } diff --git a/components/mbedtls/port/bignum_alt.c b/components/mbedtls/port/bignum_alt.c index 88901671c..2da6e7169 100644 --- a/components/mbedtls/port/bignum_alt.c +++ b/components/mbedtls/port/bignum_alt.c @@ -38,6 +38,7 @@ #if defined(ESP_BIGNUM_ALT) #include #include +#include "multi_thread.h" /* Implementation that should never be optimized out by the compiler */ static void mpi_zeroize( void *v, size_t n ) { @@ -68,7 +69,10 @@ void mpi_init( mpi *X ) X->s = 1; X->n = 0; X->p = NULL; + BIGNUM_LOCK(); + BIGNUM_TAKE(); ets_bigint_enable(); + BIGNUM_UNLOCK(); } /* @@ -88,7 +92,11 @@ void mpi_free( mpi *X ) X->s = 1; X->n = 0; X->p = NULL; - ets_bigint_disable(); + BIGNUM_LOCK(); + BIGNUM_GIVE(); + if (false == BIGNUM_IS_USED()) + ets_bigint_disable(); + BIGNUM_UNLOCK(); } /* @@ -1035,12 +1043,14 @@ int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) // for( i++; j > 0; j-- ) mpi_mul_hlp( i - 1, A->p, X->p + j - 1, B->p[j - 1] ); + BIGNUM_LOCK(); if (ets_bigint_mult_prepare(A->p, B->p, n)){ ets_bigint_wait_finish(); ets_bigint_mult_getz(X->p, n); } else{ mpi_printf("Baseline multiplication failed\n"); } + BIGNUM_UNLOCK(); X->s = A->s * B->s; @@ -1406,6 +1416,7 @@ static void mpi_montmul( mpi *A, const mpi *B, const mpi *N, mpi_uint mm, n = N->n; m = ( B->n < n ) ? B->n : n; + BIGNUM_LOCK(); if (ets_bigint_montgomery_mult_prepare(N->p, B->p, d, m, n, false)) { ets_bigint_wait_finish(); @@ -1413,6 +1424,7 @@ static void mpi_montmul( mpi *A, const mpi *B, const mpi *N, mpi_uint mm, } else{ mpi_printf("Montgomery multiplication failed\n"); } + BIGNUM_UNLOCK(); } diff --git a/components/mbedtls/port/multi_thread.c b/components/mbedtls/port/multi_thread.c new file mode 100644 index 000000000..31cf1ea6d --- /dev/null +++ b/components/mbedtls/port/multi_thread.c @@ -0,0 +1,53 @@ +#include "multi_thread.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +static xSemaphoreHandle multi_thread_mutex[MUTEX_MAX_NUM]; +static int multi_thread_sig[MUTEX_MAX_NUM]; + +int multi_thread_init(void) +{ + int i; + + for (i = 0; i < MUTEX_MAX_NUM; i++) { + multi_thread_mutex[i] = xSemaphoreCreateMutex(); + if (!multi_thread_mutex[i]) { + goto failed1; + } + multi_thread_sig[i] = 0; + } + + return 0; + +failed1: + for (i--; i >= 0; i--) + vQueueDelete(multi_thread_mutex[i]); + + return -1; +} + +void multi_thread_lock(unsigned int num) +{ + xSemaphoreTake(multi_thread_mutex[num], portMAX_DELAY); +} + +void multi_thread_unlock(unsigned int num) +{ + xSemaphoreGive(multi_thread_mutex[num]); +} + +void multi_thread_take(unsigned int num) +{ + multi_thread_sig[num]++; +} + +void multi_thread_give(unsigned int num) +{ + multi_thread_sig[num]--; +} + +bool multi_thread_is_used(num) +{ + return (multi_thread_sig[num] != 0) ? true : false; +} + diff --git a/components/mbedtls/port/sha1_alt.c b/components/mbedtls/port/sha1_alt.c index 32a970704..b73d03ffa 100644 --- a/components/mbedtls/port/sha1_alt.c +++ b/components/mbedtls/port/sha1_alt.c @@ -27,6 +27,7 @@ #if defined(ESP_SHA1_C) #include +#include "multi_thread.h" /* Implementation that should never be optimized out by the compiler */ static void sha1_zeroize( void *v, size_t n ) { @@ -36,7 +37,11 @@ static void sha1_zeroize( void *v, size_t n ) { void sha1_init( SHA1_CTX *ctx ) { memset( ctx, 0, sizeof( SHA1_CTX ) ); + + SHA1_LOCK(); + SHA1_TAKE(); ets_sha_enable(); + SHA1_UNLOCK(); } void sha1_free( SHA1_CTX *ctx ) @@ -45,7 +50,12 @@ void sha1_free( SHA1_CTX *ctx ) return; sha1_zeroize( ctx, sizeof( SHA1_CTX ) ); - ets_sha_disable(); + + SHA1_LOCK(); + SHA1_GIVE(); + if (false == SHA1_IS_USED()) + ets_sha_disable(); + SHA1_UNLOCK(); } void sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) @@ -63,7 +73,10 @@ void sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) */ void sha1_starts( SHA1_CTX *ctx ) { + SHA1_LOCK(); ets_sha_init(&ctx->context); + SHA1_UNLOCK(); + ctx->context_type = SHA1; } @@ -72,6 +85,7 @@ void sha1_starts( SHA1_CTX *ctx ) */ void sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) { + SHA1_LOCK(); ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -81,6 +95,7 @@ void sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) void sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA1_UNLOCK(); } /* diff --git a/components/mbedtls/port/sha256_alt.c b/components/mbedtls/port/sha256_alt.c index 781cfa7a1..fc8769d1b 100644 --- a/components/mbedtls/port/sha256_alt.c +++ b/components/mbedtls/port/sha256_alt.c @@ -27,6 +27,7 @@ #if defined(ESP_SHA256_C) #include +#include "multi_thread.h" /* Implementation that should never be optimized out by the compiler */ static void sha256_zeroize( void *v, size_t n ) { @@ -36,7 +37,11 @@ static void sha256_zeroize( void *v, size_t n ) { void sha256_init( SHA256_CTX *ctx ) { memset( ctx, 0, sizeof( SHA256_CTX ) ); + + SHA256_LOCK(); + SHA256_TAKE(); ets_sha_enable(); + SHA256_UNLOCK(); } void sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) @@ -50,7 +55,12 @@ void sha256_free( SHA256_CTX *ctx ) return; sha256_zeroize( ctx, sizeof( SHA256_CTX ) ); - ets_sha_disable(); + + SHA256_LOCK(); + SHA256_GIVE(); + if (false == SHA256_IS_USED()) + ets_sha_disable(); + SHA256_UNLOCK(); } void sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) @@ -63,7 +73,10 @@ void sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) */ void sha256_starts( SHA256_CTX *ctx, int is224 ) { + SHA256_LOCK(); ets_sha_init(&ctx->context); + SHA256_UNLOCK(); + if( is224 == 0 ) { /* SHA-256 */ @@ -79,6 +92,7 @@ void sha256_starts( SHA256_CTX *ctx, int is224 ) */ void sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) { + SHA256_LOCK(); ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -88,6 +102,7 @@ void sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) void sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA256_UNLOCK(); } /* diff --git a/components/mbedtls/port/sha512_alt.c b/components/mbedtls/port/sha512_alt.c index 9884dd8d1..02d315681 100644 --- a/components/mbedtls/port/sha512_alt.c +++ b/components/mbedtls/port/sha512_alt.c @@ -26,6 +26,7 @@ #if defined(ESP_SHA512_C) #include +#include "multi_thread.h" /* Implementation that should never be optimized out by the compiler */ static void sha512_zeroize( void *v, size_t n ) { @@ -35,7 +36,11 @@ static void sha512_zeroize( void *v, size_t n ) { void sha512_init( SHA512_CTX *ctx ) { memset( ctx, 0, sizeof( SHA512_CTX ) ); + + SHA512_LOCK(); + SHA512_TAKE(); ets_sha_enable(); + SHA512_UNLOCK(); } void sha512_free( SHA512_CTX *ctx ) @@ -44,7 +49,12 @@ void sha512_free( SHA512_CTX *ctx ) return; sha512_zeroize( ctx, sizeof( SHA512_CTX ) ); - ets_sha_disable(); + + SHA512_LOCK(); + SHA512_GIVE(); + if (false == SHA512_IS_USED()) + ets_sha_disable(); + SHA512_UNLOCK(); } void sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) @@ -57,7 +67,9 @@ void sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) */ void sha512_starts( SHA512_CTX *ctx, int is384 ) { + SHA512_LOCK(); ets_sha_init(&ctx->context); + SHA512_UNLOCK(); if( is384 == 0 ) { /* SHA-512 */ @@ -75,6 +87,7 @@ void sha512_starts( SHA512_CTX *ctx, int is384 ) */ void sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) { + SHA512_LOCK(); ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -84,6 +97,7 @@ void sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) void sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA512_UNLOCK(); } /* From 98021903a2f8864963aa501801a3f3ff5aa169e5 Mon Sep 17 00:00:00 2001 From: liuhan Date: Mon, 8 Aug 2016 17:29:28 +0800 Subject: [PATCH 03/57] recompile crypto and bignum function --- .../{mbedtls/port/aes_alt.c => esp32/aes.c} | 74 +- .../port/bignum_alt.c => esp32/bignum.c} | 704 +++++++++--------- components/esp32/esp_thread.c | 53 ++ .../port/aes_alt.h => esp32/include/aes.h} | 40 +- .../bignum_alt.h => esp32/include/bignum.h} | 121 ++- components/esp32/include/esp_thread.h | 56 ++ components/esp32/include/sha.h | 224 ++++++ components/esp32/sha.c | 285 +++++++ components/mbedtls/Makefile | 0 components/mbedtls/include/mbedtls/aes.h | 22 +- components/mbedtls/include/mbedtls/bignum.h | 47 +- .../mbedtls/include/mbedtls/esp_config.h | 3 +- components/mbedtls/include/mbedtls/sha1.h | 12 +- components/mbedtls/include/mbedtls/sha256.h | 12 +- components/mbedtls/include/mbedtls/sha512.h | 12 +- .../mbedtls/include/port/multi_thread.h | 63 -- components/mbedtls/include/port/sha1_alt.h | 93 --- components/mbedtls/include/port/sha256_alt.h | 95 --- components/mbedtls/include/port/sha512_alt.h | 92 --- components/mbedtls/port/include/aes_alt.h | 59 ++ components/mbedtls/port/include/bignum_alt.h | 77 ++ components/mbedtls/port/include/sha1_alt.h | 34 + components/mbedtls/port/include/sha256_alt.h | 34 + components/mbedtls/port/include/sha512_alt.h | 32 + components/mbedtls/port/multi_thread.c | 53 -- components/mbedtls/port/sha1_alt.c | 117 --- components/mbedtls/port/sha256_alt.c | 122 --- components/mbedtls/port/sha512_alt.c | 117 --- 28 files changed, 1325 insertions(+), 1328 deletions(-) rename components/{mbedtls/port/aes_alt.c => esp32/aes.c} (79%) rename components/{mbedtls/port/bignum_alt.c => esp32/bignum.c} (63%) create mode 100644 components/esp32/esp_thread.c rename components/{mbedtls/include/port/aes_alt.h => esp32/include/aes.h} (89%) rename components/{mbedtls/include/port/bignum_alt.h => esp32/include/bignum.h} (86%) create mode 100644 components/esp32/include/esp_thread.h create mode 100644 components/esp32/include/sha.h create mode 100644 components/esp32/sha.c mode change 100755 => 100644 components/mbedtls/Makefile delete mode 100644 components/mbedtls/include/port/multi_thread.h delete mode 100644 components/mbedtls/include/port/sha1_alt.h delete mode 100644 components/mbedtls/include/port/sha256_alt.h delete mode 100644 components/mbedtls/include/port/sha512_alt.h create mode 100644 components/mbedtls/port/include/aes_alt.h create mode 100644 components/mbedtls/port/include/bignum_alt.h create mode 100644 components/mbedtls/port/include/sha1_alt.h create mode 100644 components/mbedtls/port/include/sha256_alt.h create mode 100644 components/mbedtls/port/include/sha512_alt.h delete mode 100644 components/mbedtls/port/multi_thread.c delete mode 100644 components/mbedtls/port/sha1_alt.c delete mode 100644 components/mbedtls/port/sha256_alt.c delete mode 100644 components/mbedtls/port/sha512_alt.c diff --git a/components/mbedtls/port/aes_alt.c b/components/esp32/aes.c similarity index 79% rename from components/mbedtls/port/aes_alt.c rename to components/esp32/aes.c index 504a2a7db..10a5025a5 100644 --- a/components/mbedtls/port/aes_alt.c +++ b/components/esp32/aes.c @@ -25,19 +25,17 @@ * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ -#include "port/aes_alt.h" - -#if defined(ESP_AES_C) +#include "aes.h" #include -#include "multi_thread.h" +#include "esp_thread.h" /* Implementation that should never be optimized out by the compiler */ -static void aes_zeroize( void *v, size_t n ) { +static void esp_aes_zeroize( void *v, size_t n ) { volatile unsigned char *p = v; while( n-- ) *p++ = 0; } -void aes_init( AES_CTX *ctx ) +void esp_aes_init( AES_CTX *ctx ) { memset( ctx, 0, sizeof( AES_CTX ) ); @@ -47,12 +45,12 @@ void aes_init( AES_CTX *ctx ) AES_UNLOCK(); } -void aes_free( AES_CTX *ctx ) +void esp_aes_free( AES_CTX *ctx ) { if( ctx == NULL ) return; - aes_zeroize( ctx, sizeof( AES_CTX ) ); + esp_aes_zeroize( ctx, sizeof( AES_CTX ) ); AES_LOCK(); AES_GIVE(); @@ -64,7 +62,7 @@ void aes_free( AES_CTX *ctx ) /* * AES key schedule (encryption) */ -int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, +int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { enum AES_BITS keybit; @@ -94,7 +92,7 @@ int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, /* * AES key schedule (decryption) */ -int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, +int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { enum AES_BITS keybit; @@ -122,17 +120,17 @@ int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, } -static void aes_process_enable(AES_CTX *ctx, int mode) +static void esp_aes_process_enable(AES_CTX *ctx, int mode) { if( mode == AES_ENCRYPT ){ - aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybites); + esp_aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybites); }else{ - aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybites); + esp_aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybites); } return; } -static void aes_process_disable(AES_CTX *ctx, int mode) +static void esp_aes_process_disable(AES_CTX *ctx, int mode) { } @@ -141,7 +139,7 @@ static void aes_process_disable(AES_CTX *ctx, int mode) * AES-ECB block encryption */ -void aes_encrypt( AES_CTX *ctx, +void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ) { @@ -154,7 +152,7 @@ void aes_encrypt( AES_CTX *ctx, * AES-ECB block decryption */ -void aes_decrypt( AES_CTX *ctx, +void esp_aes_decrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ) { @@ -166,15 +164,15 @@ void aes_decrypt( AES_CTX *ctx, /* * AES-ECB block encryption/decryption */ -int aes_crypt_ecb( AES_CTX *ctx, +int esp_aes_crypt_ecb( AES_CTX *ctx, int mode, const unsigned char input[16], unsigned char output[16] ) { if( mode == AES_ENCRYPT ) - aes_encrypt( ctx, input, output ); + esp_aes_encrypt( ctx, input, output ); else - aes_decrypt( ctx, input, output ); + esp_aes_decrypt( ctx, input, output ); return 0; } @@ -182,7 +180,7 @@ int aes_crypt_ecb( AES_CTX *ctx, /* * AES-CBC buffer encryption/decryption */ -int aes_crypt_cbc( AES_CTX *ctx, +int esp_aes_crypt_cbc( AES_CTX *ctx, int mode, size_t length, unsigned char iv[16], @@ -197,13 +195,13 @@ int aes_crypt_cbc( AES_CTX *ctx, AES_LOCK(); - aes_process_enable(ctx, mode); + esp_aes_process_enable(ctx, mode); if( mode == AES_DECRYPT ) { while( length > 0 ) { memcpy( temp, input, 16 ); - aes_crypt_ecb( ctx, mode, input, output ); + esp_aes_crypt_ecb( ctx, mode, input, output ); for( i = 0; i < 16; i++ ) output[i] = (unsigned char)( output[i] ^ iv[i] ); @@ -222,7 +220,7 @@ int aes_crypt_cbc( AES_CTX *ctx, for( i = 0; i < 16; i++ ) output[i] = (unsigned char)( input[i] ^ iv[i] ); - aes_crypt_ecb( ctx, mode, output, output ); + esp_aes_crypt_ecb( ctx, mode, output, output ); memcpy( iv, output, 16 ); input += 16; @@ -230,7 +228,7 @@ int aes_crypt_cbc( AES_CTX *ctx, length -= 16; } } - aes_process_disable(ctx, mode); + esp_aes_process_disable(ctx, mode); AES_UNLOCK(); @@ -240,7 +238,7 @@ int aes_crypt_cbc( AES_CTX *ctx, /* * AES-CFB128 buffer encryption/decryption */ -int aes_crypt_cfb128( AES_CTX *ctx, +int esp_aes_crypt_cfb128( AES_CTX *ctx, int mode, size_t length, size_t *iv_off, @@ -253,13 +251,13 @@ int aes_crypt_cfb128( AES_CTX *ctx, AES_LOCK(); - aes_process_enable(ctx, mode); + esp_aes_process_enable(ctx, mode); if( mode == AES_DECRYPT ) { while( length-- ) { if( n == 0 ) - aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); c = *input++; *output++ = (unsigned char)( c ^ iv[n] ); @@ -273,7 +271,7 @@ int aes_crypt_cfb128( AES_CTX *ctx, while( length-- ) { if( n == 0 ) - aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); @@ -282,7 +280,7 @@ int aes_crypt_cfb128( AES_CTX *ctx, } *iv_off = n; - aes_process_disable(ctx, mode); + esp_aes_process_disable(ctx, mode); AES_UNLOCK(); @@ -292,7 +290,7 @@ int aes_crypt_cfb128( AES_CTX *ctx, /* * AES-CFB8 buffer encryption/decryption */ -int aes_crypt_cfb8( AES_CTX *ctx, +int esp_aes_crypt_cfb8( AES_CTX *ctx, int mode, size_t length, unsigned char iv[16], @@ -304,11 +302,11 @@ int aes_crypt_cfb8( AES_CTX *ctx, AES_LOCK(); - aes_process_enable(ctx, mode); + esp_aes_process_enable(ctx, mode); while( length-- ) { memcpy( ov, iv, 16 ); - aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); if( mode == AES_DECRYPT ) ov[16] = *input; @@ -320,7 +318,7 @@ int aes_crypt_cfb8( AES_CTX *ctx, memcpy( iv, ov + 1, 16 ); } - aes_process_disable(ctx, mode); + esp_aes_process_disable(ctx, mode); AES_UNLOCK(); @@ -330,7 +328,7 @@ int aes_crypt_cfb8( AES_CTX *ctx, /* * AES-CTR buffer encryption/decryption */ -int aes_crypt_ctr( AES_CTX *ctx, +int esp_aes_crypt_ctr( AES_CTX *ctx, size_t length, size_t *nc_off, unsigned char nonce_counter[16], @@ -343,12 +341,12 @@ int aes_crypt_ctr( AES_CTX *ctx, AES_LOCK(); - aes_process_enable(ctx, AES_ENCRYPT); + esp_aes_process_enable(ctx, AES_ENCRYPT); while( length-- ) { if( n == 0 ) { - aes_crypt_ecb( ctx, AES_ENCRYPT, nonce_counter, stream_block ); + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, nonce_counter, stream_block ); for( i = 16; i > 0; i-- ) if( ++nonce_counter[i - 1] != 0 ) @@ -361,12 +359,10 @@ int aes_crypt_ctr( AES_CTX *ctx, } *nc_off = n; - aes_process_disable(ctx, AES_ENCRYPT); + esp_aes_process_disable(ctx, AES_ENCRYPT); AES_UNLOCK(); return 0; } -#endif /* AES_ALT_C */ - diff --git a/components/mbedtls/port/bignum_alt.c b/components/esp32/bignum.c similarity index 63% rename from components/mbedtls/port/bignum_alt.c rename to components/esp32/bignum.c index 2da6e7169..02d5a9c3d 100644 --- a/components/mbedtls/port/bignum_alt.c +++ b/components/esp32/bignum.c @@ -33,19 +33,19 @@ * https://gmplib.org/manual/index.html * */ -#include "port/bignum_alt.h" +#include "bignum.h" #if defined(ESP_BIGNUM_ALT) #include #include -#include "multi_thread.h" +#include "esp_thread.h" /* Implementation that should never be optimized out by the compiler */ -static void mpi_zeroize( void *v, size_t n ) { +static void esp_mpi_zeroize( void *v, size_t n ) { volatile unsigned char *p = v; while( n-- ) *p++ = 0; } -#define ciL (sizeof(mpi_uint)) /* chars in limb */ +#define ciL (sizeof(esp_mpi_uint)) /* chars in limb */ #define biL (ciL << 3) /* bits in limb */ #define biH (ciL << 2) /* half limb size */ @@ -61,7 +61,7 @@ static void mpi_zeroize( void *v, size_t n ) { /* * Initialize one MPI */ -void mpi_init( mpi *X ) +void esp_mpi_init( mpi *X ) { if( X == NULL ) return; @@ -78,14 +78,14 @@ void mpi_init( mpi *X ) /* * Unallocate one MPI */ -void mpi_free( mpi *X ) +void esp_mpi_free( mpi *X ) { if( X == NULL ) return; if( X->p != NULL ) { - mpi_zeroize( X->p, X->n * ciL ); + esp_mpi_zeroize( X->p, X->n * ciL ); free( X->p ); } @@ -102,9 +102,9 @@ void mpi_free( mpi *X ) /* * Enlarge to the specified number of limbs */ -int mpi_grow( mpi *X, size_t nblimbs ) +int esp_mpi_grow( mpi *X, size_t nblimbs ) { - mpi_uint *p; + esp_mpi_uint *p; if( nblimbs > MPI_MAX_LIMBS ) return( ERR_MPI_ALLOC_FAILED ); @@ -117,7 +117,7 @@ int mpi_grow( mpi *X, size_t nblimbs ) if( X->p != NULL ) { memcpy( p, X->p, X->n * ciL ); - mpi_zeroize( X->p, X->n * ciL ); + esp_mpi_zeroize( X->p, X->n * ciL ); free( X->p ); } @@ -132,14 +132,14 @@ int mpi_grow( mpi *X, size_t nblimbs ) * Resize down as much as possible, * while keeping at least the specified number of limbs */ -int mpi_shrink( mpi *X, size_t nblimbs ) +int esp_mpi_shrink( mpi *X, size_t nblimbs ) { - mpi_uint *p; + esp_mpi_uint *p; size_t i; /* Actually resize up in this case */ if( X->n <= nblimbs ) - return( mpi_grow( X, nblimbs ) ); + return( esp_mpi_grow( X, nblimbs ) ); for( i = X->n - 1; i > 0; i-- ) if( X->p[i] != 0 ) @@ -155,7 +155,7 @@ int mpi_shrink( mpi *X, size_t nblimbs ) if( X->p != NULL ) { memcpy( p, X->p, i * ciL ); - mpi_zeroize( X->p, X->n * ciL ); + esp_mpi_zeroize( X->p, X->n * ciL ); free( X->p ); } @@ -168,7 +168,7 @@ int mpi_shrink( mpi *X, size_t nblimbs ) /* * Copy the contents of Y into X */ -int mpi_copy( mpi *X, const mpi *Y ) +int esp_mpi_copy( mpi *X, const mpi *Y ) { int ret; size_t i; @@ -178,7 +178,7 @@ int mpi_copy( mpi *X, const mpi *Y ) if( Y->p == NULL ) { - mpi_free( X ); + esp_mpi_free( X ); return( 0 ); } @@ -189,7 +189,7 @@ int mpi_copy( mpi *X, const mpi *Y ) X->s = Y->s; - MPI_CHK( mpi_grow( X, i ) ); + MPI_CHK( esp_mpi_grow( X, i ) ); memset( X->p, 0, X->n * ciL ); memcpy( X->p, Y->p, i * ciL ); @@ -202,7 +202,7 @@ cleanup: /* * Swap the contents of X and Y */ -void mpi_swap( mpi *X, mpi *Y ) +void esp_mpi_swap( mpi *X, mpi *Y ) { mpi T; @@ -216,7 +216,7 @@ void mpi_swap( mpi *X, mpi *Y ) * about whether the assignment was made or not. * (Leaking information about the respective sizes of X and Y is ok however.) */ -int mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ) +int esp_mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ) { int ret = 0; size_t i; @@ -224,7 +224,7 @@ int mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ) /* make sure assign is 0 or 1 in a time-constant manner */ assign = (assign | (unsigned char)-assign) >> 7; - MPI_CHK( mpi_grow( X, Y->n ) ); + MPI_CHK( esp_mpi_grow( X, Y->n ) ); X->s = X->s * ( 1 - assign ) + Y->s * assign; @@ -244,11 +244,11 @@ cleanup: * Here it is not ok to simply swap the pointers, which whould lead to * different memory access patterns when X and Y are used afterwards. */ -int mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char swap ) +int esp_mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char swap ) { int ret, s; size_t i; - mpi_uint tmp; + esp_mpi_uint tmp; if( X == Y ) return( 0 ); @@ -256,8 +256,8 @@ int mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char swap ) /* make sure swap is 0 or 1 in a time-constant manner */ swap = (swap | (unsigned char)-swap) >> 7; - MPI_CHK( mpi_grow( X, Y->n ) ); - MPI_CHK( mpi_grow( Y, X->n ) ); + MPI_CHK( esp_mpi_grow( X, Y->n ) ); + MPI_CHK( esp_mpi_grow( Y, X->n ) ); s = X->s; X->s = X->s * ( 1 - swap ) + Y->s * swap; @@ -278,11 +278,11 @@ cleanup: /* * Set value from integer */ -int mpi_lset( mpi *X, mpi_sint z ) +int esp_mpi_lset( mpi *X, esp_mpi_sint z ) { int ret; - MPI_CHK( mpi_grow( X, 1 ) ); + MPI_CHK( esp_mpi_grow( X, 1 ) ); memset( X->p, 0, X->n * ciL ); X->p[0] = ( z < 0 ) ? -z : z; @@ -296,7 +296,7 @@ cleanup: /* * Get a specific bit */ -int mpi_get_bit( const mpi *X, size_t pos ) +int esp_mpi_get_bit( const mpi *X, size_t pos ) { if( X->n * biL <= pos ) return( 0 ); @@ -307,7 +307,7 @@ int mpi_get_bit( const mpi *X, size_t pos ) /* * Set a bit to a specific value of 0 or 1 */ -int mpi_set_bit( mpi *X, size_t pos, unsigned char val ) +int esp_mpi_set_bit( mpi *X, size_t pos, unsigned char val ) { int ret = 0; size_t off = pos / biL; @@ -321,11 +321,11 @@ int mpi_set_bit( mpi *X, size_t pos, unsigned char val ) if( val == 0 ) return( 0 ); - MPI_CHK( mpi_grow( X, off + 1 ) ); + MPI_CHK( esp_mpi_grow( X, off + 1 ) ); } - X->p[off] &= ~( (mpi_uint) 0x01 << idx ); - X->p[off] |= (mpi_uint) val << idx; + X->p[off] &= ~( (esp_mpi_uint) 0x01 << idx ); + X->p[off] |= (esp_mpi_uint) val << idx; cleanup: @@ -335,7 +335,7 @@ cleanup: /* * Return the number of less significant zero-bits */ -size_t mpi_lsb( const mpi *X ) +size_t esp_mpi_lsb( const mpi *X ) { size_t i, j, count = 0; @@ -350,10 +350,10 @@ size_t mpi_lsb( const mpi *X ) /* * Count leading zero bits in a given integer */ -static size_t clz( const mpi_uint x ) +static size_t clz( const esp_mpi_uint x ) { size_t j; - mpi_uint mask = (mpi_uint) 1 << (biL - 1); + esp_mpi_uint mask = (esp_mpi_uint) 1 << (biL - 1); for( j = 0; j < biL; j++ ) { @@ -368,7 +368,7 @@ static size_t clz( const mpi_uint x ) /* * Return the number of bits */ -size_t mpi_bitlen( const mpi *X ) +size_t esp_mpi_bitlen( const mpi *X ) { size_t i, j; @@ -387,15 +387,15 @@ size_t mpi_bitlen( const mpi *X ) /* * Return the total size in bytes */ -size_t mpi_size( const mpi *X ) +size_t esp_mpi_size( const mpi *X ) { - return( ( mpi_bitlen( X ) + 7 ) >> 3 ); + return( ( esp_mpi_bitlen( X ) + 7 ) >> 3 ); } /* * Convert an ASCII character to digit value */ -static int mpi_get_digit( mpi_uint *d, int radix, char c ) +static int esp_mpi_get_digit( esp_mpi_uint *d, int radix, char c ) { *d = 255; @@ -403,7 +403,7 @@ static int mpi_get_digit( mpi_uint *d, int radix, char c ) if( c >= 0x41 && c <= 0x46 ) *d = c - 0x37; if( c >= 0x61 && c <= 0x66 ) *d = c - 0x57; - if( *d >= (mpi_uint) radix ) + if( *d >= (esp_mpi_uint) radix ) return( ERR_MPI_INVALID_CHARACTER ); return( 0 ); @@ -412,17 +412,17 @@ static int mpi_get_digit( mpi_uint *d, int radix, char c ) /* * Import from an ASCII string */ -int mpi_read_string( mpi *X, int radix, const char *s ) +int esp_mpi_read_string( mpi *X, int radix, const char *s ) { int ret; size_t i, j, slen, n; - mpi_uint d; + esp_mpi_uint d; mpi T; if( radix < 2 || radix > 16 ) return( ERR_MPI_BAD_INPUT_DATA ); - mpi_init( &T ); + esp_mpi_init( &T ); slen = strlen( s ); @@ -433,8 +433,8 @@ int mpi_read_string( mpi *X, int radix, const char *s ) n = BITS_TO_LIMBS( slen << 2 ); - MPI_CHK( mpi_grow( X, n ) ); - MPI_CHK( mpi_lset( X, 0 ) ); + MPI_CHK( esp_mpi_grow( X, n ) ); + MPI_CHK( esp_mpi_lset( X, 0 ) ); for( i = slen, j = 0; i > 0; i--, j++ ) { @@ -444,13 +444,13 @@ int mpi_read_string( mpi *X, int radix, const char *s ) break; } - MPI_CHK( mpi_get_digit( &d, radix, s[i - 1] ) ); + MPI_CHK( esp_mpi_get_digit( &d, radix, s[i - 1] ) ); X->p[j / ( 2 * ciL )] |= d << ( ( j % ( 2 * ciL ) ) << 2 ); } } else { - MPI_CHK( mpi_lset( X, 0 ) ); + MPI_CHK( esp_mpi_lset( X, 0 ) ); for( i = 0; i < slen; i++ ) { @@ -460,23 +460,23 @@ int mpi_read_string( mpi *X, int radix, const char *s ) continue; } - MPI_CHK( mpi_get_digit( &d, radix, s[i] ) ); - MPI_CHK( mpi_mul_int( &T, X, radix ) ); + MPI_CHK( esp_mpi_get_digit( &d, radix, s[i] ) ); + MPI_CHK( esp_mpi_mul_int( &T, X, radix ) ); if( X->s == 1 ) { - MPI_CHK( mpi_add_int( X, &T, d ) ); + MPI_CHK( esp_mpi_add_int( X, &T, d ) ); } else { - MPI_CHK( mpi_sub_int( X, &T, d ) ); + MPI_CHK( esp_mpi_sub_int( X, &T, d ) ); } } } cleanup: - mpi_free( &T ); + esp_mpi_free( &T ); return( ret ); } @@ -484,19 +484,19 @@ cleanup: /* * Helper to write the digits high-order first */ -static int mpi_write_hlp( mpi *X, int radix, char **p ) +static int esp_mpi_write_hlp( mpi *X, int radix, char **p ) { int ret; - mpi_uint r; + esp_mpi_uint r; if( radix < 2 || radix > 16 ) return( ERR_MPI_BAD_INPUT_DATA ); - MPI_CHK( mpi_mod_int( &r, X, radix ) ); - MPI_CHK( mpi_div_int( X, NULL, X, radix ) ); + MPI_CHK( esp_mpi_mod_int( &r, X, radix ) ); + MPI_CHK( esp_mpi_div_int( X, NULL, X, radix ) ); - if( mpi_cmp_int( X, 0 ) != 0 ) - MPI_CHK( mpi_write_hlp( X, radix, p ) ); + if( esp_mpi_cmp_int( X, 0 ) != 0 ) + MPI_CHK( esp_mpi_write_hlp( X, radix, p ) ); if( r < 10 ) *(*p)++ = (char)( r + 0x30 ); @@ -511,7 +511,7 @@ cleanup: /* * Export into an ASCII string */ -int mpi_write_string( const mpi *X, int radix, +int esp_mpi_write_string( const mpi *X, int radix, char *buf, size_t buflen, size_t *olen ) { int ret = 0; @@ -522,7 +522,7 @@ int mpi_write_string( const mpi *X, int radix, if( radix < 2 || radix > 16 ) return( ERR_MPI_BAD_INPUT_DATA ); - n = mpi_bitlen( X ); + n = esp_mpi_bitlen( X ); if( radix >= 4 ) n >>= 1; if( radix >= 16 ) n >>= 1; n += 3; @@ -534,7 +534,7 @@ int mpi_write_string( const mpi *X, int radix, } p = buf; - mpi_init( &T ); + esp_mpi_init( &T ); if( X->s == -1 ) *p++ = '-'; @@ -561,12 +561,12 @@ int mpi_write_string( const mpi *X, int radix, } else { - MPI_CHK( mpi_copy( &T, X ) ); + MPI_CHK( esp_mpi_copy( &T, X ) ); if( T.s == -1 ) T.s = 1; - MPI_CHK( mpi_write_hlp( &T, radix, &p ) ); + MPI_CHK( esp_mpi_write_hlp( &T, radix, &p ) ); } *p++ = '\0'; @@ -574,7 +574,7 @@ int mpi_write_string( const mpi *X, int radix, cleanup: - mpi_free( &T ); + esp_mpi_free( &T ); return( ret ); } @@ -582,7 +582,7 @@ cleanup: /* * Import X from unsigned binary data, big endian */ -int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ) +int esp_mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ) { int ret; size_t i, j, n; @@ -591,11 +591,11 @@ int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ) if( buf[n] != 0 ) break; - MPI_CHK( mpi_grow( X, CHARS_TO_LIMBS( buflen - n ) ) ); - MPI_CHK( mpi_lset( X, 0 ) ); + MPI_CHK( esp_mpi_grow( X, CHARS_TO_LIMBS( buflen - n ) ) ); + MPI_CHK( esp_mpi_lset( X, 0 ) ); for( i = buflen, j = 0; i > n; i--, j++ ) - X->p[j / ciL] |= ((mpi_uint) buf[i - 1]) << ((j % ciL) << 3); + X->p[j / ciL] |= ((esp_mpi_uint) buf[i - 1]) << ((j % ciL) << 3); cleanup: @@ -605,11 +605,11 @@ cleanup: /* * Export X into unsigned binary data, big endian */ -int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ) +int esp_mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ) { size_t i, j, n; - n = mpi_size( X ); + n = esp_mpi_size( X ); if( buflen < n ) return( ERR_MPI_BUFFER_TOO_SMALL ); @@ -625,19 +625,19 @@ int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ) /* * Left-shift: X <<= count */ -int mpi_shift_l( mpi *X, size_t count ) +int esp_mpi_shift_l( mpi *X, size_t count ) { int ret; size_t i, v0, t1; - mpi_uint r0 = 0, r1; + esp_mpi_uint r0 = 0, r1; v0 = count / (biL ); t1 = count & (biL - 1); - i = mpi_bitlen( X ) + count; + i = esp_mpi_bitlen( X ) + count; if( X->n * biL < i ) - MPI_CHK( mpi_grow( X, BITS_TO_LIMBS( i ) ) ); + MPI_CHK( esp_mpi_grow( X, BITS_TO_LIMBS( i ) ) ); ret = 0; @@ -675,16 +675,16 @@ cleanup: /* * Right-shift: X >>= count */ -int mpi_shift_r( mpi *X, size_t count ) +int esp_mpi_shift_r( mpi *X, size_t count ) { size_t i, v0, v1; - mpi_uint r0 = 0, r1; + esp_mpi_uint r0 = 0, r1; v0 = count / biL; v1 = count & (biL - 1); if( v0 > X->n || ( v0 == X->n && v1 > 0 ) ) - return mpi_lset( X, 0 ); + return esp_mpi_lset( X, 0 ); /* * shift by count / limb_size @@ -718,7 +718,7 @@ int mpi_shift_r( mpi *X, size_t count ) /* * Compare unsigned values */ -int mpi_cmp_abs( const mpi *X, const mpi *Y ) +int esp_mpi_cmp_abs( const mpi *X, const mpi *Y ) { size_t i, j; @@ -748,7 +748,7 @@ int mpi_cmp_abs( const mpi *X, const mpi *Y ) /* * Compare signed values */ -int mpi_cmp_mpi( const mpi *X, const mpi *Y ) +int esp_mpi_cmp_mpi( const mpi *X, const mpi *Y ) { size_t i, j; @@ -781,27 +781,27 @@ int mpi_cmp_mpi( const mpi *X, const mpi *Y ) /* * Compare signed values */ -int mpi_cmp_int( const mpi *X, mpi_sint z ) +int esp_mpi_cmp_int( const mpi *X, esp_mpi_sint z ) { mpi Y; - mpi_uint p[1]; + esp_mpi_uint p[1]; *p = ( z < 0 ) ? -z : z; Y.s = ( z < 0 ) ? -1 : 1; Y.n = 1; Y.p = p; - return( mpi_cmp_mpi( X, &Y ) ); + return( esp_mpi_cmp_mpi( X, &Y ) ); } /* * Unsigned addition: X = |A| + |B| (HAC 14.7) */ -int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) +int esp_mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) { int ret; size_t i, j; - mpi_uint *o, *p, c; + esp_mpi_uint *o, *p, c; if( X == B ) { @@ -809,7 +809,7 @@ int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) } if( X != A ) - MPI_CHK( mpi_copy( X, A ) ); + MPI_CHK( esp_mpi_copy( X, A ) ); /* * X should always be positive as a result of unsigned additions. @@ -820,7 +820,7 @@ int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) if( B->p[j - 1] != 0 ) break; - MPI_CHK( mpi_grow( X, j ) ); + MPI_CHK( esp_mpi_grow( X, j ) ); o = B->p; p = X->p; c = 0; @@ -834,7 +834,7 @@ int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) { if( i >= X->n ) { - MPI_CHK( mpi_grow( X, i + 1 ) ); + MPI_CHK( esp_mpi_grow( X, i + 1 ) ); p = X->p + i; } @@ -849,10 +849,10 @@ cleanup: /* * Helper for mpi subtraction */ -static void mpi_sub_hlp( size_t n, mpi_uint *s, mpi_uint *d ) +static void esp_mpi_sub_hlp( size_t n, esp_mpi_uint *s, esp_mpi_uint *d ) { size_t i; - mpi_uint c, z; + esp_mpi_uint c, z; for( i = c = 0; i < n; i++, s++, d++ ) { @@ -870,25 +870,25 @@ static void mpi_sub_hlp( size_t n, mpi_uint *s, mpi_uint *d ) /* * Unsigned subtraction: X = |A| - |B| (HAC 14.9) */ -int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ) +int esp_mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ) { mpi TB; int ret; size_t n; - if( mpi_cmp_abs( A, B ) < 0 ) + if( esp_mpi_cmp_abs( A, B ) < 0 ) return( ERR_MPI_NEGATIVE_VALUE ); - mpi_init( &TB ); + esp_mpi_init( &TB ); if( X == B ) { - MPI_CHK( mpi_copy( &TB, B ) ); + MPI_CHK( esp_mpi_copy( &TB, B ) ); B = &TB; } if( X != A ) - MPI_CHK( mpi_copy( X, A ) ); + MPI_CHK( esp_mpi_copy( X, A ) ); /* * X should always be positive as a result of unsigned subtractions. @@ -901,11 +901,11 @@ int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ) if( B->p[n - 1] != 0 ) break; - mpi_sub_hlp( n, B->p, X->p ); + esp_mpi_sub_hlp( n, B->p, X->p ); cleanup: - mpi_free( &TB ); + esp_mpi_free( &TB ); return( ret ); } @@ -913,26 +913,26 @@ cleanup: /* * Signed addition: X = A + B */ -int mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ) +int esp_mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ) { int ret, s = A->s; if( A->s * B->s < 0 ) { - if( mpi_cmp_abs( A, B ) >= 0 ) + if( esp_mpi_cmp_abs( A, B ) >= 0 ) { - MPI_CHK( mpi_sub_abs( X, A, B ) ); + MPI_CHK( esp_mpi_sub_abs( X, A, B ) ); X->s = s; } else { - MPI_CHK( mpi_sub_abs( X, B, A ) ); + MPI_CHK( esp_mpi_sub_abs( X, B, A ) ); X->s = -s; } } else { - MPI_CHK( mpi_add_abs( X, A, B ) ); + MPI_CHK( esp_mpi_add_abs( X, A, B ) ); X->s = s; } @@ -944,26 +944,26 @@ cleanup: /* * Signed subtraction: X = A - B */ -int mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ) +int esp_mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ) { int ret, s = A->s; if( A->s * B->s > 0 ) { - if( mpi_cmp_abs( A, B ) >= 0 ) + if( esp_mpi_cmp_abs( A, B ) >= 0 ) { - MPI_CHK( mpi_sub_abs( X, A, B ) ); + MPI_CHK( esp_mpi_sub_abs( X, A, B ) ); X->s = s; } else { - MPI_CHK( mpi_sub_abs( X, B, A ) ); + MPI_CHK( esp_mpi_sub_abs( X, B, A ) ); X->s = -s; } } else { - MPI_CHK( mpi_add_abs( X, A, B ) ); + MPI_CHK( esp_mpi_add_abs( X, A, B ) ); X->s = s; } @@ -975,39 +975,39 @@ cleanup: /* * Signed addition: X = A + b */ -int mpi_add_int( mpi *X, const mpi *A, mpi_sint b ) +int esp_mpi_add_int( mpi *X, const mpi *A, esp_mpi_sint b ) { mpi _B; - mpi_uint p[1]; + esp_mpi_uint p[1]; p[0] = ( b < 0 ) ? -b : b; _B.s = ( b < 0 ) ? -1 : 1; _B.n = 1; _B.p = p; - return( mpi_add_mpi( X, A, &_B ) ); + return( esp_mpi_add_mpi( X, A, &_B ) ); } /* * Signed subtraction: X = A - b */ -int mpi_sub_int( mpi *X, const mpi *A, mpi_sint b ) +int esp_mpi_sub_int( mpi *X, const mpi *A, esp_mpi_sint b ) { mpi _B; - mpi_uint p[1]; + esp_mpi_uint p[1]; p[0] = ( b < 0 ) ? -b : b; _B.s = ( b < 0 ) ? -1 : 1; _B.n = 1; _B.p = p; - return( mpi_sub_mpi( X, A, &_B ) ); + return( esp_mpi_sub_mpi( X, A, &_B ) ); } /* * Helper for mpi multiplication */ -static void mpi_mul_hlp( size_t i, mpi_uint *s, mpi_uint *d, mpi_uint b ) +static void esp_mpi_mul_hlp( size_t i, esp_mpi_uint *s, esp_mpi_uint *d, esp_mpi_uint b ) { } @@ -1015,7 +1015,7 @@ static void mpi_mul_hlp( size_t i, mpi_uint *s, mpi_uint *d, mpi_uint b ) /* * Baseline multiplication: X = A * B (HAC 14.12) */ -int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) +int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) { int ret; size_t i, j; @@ -1023,10 +1023,10 @@ int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) mpi TA, TB; - mpi_init( &TA ); mpi_init( &TB ); + esp_mpi_init( &TA ); esp_mpi_init( &TB ); - if( X == A ) { MPI_CHK( mpi_copy( &TA, A ) ); A = &TA; } - if( X == B ) { MPI_CHK( mpi_copy( &TB, B ) ); B = &TB; } + if( X == A ) { MPI_CHK( esp_mpi_copy( &TA, A ) ); A = &TA; } + if( X == B ) { MPI_CHK( esp_mpi_copy( &TB, B ) ); B = &TB; } for( i = A->n; i > 0; i-- ) if( A->p[i - 1] != 0 ) @@ -1036,19 +1036,19 @@ int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) if( B->p[j - 1] != 0 ) break; - MPI_CHK( mpi_grow( X, i + j ) ); - MPI_CHK( mpi_lset( X, 0 ) ); + MPI_CHK( esp_mpi_grow( X, i + j ) ); + MPI_CHK( esp_mpi_lset( X, 0 ) ); n = j; // for( i++; j > 0; j-- ) - mpi_mul_hlp( i - 1, A->p, X->p + j - 1, B->p[j - 1] ); + esp_mpi_mul_hlp( i - 1, A->p, X->p + j - 1, B->p[j - 1] ); BIGNUM_LOCK(); if (ets_bigint_mult_prepare(A->p, B->p, n)){ ets_bigint_wait_finish(); ets_bigint_mult_getz(X->p, n); } else{ - mpi_printf("Baseline multiplication failed\n"); + esp_mpi_printf("Baseline multiplication failed\n"); } BIGNUM_UNLOCK(); @@ -1056,7 +1056,7 @@ int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) cleanup: - mpi_free( &TB ); mpi_free( &TA ); + esp_mpi_free( &TB ); esp_mpi_free( &TA ); return( ret ); } @@ -1064,33 +1064,33 @@ cleanup: /* * Baseline multiplication: X = A * b */ -int mpi_mul_int( mpi *X, const mpi *A, mpi_uint b ) +int esp_mpi_mul_int( mpi *X, const mpi *A, esp_mpi_uint b ) { mpi _B; - mpi_uint p[1]; + esp_mpi_uint p[1]; _B.s = 1; _B.n = 1; _B.p = p; p[0] = b; - return( mpi_mul_mpi( X, A, &_B ) ); + return( esp_mpi_mul_mpi( X, A, &_B ) ); } /* - * Unsigned integer divide - double mpi_uint dividend, u1/u0, and - * mpi_uint divisor, d + * Unsigned integer divide - double esp_mpi_uint dividend, u1/u0, and + * esp_mpi_uint divisor, d */ -static mpi_uint int_div_int( mpi_uint u1, - mpi_uint u0, mpi_uint d, mpi_uint *r ) +static esp_mpi_uint int_div_int( esp_mpi_uint u1, + esp_mpi_uint u0, esp_mpi_uint d, esp_mpi_uint *r ) { #if defined(HAVE_UDBL) t_udbl dividend, quotient; #else - const mpi_uint radix = (mpi_uint) 1 << biH; - const mpi_uint uint_halfword_mask = ( (mpi_uint) 1 << biH ) - 1; - mpi_uint d0, d1, q0, q1, rAX, r0, quotient; - mpi_uint u0_msw, u0_lsw; + const esp_mpi_uint radix = (esp_mpi_uint) 1 << biH; + const esp_mpi_uint uint_halfword_mask = ( (esp_mpi_uint) 1 << biH ) - 1; + esp_mpi_uint d0, d1, q0, q1, rAX, r0, quotient; + esp_mpi_uint u0_msw, u0_lsw; size_t s; #endif @@ -1112,9 +1112,9 @@ static mpi_uint int_div_int( mpi_uint u1, quotient = ( (t_udbl) 1 << biL ) - 1; if( r != NULL ) - *r = (mpi_uint)( dividend - (quotient * d ) ); + *r = (esp_mpi_uint)( dividend - (quotient * d ) ); - return (mpi_uint) quotient; + return (esp_mpi_uint) quotient; #else /* @@ -1129,7 +1129,7 @@ static mpi_uint int_div_int( mpi_uint u1, d = d << s; u1 = u1 << s; - u1 |= ( u0 >> ( biL - s ) ) & ( -(mpi_sint)s >> ( biL - 1 ) ); + u1 |= ( u0 >> ( biL - s ) ) & ( -(esp_mpi_sint)s >> ( biL - 1 ) ); u0 = u0 << s; d1 = d >> biH; @@ -1176,53 +1176,53 @@ static mpi_uint int_div_int( mpi_uint u1, /* * Division by mpi: A = Q * B + R (HAC 14.20) */ -int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ) +int esp_mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ) { int ret; size_t i, n, t, k; mpi X, Y, Z, T1, T2; - if( mpi_cmp_int( B, 0 ) == 0 ) + if( esp_mpi_cmp_int( B, 0 ) == 0 ) return( ERR_MPI_DIVISION_BY_ZERO ); - mpi_init( &X ); mpi_init( &Y ); mpi_init( &Z ); - mpi_init( &T1 ); mpi_init( &T2 ); + esp_mpi_init( &X ); esp_mpi_init( &Y ); esp_mpi_init( &Z ); + esp_mpi_init( &T1 ); esp_mpi_init( &T2 ); - if( mpi_cmp_abs( A, B ) < 0 ) + if( esp_mpi_cmp_abs( A, B ) < 0 ) { - if( Q != NULL ) MPI_CHK( mpi_lset( Q, 0 ) ); - if( R != NULL ) MPI_CHK( mpi_copy( R, A ) ); + if( Q != NULL ) MPI_CHK( esp_mpi_lset( Q, 0 ) ); + if( R != NULL ) MPI_CHK( esp_mpi_copy( R, A ) ); return( 0 ); } - MPI_CHK( mpi_copy( &X, A ) ); - MPI_CHK( mpi_copy( &Y, B ) ); + MPI_CHK( esp_mpi_copy( &X, A ) ); + MPI_CHK( esp_mpi_copy( &Y, B ) ); X.s = Y.s = 1; - MPI_CHK( mpi_grow( &Z, A->n + 2 ) ); - MPI_CHK( mpi_lset( &Z, 0 ) ); - MPI_CHK( mpi_grow( &T1, 2 ) ); - MPI_CHK( mpi_grow( &T2, 3 ) ); + MPI_CHK( esp_mpi_grow( &Z, A->n + 2 ) ); + MPI_CHK( esp_mpi_lset( &Z, 0 ) ); + MPI_CHK( esp_mpi_grow( &T1, 2 ) ); + MPI_CHK( esp_mpi_grow( &T2, 3 ) ); - k = mpi_bitlen( &Y ) % biL; + k = esp_mpi_bitlen( &Y ) % biL; if( k < biL - 1 ) { k = biL - 1 - k; - MPI_CHK( mpi_shift_l( &X, k ) ); - MPI_CHK( mpi_shift_l( &Y, k ) ); + MPI_CHK( esp_mpi_shift_l( &X, k ) ); + MPI_CHK( esp_mpi_shift_l( &Y, k ) ); } else k = 0; n = X.n - 1; t = Y.n - 1; - MPI_CHK( mpi_shift_l( &Y, biL * ( n - t ) ) ); + MPI_CHK( esp_mpi_shift_l( &Y, biL * ( n - t ) ) ); - while( mpi_cmp_mpi( &X, &Y ) >= 0 ) + while( esp_mpi_cmp_mpi( &X, &Y ) >= 0 ) { Z.p[n - t]++; - MPI_CHK( mpi_sub_mpi( &X, &X, &Y ) ); + MPI_CHK( esp_mpi_sub_mpi( &X, &X, &Y ) ); } - MPI_CHK( mpi_shift_r( &Y, biL * ( n - t ) ) ); + MPI_CHK( esp_mpi_shift_r( &Y, biL * ( n - t ) ) ); for( i = n; i > t ; i-- ) { @@ -1239,51 +1239,51 @@ int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ) { Z.p[i - t - 1]--; - MPI_CHK( mpi_lset( &T1, 0 ) ); + MPI_CHK( esp_mpi_lset( &T1, 0 ) ); T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1]; T1.p[1] = Y.p[t]; - MPI_CHK( mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) ); + MPI_CHK( esp_mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) ); - MPI_CHK( mpi_lset( &T2, 0 ) ); + MPI_CHK( esp_mpi_lset( &T2, 0 ) ); T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2]; T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1]; T2.p[2] = X.p[i]; } - while( mpi_cmp_mpi( &T1, &T2 ) > 0 ); + while( esp_mpi_cmp_mpi( &T1, &T2 ) > 0 ); - MPI_CHK( mpi_mul_int( &T1, &Y, Z.p[i - t - 1] ) ); - MPI_CHK( mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); - MPI_CHK( mpi_sub_mpi( &X, &X, &T1 ) ); + MPI_CHK( esp_mpi_mul_int( &T1, &Y, Z.p[i - t - 1] ) ); + MPI_CHK( esp_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); + MPI_CHK( esp_mpi_sub_mpi( &X, &X, &T1 ) ); - if( mpi_cmp_int( &X, 0 ) < 0 ) + if( esp_mpi_cmp_int( &X, 0 ) < 0 ) { - MPI_CHK( mpi_copy( &T1, &Y ) ); - MPI_CHK( mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); - MPI_CHK( mpi_add_mpi( &X, &X, &T1 ) ); + MPI_CHK( esp_mpi_copy( &T1, &Y ) ); + MPI_CHK( esp_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); + MPI_CHK( esp_mpi_add_mpi( &X, &X, &T1 ) ); Z.p[i - t - 1]--; } } if( Q != NULL ) { - MPI_CHK( mpi_copy( Q, &Z ) ); + MPI_CHK( esp_mpi_copy( Q, &Z ) ); Q->s = A->s * B->s; } if( R != NULL ) { - MPI_CHK( mpi_shift_r( &X, k ) ); + MPI_CHK( esp_mpi_shift_r( &X, k ) ); X.s = A->s; - MPI_CHK( mpi_copy( R, &X ) ); + MPI_CHK( esp_mpi_copy( R, &X ) ); - if( mpi_cmp_int( R, 0 ) == 0 ) + if( esp_mpi_cmp_int( R, 0 ) == 0 ) R->s = 1; } cleanup: - mpi_free( &X ); mpi_free( &Y ); mpi_free( &Z ); - mpi_free( &T1 ); mpi_free( &T2 ); + esp_mpi_free( &X ); esp_mpi_free( &Y ); esp_mpi_free( &Z ); + esp_mpi_free( &T1 ); esp_mpi_free( &T2 ); return( ret ); } @@ -1291,36 +1291,36 @@ cleanup: /* * Division by int: A = Q * b + R */ -int mpi_div_int( mpi *Q, mpi *R, const mpi *A, mpi_sint b ) +int esp_mpi_div_int( mpi *Q, mpi *R, const mpi *A, esp_mpi_sint b ) { mpi _B; - mpi_uint p[1]; + esp_mpi_uint p[1]; p[0] = ( b < 0 ) ? -b : b; _B.s = ( b < 0 ) ? -1 : 1; _B.n = 1; _B.p = p; - return( mpi_div_mpi( Q, R, A, &_B ) ); + return( esp_mpi_div_mpi( Q, R, A, &_B ) ); } /* * Modulo: R = A mod B */ -int mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ) +int esp_mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ) { int ret; - if( mpi_cmp_int( B, 0 ) < 0 ) + if( esp_mpi_cmp_int( B, 0 ) < 0 ) return( ERR_MPI_NEGATIVE_VALUE ); - MPI_CHK( mpi_div_mpi( NULL, R, A, B ) ); + MPI_CHK( esp_mpi_div_mpi( NULL, R, A, B ) ); - while( mpi_cmp_int( R, 0 ) < 0 ) - MPI_CHK( mpi_add_mpi( R, R, B ) ); + while( esp_mpi_cmp_int( R, 0 ) < 0 ) + MPI_CHK( esp_mpi_add_mpi( R, R, B ) ); - while( mpi_cmp_mpi( R, B ) >= 0 ) - MPI_CHK( mpi_sub_mpi( R, R, B ) ); + while( esp_mpi_cmp_mpi( R, B ) >= 0 ) + MPI_CHK( esp_mpi_sub_mpi( R, R, B ) ); cleanup: @@ -1330,10 +1330,10 @@ cleanup: /* * Modulo: r = A mod b */ -int mpi_mod_int( mpi_uint *r, const mpi *A, mpi_sint b ) +int esp_mpi_mod_int( esp_mpi_uint *r, const mpi *A, esp_mpi_sint b ) { size_t i; - mpi_uint x, y, z; + esp_mpi_uint x, y, z; if( b == 0 ) return( ERR_MPI_DIVISION_BY_ZERO ); @@ -1387,9 +1387,9 @@ int mpi_mod_int( mpi_uint *r, const mpi *A, mpi_sint b ) /* * Fast Montgomery initialization (thanks to Tom St Denis) */ -static void mpi_montg_init( mpi_uint *mm, const mpi *N ) +static void esp_mpi_montg_init( esp_mpi_uint *mm, const mpi *N ) { - mpi_uint x, m0 = N->p[0]; + esp_mpi_uint x, m0 = N->p[0]; unsigned int i; x = m0; @@ -1404,11 +1404,11 @@ static void mpi_montg_init( mpi_uint *mm, const mpi *N ) /* * Montgomery multiplication: A = A * B * R^-1 mod N (HAC 14.36) */ -static void mpi_montmul( mpi *A, const mpi *B, const mpi *N, mpi_uint mm, +static void esp_mpi_montmul( mpi *A, const mpi *B, const mpi *N, esp_mpi_uint mm, const mpi *T ) { size_t n, m; - mpi_uint *d = NULL; + esp_mpi_uint *d = NULL; memset( T->p, 0, T->n * ciL ); @@ -1422,7 +1422,7 @@ static void mpi_montmul( mpi *A, const mpi *B, const mpi *N, mpi_uint mm, ets_bigint_montgomery_mult_getz(A->p, n); } else{ - mpi_printf("Montgomery multiplication failed\n"); + esp_mpi_printf("Montgomery multiplication failed\n"); } BIGNUM_UNLOCK(); @@ -1431,45 +1431,45 @@ static void mpi_montmul( mpi *A, const mpi *B, const mpi *N, mpi_uint mm, /* * Montgomery reduction: A = A * R^-1 mod N */ -static void mpi_montred( mpi *A, const mpi *N, mpi_uint mm, const mpi *T ) +static void esp_mpi_montred( mpi *A, const mpi *N, esp_mpi_uint mm, const mpi *T ) { - mpi_uint z = 1; + esp_mpi_uint z = 1; mpi U; U.n = U.s = (int) z; U.p = &z; - mpi_montmul( A, &U, N, mm, T ); + esp_mpi_montmul( A, &U, N, mm, T ); } /* * Sliding-window exponentiation: X = A^E mod N (HAC 14.85) */ -int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) +int esp_mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) { int ret; size_t wbits, wsize, one = 1; size_t i, j, nblimbs; size_t bufsize, nbits; - mpi_uint ei, mm, state; + esp_mpi_uint ei, mm, state; mpi RR, T, W[ 2 << MPI_WINDOW_SIZE ], Apos; int neg; - if( mpi_cmp_int( N, 0 ) < 0 || ( N->p[0] & 1 ) == 0 ) + if( esp_mpi_cmp_int( N, 0 ) < 0 || ( N->p[0] & 1 ) == 0 ) return( ERR_MPI_BAD_INPUT_DATA ); - if( mpi_cmp_int( E, 0 ) < 0 ) + if( esp_mpi_cmp_int( E, 0 ) < 0 ) return( ERR_MPI_BAD_INPUT_DATA ); /* * Init temps and window size */ - mpi_montg_init( &mm, N ); - mpi_init( &RR ); mpi_init( &T ); - mpi_init( &Apos ); + esp_mpi_montg_init( &mm, N ); + esp_mpi_init( &RR ); esp_mpi_init( &T ); + esp_mpi_init( &Apos ); memset( W, 0, sizeof( W ) ); - i = mpi_bitlen( E ); + i = esp_mpi_bitlen( E ); wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 : ( i > 79 ) ? 4 : ( i > 23 ) ? 3 : 1; @@ -1478,9 +1478,9 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) wsize = MPI_WINDOW_SIZE; j = N->n + 1; - MPI_CHK( mpi_grow( X, j ) ); - MPI_CHK( mpi_grow( &W[1], j ) ); - MPI_CHK( mpi_grow( &T, j * 2 ) ); + MPI_CHK( esp_mpi_grow( X, j ) ); + MPI_CHK( esp_mpi_grow( &W[1], j ) ); + MPI_CHK( esp_mpi_grow( &T, j * 2 ) ); /* * Compensate for negative A (and correct at the end) @@ -1488,7 +1488,7 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) neg = ( A->s == -1 ); if( neg ) { - MPI_CHK( mpi_copy( &Apos, A ) ); + MPI_CHK( esp_mpi_copy( &Apos, A ) ); Apos.s = 1; A = &Apos; } @@ -1498,9 +1498,9 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) */ if( _RR == NULL || _RR->p == NULL ) { - MPI_CHK( mpi_lset( &RR, 1 ) ); - MPI_CHK( mpi_shift_l( &RR, N->n * 2 * biL ) ); - MPI_CHK( mpi_mod_mpi( &RR, &RR, N ) ); + MPI_CHK( esp_mpi_lset( &RR, 1 ) ); + MPI_CHK( esp_mpi_shift_l( &RR, N->n * 2 * biL ) ); + MPI_CHK( esp_mpi_mod_mpi( &RR, &RR, N ) ); if( _RR != NULL ) memcpy( _RR, &RR, sizeof( mpi ) ); @@ -1511,18 +1511,18 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) /* * W[1] = A * R^2 * R^-1 mod N = A * R mod N */ - if( mpi_cmp_mpi( A, N ) >= 0 ) - MPI_CHK( mpi_mod_mpi( &W[1], A, N ) ); + if( esp_mpi_cmp_mpi( A, N ) >= 0 ) + MPI_CHK( esp_mpi_mod_mpi( &W[1], A, N ) ); else - MPI_CHK( mpi_copy( &W[1], A ) ); + MPI_CHK( esp_mpi_copy( &W[1], A ) ); - mpi_montmul( &W[1], &RR, N, mm, &T ); + esp_mpi_montmul( &W[1], &RR, N, mm, &T ); /* * X = R^2 * R^-1 mod N = R mod N */ - MPI_CHK( mpi_copy( X, &RR ) ); - mpi_montred( X, N, mm, &T ); + MPI_CHK( esp_mpi_copy( X, &RR ) ); + esp_mpi_montred( X, N, mm, &T ); if( wsize > 1 ) { @@ -1531,21 +1531,21 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) */ j = one << ( wsize - 1 ); - MPI_CHK( mpi_grow( &W[j], N->n + 1 ) ); - MPI_CHK( mpi_copy( &W[j], &W[1] ) ); + MPI_CHK( esp_mpi_grow( &W[j], N->n + 1 ) ); + MPI_CHK( esp_mpi_copy( &W[j], &W[1] ) ); for( i = 0; i < wsize - 1; i++ ) - mpi_montmul( &W[j], &W[j], N, mm, &T ); + esp_mpi_montmul( &W[j], &W[j], N, mm, &T ); /* * W[i] = W[i - 1] * W[1] */ for( i = j + 1; i < ( one << wsize ); i++ ) { - MPI_CHK( mpi_grow( &W[i], N->n + 1 ) ); - MPI_CHK( mpi_copy( &W[i], &W[i - 1] ) ); + MPI_CHK( esp_mpi_grow( &W[i], N->n + 1 ) ); + MPI_CHK( esp_mpi_copy( &W[i], &W[i - 1] ) ); - mpi_montmul( &W[i], &W[1], N, mm, &T ); + esp_mpi_montmul( &W[i], &W[1], N, mm, &T ); } } @@ -1564,7 +1564,7 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) nblimbs--; - bufsize = sizeof( mpi_uint ) << 3; + bufsize = sizeof( esp_mpi_uint ) << 3; } bufsize--; @@ -1582,7 +1582,7 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) /* * out of window, square X */ - mpi_montmul( X, X, N, mm, &T ); + esp_mpi_montmul( X, X, N, mm, &T ); continue; } @@ -1600,12 +1600,12 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) * X = X^wsize R^-1 mod N */ for( i = 0; i < wsize; i++ ) - mpi_montmul( X, X, N, mm, &T ); + esp_mpi_montmul( X, X, N, mm, &T ); /* * X = X * W[wbits] R^-1 mod N */ - mpi_montmul( X, &W[wbits], N, mm, &T ); + esp_mpi_montmul( X, &W[wbits], N, mm, &T ); state--; nbits = 0; @@ -1618,34 +1618,34 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) */ for( i = 0; i < nbits; i++ ) { - mpi_montmul( X, X, N, mm, &T ); + esp_mpi_montmul( X, X, N, mm, &T ); wbits <<= 1; if( ( wbits & ( one << wsize ) ) != 0 ) - mpi_montmul( X, &W[1], N, mm, &T ); + esp_mpi_montmul( X, &W[1], N, mm, &T ); } /* * X = A^E * R * R^-1 mod N = A^E mod N */ - mpi_montred( X, N, mm, &T ); + esp_mpi_montred( X, N, mm, &T ); if( neg ) { X->s = -1; - MPI_CHK( mpi_add_mpi( X, N, X ) ); + MPI_CHK( esp_mpi_add_mpi( X, N, X ) ); } cleanup: for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ ) - mpi_free( &W[i] ); + esp_mpi_free( &W[i] ); - mpi_free( &W[1] ); mpi_free( &T ); mpi_free( &Apos ); + esp_mpi_free( &W[1] ); esp_mpi_free( &T ); esp_mpi_free( &Apos ); if( _RR == NULL || _RR->p == NULL ) - mpi_free( &RR ); + esp_mpi_free( &RR ); return( ret ); } @@ -1653,51 +1653,51 @@ cleanup: /* * Greatest common divisor: G = gcd(A, B) (HAC 14.54) */ -int mpi_gcd( mpi *G, const mpi *A, const mpi *B ) +int esp_mpi_gcd( mpi *G, const mpi *A, const mpi *B ) { int ret; size_t lz, lzt; mpi TG, TA, TB; - mpi_init( &TG ); mpi_init( &TA ); mpi_init( &TB ); + esp_mpi_init( &TG ); esp_mpi_init( &TA ); esp_mpi_init( &TB ); - MPI_CHK( mpi_copy( &TA, A ) ); - MPI_CHK( mpi_copy( &TB, B ) ); + MPI_CHK( esp_mpi_copy( &TA, A ) ); + MPI_CHK( esp_mpi_copy( &TB, B ) ); - lz = mpi_lsb( &TA ); - lzt = mpi_lsb( &TB ); + lz = esp_mpi_lsb( &TA ); + lzt = esp_mpi_lsb( &TB ); if( lzt < lz ) lz = lzt; - MPI_CHK( mpi_shift_r( &TA, lz ) ); - MPI_CHK( mpi_shift_r( &TB, lz ) ); + MPI_CHK( esp_mpi_shift_r( &TA, lz ) ); + MPI_CHK( esp_mpi_shift_r( &TB, lz ) ); TA.s = TB.s = 1; - while( mpi_cmp_int( &TA, 0 ) != 0 ) + while( esp_mpi_cmp_int( &TA, 0 ) != 0 ) { - MPI_CHK( mpi_shift_r( &TA, mpi_lsb( &TA ) ) ); - MPI_CHK( mpi_shift_r( &TB, mpi_lsb( &TB ) ) ); + MPI_CHK( esp_mpi_shift_r( &TA, esp_mpi_lsb( &TA ) ) ); + MPI_CHK( esp_mpi_shift_r( &TB, esp_mpi_lsb( &TB ) ) ); - if( mpi_cmp_mpi( &TA, &TB ) >= 0 ) + if( esp_mpi_cmp_mpi( &TA, &TB ) >= 0 ) { - MPI_CHK( mpi_sub_abs( &TA, &TA, &TB ) ); - MPI_CHK( mpi_shift_r( &TA, 1 ) ); + MPI_CHK( esp_mpi_sub_abs( &TA, &TA, &TB ) ); + MPI_CHK( esp_mpi_shift_r( &TA, 1 ) ); } else { - MPI_CHK( mpi_sub_abs( &TB, &TB, &TA ) ); - MPI_CHK( mpi_shift_r( &TB, 1 ) ); + MPI_CHK( esp_mpi_sub_abs( &TB, &TB, &TA ) ); + MPI_CHK( esp_mpi_shift_r( &TB, 1 ) ); } } - MPI_CHK( mpi_shift_l( &TB, lz ) ); - MPI_CHK( mpi_copy( G, &TB ) ); + MPI_CHK( esp_mpi_shift_l( &TB, lz ) ); + MPI_CHK( esp_mpi_copy( G, &TB ) ); cleanup: - mpi_free( &TG ); mpi_free( &TA ); mpi_free( &TB ); + esp_mpi_free( &TG ); esp_mpi_free( &TA ); esp_mpi_free( &TB ); return( ret ); } @@ -1709,7 +1709,7 @@ cleanup: * regardless of the platform endianness (useful when f_rng is actually * deterministic, eg for tests). */ -int mpi_fill_random( mpi *X, size_t size, +int esp_mpi_fill_random( mpi *X, size_t size, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { @@ -1720,7 +1720,7 @@ int mpi_fill_random( mpi *X, size_t size, return( ERR_MPI_BAD_INPUT_DATA ); MPI_CHK( f_rng( p_rng, buf, size ) ); - MPI_CHK( mpi_read_binary( X, buf, size ) ); + MPI_CHK( esp_mpi_read_binary( X, buf, size ) ); cleanup: return( ret ); @@ -1729,94 +1729,94 @@ cleanup: /* * Modular inverse: X = A^-1 mod N (HAC 14.61 / 14.64) */ -int mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ) +int esp_mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ) { int ret; mpi G, TA, TU, U1, U2, TB, TV, V1, V2; - if( mpi_cmp_int( N, 0 ) <= 0 ) + if( esp_mpi_cmp_int( N, 0 ) <= 0 ) return( ERR_MPI_BAD_INPUT_DATA ); - mpi_init( &TA ); mpi_init( &TU ); mpi_init( &U1 ); mpi_init( &U2 ); - mpi_init( &G ); mpi_init( &TB ); mpi_init( &TV ); - mpi_init( &V1 ); mpi_init( &V2 ); + esp_mpi_init( &TA ); esp_mpi_init( &TU ); esp_mpi_init( &U1 ); esp_mpi_init( &U2 ); + esp_mpi_init( &G ); esp_mpi_init( &TB ); esp_mpi_init( &TV ); + esp_mpi_init( &V1 ); esp_mpi_init( &V2 ); - MPI_CHK( mpi_gcd( &G, A, N ) ); + MPI_CHK( esp_mpi_gcd( &G, A, N ) ); - if( mpi_cmp_int( &G, 1 ) != 0 ) + if( esp_mpi_cmp_int( &G, 1 ) != 0 ) { ret = ERR_MPI_NOT_ACCEPTABLE; goto cleanup; } - MPI_CHK( mpi_mod_mpi( &TA, A, N ) ); - MPI_CHK( mpi_copy( &TU, &TA ) ); - MPI_CHK( mpi_copy( &TB, N ) ); - MPI_CHK( mpi_copy( &TV, N ) ); + MPI_CHK( esp_mpi_mod_mpi( &TA, A, N ) ); + MPI_CHK( esp_mpi_copy( &TU, &TA ) ); + MPI_CHK( esp_mpi_copy( &TB, N ) ); + MPI_CHK( esp_mpi_copy( &TV, N ) ); - MPI_CHK( mpi_lset( &U1, 1 ) ); - MPI_CHK( mpi_lset( &U2, 0 ) ); - MPI_CHK( mpi_lset( &V1, 0 ) ); - MPI_CHK( mpi_lset( &V2, 1 ) ); + MPI_CHK( esp_mpi_lset( &U1, 1 ) ); + MPI_CHK( esp_mpi_lset( &U2, 0 ) ); + MPI_CHK( esp_mpi_lset( &V1, 0 ) ); + MPI_CHK( esp_mpi_lset( &V2, 1 ) ); do { while( ( TU.p[0] & 1 ) == 0 ) { - MPI_CHK( mpi_shift_r( &TU, 1 ) ); + MPI_CHK( esp_mpi_shift_r( &TU, 1 ) ); if( ( U1.p[0] & 1 ) != 0 || ( U2.p[0] & 1 ) != 0 ) { - MPI_CHK( mpi_add_mpi( &U1, &U1, &TB ) ); - MPI_CHK( mpi_sub_mpi( &U2, &U2, &TA ) ); + MPI_CHK( esp_mpi_add_mpi( &U1, &U1, &TB ) ); + MPI_CHK( esp_mpi_sub_mpi( &U2, &U2, &TA ) ); } - MPI_CHK( mpi_shift_r( &U1, 1 ) ); - MPI_CHK( mpi_shift_r( &U2, 1 ) ); + MPI_CHK( esp_mpi_shift_r( &U1, 1 ) ); + MPI_CHK( esp_mpi_shift_r( &U2, 1 ) ); } while( ( TV.p[0] & 1 ) == 0 ) { - MPI_CHK( mpi_shift_r( &TV, 1 ) ); + MPI_CHK( esp_mpi_shift_r( &TV, 1 ) ); if( ( V1.p[0] & 1 ) != 0 || ( V2.p[0] & 1 ) != 0 ) { - MPI_CHK( mpi_add_mpi( &V1, &V1, &TB ) ); - MPI_CHK( mpi_sub_mpi( &V2, &V2, &TA ) ); + MPI_CHK( esp_mpi_add_mpi( &V1, &V1, &TB ) ); + MPI_CHK( esp_mpi_sub_mpi( &V2, &V2, &TA ) ); } - MPI_CHK( mpi_shift_r( &V1, 1 ) ); - MPI_CHK( mpi_shift_r( &V2, 1 ) ); + MPI_CHK( esp_mpi_shift_r( &V1, 1 ) ); + MPI_CHK( esp_mpi_shift_r( &V2, 1 ) ); } - if( mpi_cmp_mpi( &TU, &TV ) >= 0 ) + if( esp_mpi_cmp_mpi( &TU, &TV ) >= 0 ) { - MPI_CHK( mpi_sub_mpi( &TU, &TU, &TV ) ); - MPI_CHK( mpi_sub_mpi( &U1, &U1, &V1 ) ); - MPI_CHK( mpi_sub_mpi( &U2, &U2, &V2 ) ); + MPI_CHK( esp_mpi_sub_mpi( &TU, &TU, &TV ) ); + MPI_CHK( esp_mpi_sub_mpi( &U1, &U1, &V1 ) ); + MPI_CHK( esp_mpi_sub_mpi( &U2, &U2, &V2 ) ); } else { - MPI_CHK( mpi_sub_mpi( &TV, &TV, &TU ) ); - MPI_CHK( mpi_sub_mpi( &V1, &V1, &U1 ) ); - MPI_CHK( mpi_sub_mpi( &V2, &V2, &U2 ) ); + MPI_CHK( esp_mpi_sub_mpi( &TV, &TV, &TU ) ); + MPI_CHK( esp_mpi_sub_mpi( &V1, &V1, &U1 ) ); + MPI_CHK( esp_mpi_sub_mpi( &V2, &V2, &U2 ) ); } } - while( mpi_cmp_int( &TU, 0 ) != 0 ); + while( esp_mpi_cmp_int( &TU, 0 ) != 0 ); - while( mpi_cmp_int( &V1, 0 ) < 0 ) - MPI_CHK( mpi_add_mpi( &V1, &V1, N ) ); + while( esp_mpi_cmp_int( &V1, 0 ) < 0 ) + MPI_CHK( esp_mpi_add_mpi( &V1, &V1, N ) ); - while( mpi_cmp_mpi( &V1, N ) >= 0 ) - MPI_CHK( mpi_sub_mpi( &V1, &V1, N ) ); + while( esp_mpi_cmp_mpi( &V1, N ) >= 0 ) + MPI_CHK( esp_mpi_sub_mpi( &V1, &V1, N ) ); - MPI_CHK( mpi_copy( X, &V1 ) ); + MPI_CHK( esp_mpi_copy( X, &V1 ) ); cleanup: - mpi_free( &TA ); mpi_free( &TU ); mpi_free( &U1 ); mpi_free( &U2 ); - mpi_free( &G ); mpi_free( &TB ); mpi_free( &TV ); - mpi_free( &V1 ); mpi_free( &V2 ); + esp_mpi_free( &TA ); esp_mpi_free( &TU ); esp_mpi_free( &U1 ); esp_mpi_free( &U2 ); + esp_mpi_free( &G ); esp_mpi_free( &TB ); esp_mpi_free( &TV ); + esp_mpi_free( &V1 ); esp_mpi_free( &V2 ); return( ret ); } @@ -1855,21 +1855,21 @@ static const int small_prime[] = * ERR_MPI_NOT_ACCEPTABLE: certain non-prime * other negative: error */ -static int mpi_check_small_factors( const mpi *X ) +static int esp_mpi_check_small_factors( const mpi *X ) { int ret = 0; size_t i; - mpi_uint r; + esp_mpi_uint r; if( ( X->p[0] & 1 ) == 0 ) return( ERR_MPI_NOT_ACCEPTABLE ); for( i = 0; small_prime[i] > 0; i++ ) { - if( mpi_cmp_int( X, small_prime[i] ) <= 0 ) + if( esp_mpi_cmp_int( X, small_prime[i] ) <= 0 ) return( 1 ); - MPI_CHK( mpi_mod_int( &r, X, small_prime[i] ) ); + MPI_CHK( esp_mpi_mod_int( &r, X, small_prime[i] ) ); if( r == 0 ) return( ERR_MPI_NOT_ACCEPTABLE ); @@ -1882,7 +1882,7 @@ cleanup: /* * Miller-Rabin pseudo-primality test (HAC 4.24) */ -static int mpi_miller_rabin( const mpi *X, +static int esp_mpi_miller_rabin( const mpi *X, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { @@ -1890,19 +1890,19 @@ static int mpi_miller_rabin( const mpi *X, size_t i, j, k, n, s; mpi W, R, T, A, RR; - mpi_init( &W ); mpi_init( &R ); mpi_init( &T ); mpi_init( &A ); - mpi_init( &RR ); + esp_mpi_init( &W ); esp_mpi_init( &R ); esp_mpi_init( &T ); esp_mpi_init( &A ); + esp_mpi_init( &RR ); /* * W = |X| - 1 * R = W >> lsb( W ) */ - MPI_CHK( mpi_sub_int( &W, X, 1 ) ); - s = mpi_lsb( &W ); - MPI_CHK( mpi_copy( &R, &W ) ); - MPI_CHK( mpi_shift_r( &R, s ) ); + MPI_CHK( esp_mpi_sub_int( &W, X, 1 ) ); + s = esp_mpi_lsb( &W ); + MPI_CHK( esp_mpi_copy( &R, &W ) ); + MPI_CHK( esp_mpi_shift_r( &R, s ) ); - i = mpi_bitlen( X ); + i = esp_mpi_bitlen( X ); /* * HAC, table 4.4 */ @@ -1915,51 +1915,51 @@ static int mpi_miller_rabin( const mpi *X, /* * pick a random A, 1 < A < |X| - 1 */ - MPI_CHK( mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); + MPI_CHK( esp_mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); - if( mpi_cmp_mpi( &A, &W ) >= 0 ) + if( esp_mpi_cmp_mpi( &A, &W ) >= 0 ) { - j = mpi_bitlen( &A ) - mpi_bitlen( &W ); - MPI_CHK( mpi_shift_r( &A, j + 1 ) ); + j = esp_mpi_bitlen( &A ) - esp_mpi_bitlen( &W ); + MPI_CHK( esp_mpi_shift_r( &A, j + 1 ) ); } A.p[0] |= 3; count = 0; do { - MPI_CHK( mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); + MPI_CHK( esp_mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); - j = mpi_bitlen( &A ); - k = mpi_bitlen( &W ); + j = esp_mpi_bitlen( &A ); + k = esp_mpi_bitlen( &W ); if (j > k) { - MPI_CHK( mpi_shift_r( &A, j - k ) ); + MPI_CHK( esp_mpi_shift_r( &A, j - k ) ); } if (count++ > 30) { return ERR_MPI_NOT_ACCEPTABLE; } - } while ( mpi_cmp_mpi( &A, &W ) >= 0 || - mpi_cmp_int( &A, 1 ) <= 0 ); + } while ( esp_mpi_cmp_mpi( &A, &W ) >= 0 || + esp_mpi_cmp_int( &A, 1 ) <= 0 ); /* * A = A^R mod |X| */ - MPI_CHK( mpi_exp_mod( &A, &A, &R, X, &RR ) ); + MPI_CHK( esp_mpi_exp_mod( &A, &A, &R, X, &RR ) ); - if( mpi_cmp_mpi( &A, &W ) == 0 || - mpi_cmp_int( &A, 1 ) == 0 ) + if( esp_mpi_cmp_mpi( &A, &W ) == 0 || + esp_mpi_cmp_int( &A, 1 ) == 0 ) continue; j = 1; - while( j < s && mpi_cmp_mpi( &A, &W ) != 0 ) + while( j < s && esp_mpi_cmp_mpi( &A, &W ) != 0 ) { /* * A = A * A mod |X| */ - MPI_CHK( mpi_mul_mpi( &T, &A, &A ) ); - MPI_CHK( mpi_mod_mpi( &A, &T, X ) ); + MPI_CHK( esp_mpi_mul_mpi( &T, &A, &A ) ); + MPI_CHK( esp_mpi_mod_mpi( &A, &T, X ) ); - if( mpi_cmp_int( &A, 1 ) == 0 ) + if( esp_mpi_cmp_int( &A, 1 ) == 0 ) break; j++; @@ -1968,8 +1968,8 @@ static int mpi_miller_rabin( const mpi *X, /* * not prime if A != |X| - 1 or A == 1 */ - if( mpi_cmp_mpi( &A, &W ) != 0 || - mpi_cmp_int( &A, 1 ) == 0 ) + if( esp_mpi_cmp_mpi( &A, &W ) != 0 || + esp_mpi_cmp_int( &A, 1 ) == 0 ) { ret = ERR_MPI_NOT_ACCEPTABLE; break; @@ -1977,8 +1977,8 @@ static int mpi_miller_rabin( const mpi *X, } cleanup: - mpi_free( &W ); mpi_free( &R ); mpi_free( &T ); mpi_free( &A ); - mpi_free( &RR ); + esp_mpi_free( &W ); esp_mpi_free( &R ); esp_mpi_free( &T ); esp_mpi_free( &A ); + esp_mpi_free( &RR ); return( ret ); } @@ -1986,7 +1986,7 @@ cleanup: /* * Pseudo-primality test: small factors, then Miller-Rabin */ -int mpi_is_prime( const mpi *X, +int esp_mpi_is_prime( const mpi *X, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { @@ -1997,14 +1997,14 @@ int mpi_is_prime( const mpi *X, XX.n = X->n; XX.p = X->p; - if( mpi_cmp_int( &XX, 0 ) == 0 || - mpi_cmp_int( &XX, 1 ) == 0 ) + if( esp_mpi_cmp_int( &XX, 0 ) == 0 || + esp_mpi_cmp_int( &XX, 1 ) == 0 ) return( ERR_MPI_NOT_ACCEPTABLE ); - if( mpi_cmp_int( &XX, 2 ) == 0 ) + if( esp_mpi_cmp_int( &XX, 2 ) == 0 ) return( 0 ); - if( ( ret = mpi_check_small_factors( &XX ) ) != 0 ) + if( ( ret = esp_mpi_check_small_factors( &XX ) ) != 0 ) { if( ret == 1 ) return( 0 ); @@ -2012,45 +2012,45 @@ int mpi_is_prime( const mpi *X, return( ret ); } - return( mpi_miller_rabin( &XX, f_rng, p_rng ) ); + return( esp_mpi_miller_rabin( &XX, f_rng, p_rng ) ); } /* * Prime number generation */ -int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, +int esp_mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { int ret; size_t k, n; - mpi_uint r; + esp_mpi_uint r; mpi Y; if( nbits < 3 || nbits > MPI_MAX_BITS ) return( ERR_MPI_BAD_INPUT_DATA ); - mpi_init( &Y ); + esp_mpi_init( &Y ); n = BITS_TO_LIMBS( nbits ); - MPI_CHK( mpi_fill_random( X, n * ciL, f_rng, p_rng ) ); + MPI_CHK( esp_mpi_fill_random( X, n * ciL, f_rng, p_rng ) ); - k = mpi_bitlen( X ); - if( k > nbits ) MPI_CHK( mpi_shift_r( X, k - nbits + 1 ) ); + k = esp_mpi_bitlen( X ); + if( k > nbits ) MPI_CHK( esp_mpi_shift_r( X, k - nbits + 1 ) ); - mpi_set_bit( X, nbits-1, 1 ); + esp_mpi_set_bit( X, nbits-1, 1 ); X->p[0] |= 1; if( dh_flag == 0 ) { - while( ( ret = mpi_is_prime( X, f_rng, p_rng ) ) != 0 ) + while( ( ret = esp_mpi_is_prime( X, f_rng, p_rng ) ) != 0 ) { if( ret != ERR_MPI_NOT_ACCEPTABLE ) goto cleanup; - MPI_CHK( mpi_add_int( X, X, 2 ) ); + MPI_CHK( esp_mpi_add_int( X, X, 2 ) ); } } else @@ -2063,15 +2063,15 @@ int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, X->p[0] |= 2; - MPI_CHK( mpi_mod_int( &r, X, 3 ) ); + MPI_CHK( esp_mpi_mod_int( &r, X, 3 ) ); if( r == 0 ) - MPI_CHK( mpi_add_int( X, X, 8 ) ); + MPI_CHK( esp_mpi_add_int( X, X, 8 ) ); else if( r == 1 ) - MPI_CHK( mpi_add_int( X, X, 4 ) ); + MPI_CHK( esp_mpi_add_int( X, X, 4 ) ); /* Set Y = (X-1) / 2, which is X / 2 because X is odd */ - MPI_CHK( mpi_copy( &Y, X ) ); - MPI_CHK( mpi_shift_r( &Y, 1 ) ); + MPI_CHK( esp_mpi_copy( &Y, X ) ); + MPI_CHK( esp_mpi_shift_r( &Y, 1 ) ); while( 1 ) { @@ -2079,10 +2079,10 @@ int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, * First, check small factors for X and Y * before doing Miller-Rabin on any of them */ - if( ( ret = mpi_check_small_factors( X ) ) == 0 && - ( ret = mpi_check_small_factors( &Y ) ) == 0 && - ( ret = mpi_miller_rabin( X, f_rng, p_rng ) ) == 0 && - ( ret = mpi_miller_rabin( &Y, f_rng, p_rng ) ) == 0 ) + if( ( ret = esp_mpi_check_small_factors( X ) ) == 0 && + ( ret = esp_mpi_check_small_factors( &Y ) ) == 0 && + ( ret = esp_mpi_miller_rabin( X, f_rng, p_rng ) ) == 0 && + ( ret = esp_mpi_miller_rabin( &Y, f_rng, p_rng ) ) == 0 ) { break; } @@ -2095,14 +2095,14 @@ int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, * Y = 1 mod 2 and Y = 2 mod 3 (eq X = 3 mod 4 and X = 2 mod 3) * so up Y by 6 and X by 12. */ - MPI_CHK( mpi_add_int( X, X, 12 ) ); - MPI_CHK( mpi_add_int( &Y, &Y, 6 ) ); + MPI_CHK( esp_mpi_add_int( X, X, 12 ) ); + MPI_CHK( esp_mpi_add_int( &Y, &Y, 6 ) ); } } cleanup: - mpi_free( &Y ); + esp_mpi_free( &Y ); return( ret ); } diff --git a/components/esp32/esp_thread.c b/components/esp32/esp_thread.c new file mode 100644 index 000000000..e72dc996b --- /dev/null +++ b/components/esp32/esp_thread.c @@ -0,0 +1,53 @@ +#include "esp_thread.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +static xSemaphoreHandle esp_thread_mutex[MUTEX_MAX_NUM]; +static int esp_thread_sig[MUTEX_MAX_NUM]; + +int esp_thread_init(void) +{ + int i; + + for (i = 0; i < MUTEX_MAX_NUM; i++) { + esp_thread_mutex[i] = xSemaphoreCreateMutex(); + if (!esp_thread_mutex[i]) { + goto failed1; + } + esp_thread_sig[i] = 0; + } + + return 0; + +failed1: + for (i--; i >= 0; i--) + vQueueDelete(esp_thread_mutex[i]); + + return -1; +} + +void esp_thread_lock(unsigned int num) +{ + xSemaphoreTake(esp_thread_mutex[num], portMAX_DELAY); +} + +void esp_thread_unlock(unsigned int num) +{ + xSemaphoreGive(esp_thread_mutex[num]); +} + +void esp_thread_take(unsigned int num) +{ + esp_thread_sig[num]++; +} + +void esp_thread_give(unsigned int num) +{ + esp_thread_sig[num]--; +} + +bool esp_thread_is_used(unsigned int num) +{ + return (esp_thread_sig[num] != 0) ? true : false; +} + diff --git a/components/mbedtls/include/port/aes_alt.h b/components/esp32/include/aes.h similarity index 89% rename from components/mbedtls/include/port/aes_alt.h rename to components/esp32/include/aes.h index a02f32f29..aa81e1b5f 100644 --- a/components/mbedtls/include/port/aes_alt.h +++ b/components/esp32/include/aes.h @@ -1,5 +1,5 @@ /** - * \file aes_alt.h + * \file esp_aes.h * * \brief AES block cipher * @@ -21,8 +21,8 @@ * */ -#ifndef AES_ALT_H -#define AES_ALT_H +#ifndef ESP_AES_H +#define ESP_AES_H #include "c_types.h" #include "rom/ets_sys.h" @@ -32,8 +32,6 @@ extern "C" { #endif -#define ESP_AES_C - /* padlock.c and aesni.c rely on these values! */ #define AES_ENCRYPT 1 #define AES_DECRYPT 0 @@ -61,23 +59,21 @@ typedef struct uint32_t *rk; /*!< AES round keys */ KEY_CTX enc; KEY_CTX dec; -}aes_context; - -typedef aes_context AES_CTX; +}aes_context, AES_CTX; /** * \brief Initialize AES context * * \param ctx AES context to be initialized */ -void aes_init( AES_CTX *ctx ); +void esp_aes_init( AES_CTX *ctx ); /** * \brief Clear AES context * * \param ctx AES context to be cleared */ -void aes_free( AES_CTX *ctx ); +void esp_aes_free( AES_CTX *ctx ); /** * \brief AES key schedule (encryption) @@ -88,7 +84,7 @@ void aes_free( AES_CTX *ctx ); * * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH */ -int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); +int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -99,7 +95,7 @@ int aes_setkey_enc( AES_CTX *ctx, const unsigned char *key,unsigned int keybits * * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH */ -int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); +int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -111,7 +107,7 @@ int aes_setkey_dec( AES_CTX *ctx, const unsigned char *key,unsigned int keybits * * \return 0 if successful */ -int aes_crypt_ecb( AES_CTX *ctx,int mode,const unsigned char input[16],unsigned char output[16] ); +int esp_aes_crypt_ecb( AES_CTX *ctx,int mode,const unsigned char input[16],unsigned char output[16] ); /** * \brief AES-CBC buffer encryption/decryption @@ -135,7 +131,7 @@ int aes_crypt_ecb( AES_CTX *ctx,int mode,const unsigned char input[16],unsigned * * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH */ -int aes_crypt_cbc( AES_CTX *ctx, +int esp_aes_crypt_cbc( AES_CTX *ctx, int mode, size_t length, unsigned char iv[16], @@ -148,7 +144,7 @@ int aes_crypt_cbc( AES_CTX *ctx, * * Note: Due to the nature of CFB you should use the same key schedule for * both encryption and decryption. So a context initialized with - * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. * * \note Upon exit, the content of the IV is updated so that you can * call the function same function again on the following @@ -168,7 +164,7 @@ int aes_crypt_cbc( AES_CTX *ctx, * * \return 0 if successful */ -int aes_crypt_cfb128( AES_CTX *ctx, +int esp_aes_crypt_cfb128( AES_CTX *ctx, int mode, size_t length, size_t *iv_off, @@ -181,7 +177,7 @@ int aes_crypt_cfb128( AES_CTX *ctx, * * Note: Due to the nature of CFB you should use the same key schedule for * both encryption and decryption. So a context initialized with - * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. * * \note Upon exit, the content of the IV is updated so that you can * call the function same function again on the following @@ -200,7 +196,7 @@ int aes_crypt_cfb128( AES_CTX *ctx, * * \return 0 if successful */ -int aes_crypt_cfb8( AES_CTX *ctx, +int esp_aes_crypt_cfb8( AES_CTX *ctx, int mode, size_t length, unsigned char iv[16], @@ -214,7 +210,7 @@ int aes_crypt_cfb8( AES_CTX *ctx, * * Note: Due to the nature of CTR you should use the same key schedule for * both encryption and decryption. So a context initialized with - * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. * * \param ctx AES context * \param length The length of the data @@ -229,7 +225,7 @@ int aes_crypt_cfb8( AES_CTX *ctx, * * \return 0 if successful */ -int aes_crypt_ctr( AES_CTX *ctx, +int esp_aes_crypt_ctr( AES_CTX *ctx, size_t length, size_t *nc_off, unsigned char nonce_counter[16], @@ -247,7 +243,7 @@ int aes_crypt_ctr( AES_CTX *ctx, * \param input Plaintext block * \param output Output (ciphertext) block */ -void aes_encrypt( AES_CTX *ctx, const unsigned char input[16],unsigned char output[16] ); +void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16],unsigned char output[16] ); /** * \brief Internal AES block decryption function @@ -258,7 +254,7 @@ void aes_encrypt( AES_CTX *ctx, const unsigned char input[16],unsigned char outp * \param input Ciphertext block * \param output Output (plaintext) block */ -void aes_decrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ); +void esp_aes_decrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ); #ifdef __cplusplus } diff --git a/components/mbedtls/include/port/bignum_alt.h b/components/esp32/include/bignum.h similarity index 86% rename from components/mbedtls/include/port/bignum_alt.h rename to components/esp32/include/bignum.h index 64d492a98..4cb1ca88f 100644 --- a/components/mbedtls/include/port/bignum_alt.h +++ b/components/esp32/include/bignum.h @@ -20,8 +20,8 @@ * */ -#ifndef BIGNUM_ALT_H -#define BIGNUM_ALT_H +#ifndef _ESP_BIGNUM_H +#define _ESP_BIGNUM_H #include "c_types.h" #include "rom/ets_sys.h" @@ -42,9 +42,9 @@ #define MPI_CHK(f) do { if( ( ret = f ) != 0 ) goto cleanup; } while( 0 ) #if defined(MPI_DEBUG_ALT) -#define mpi_printf ets_printf +#define esp_mpi_printf ets_printf #else -#define mpi_printf +#define esp_mpi_printf #endif /* * Maximum size MPIs are allowed to grow to in number of limbs. @@ -78,8 +78,8 @@ #define MPI_MAX_BITS ( 8 * MPI_MAX_SIZE ) /**< Maximum number of bits for usable MPIs. */ /* - * When reading from files with mpi_read_file() and writing to files with - * mpi_write_file() the buffer should have space + * When reading from files with esp_mpi_read_file() and writing to files with + * esp_mpi_write_file() the buffer should have space * for a (short) label, the MPI (in the provided radix), the newline * characters and the '\0'. * @@ -108,8 +108,8 @@ #if ( ! defined(HAVE_INT32) && \ defined(_MSC_VER) && defined(_M_AMD64) ) #define HAVE_INT64 - typedef int64_t mpi_sint; - typedef uint64_t mpi_uint; + typedef int64_t esp_mpi_sint; + typedef uint64_t esp_mpi_uint; #else #if ( ! defined(HAVE_INT32) && \ defined(__GNUC__) && ( \ @@ -119,15 +119,15 @@ (defined(__sparc__) && defined(__arch64__)) || \ defined(__s390x__) || defined(__mips64) ) ) #define HAVE_INT64 - typedef int64_t mpi_sint; - typedef uint64_t mpi_uint; + typedef int64_t esp_mpi_sint; + typedef uint64_t esp_mpi_uint; /* t_udbl defined as 128-bit unsigned int */ typedef unsigned int t_udbl __attribute__((mode(TI))); #define HAVE_UDBL #else #define HAVE_INT32 - typedef int32_t mpi_sint; - typedef uint32_t mpi_uint; + typedef int32_t esp_mpi_sint; + typedef uint32_t esp_mpi_uint; typedef uint64_t t_udbl; #define HAVE_UDBL #endif /* !HAVE_INT32 && __GNUC__ && 64-bit platform */ @@ -144,9 +144,8 @@ typedef struct { int s; /*!< integer sign */ size_t n; /*!< total # of limbs */ - mpi_uint *p; /*!< pointer to limbs */ -} -mpi; + esp_mpi_uint *p; /*!< pointer to limbs */ +}mpi, MPI_CTX; /** * \brief Initialize one MPI (make internal references valid) @@ -155,14 +154,14 @@ mpi; * * \param X One MPI to initialize. */ -void mpi_init( mpi *X ); +void esp_mpi_init( mpi *X ); /** * \brief Unallocate one MPI * * \param X One MPI to unallocate. */ -void mpi_free( mpi *X ); +void esp_mpi_free( mpi *X ); /** * \brief Enlarge to the specified number of limbs @@ -173,7 +172,7 @@ void mpi_free( mpi *X ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_grow( mpi *X, size_t nblimbs ); +int esp_mpi_grow( mpi *X, size_t nblimbs ); /** * \brief Resize down, keeping at least the specified number of limbs @@ -184,7 +183,7 @@ int mpi_grow( mpi *X, size_t nblimbs ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_shrink( mpi *X, size_t nblimbs ); +int esp_mpi_shrink( mpi *X, size_t nblimbs ); /** * \brief Copy the contents of Y into X @@ -195,7 +194,7 @@ int mpi_shrink( mpi *X, size_t nblimbs ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_copy( mpi *X, const mpi *Y ); +int esp_mpi_copy( mpi *X, const mpi *Y ); /** * \brief Swap the contents of X and Y @@ -203,7 +202,7 @@ int mpi_copy( mpi *X, const mpi *Y ); * \param X First MPI value * \param Y Second MPI value */ -void mpi_swap( mpi *X, mpi *Y ); +void esp_mpi_swap( mpi *X, mpi *Y ); /** * \brief Safe conditional assignement X = Y if assign is 1 @@ -216,13 +215,13 @@ void mpi_swap( mpi *X, mpi *Y ); * ERR_MPI_ALLOC_FAILED if memory allocation failed, * * \note This function is equivalent to - * if( assign ) mpi_copy( X, Y ); + * if( assign ) esp_mpi_copy( X, Y ); * except that it avoids leaking any information about whether * the assignment was done or not (the above code may leak * information through branch prediction and/or memory access * patterns analysis). */ -int mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ); +int esp_mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ); /** * \brief Safe conditional swap X <-> Y if swap is 1 @@ -235,13 +234,13 @@ int mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ); * ERR_MPI_ALLOC_FAILED if memory allocation failed, * * \note This function is equivalent to - * if( assign ) mpi_swap( X, Y ); + * if( assign ) esp_mpi_swap( X, Y ); * except that it avoids leaking any information about whether * the assignment was done or not (the above code may leak * information through branch prediction and/or memory access * patterns analysis). */ -int mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char assign ); +int esp_mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char assign ); /** * \brief Set value from integer @@ -252,7 +251,7 @@ int mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char assign ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_lset( mpi *X, mpi_sint z ); +int esp_mpi_lset( mpi *X, esp_mpi_sint z ); /** * \brief Get a specific bit from X @@ -262,7 +261,7 @@ int mpi_lset( mpi *X, mpi_sint z ); * * \return Either a 0 or a 1 */ -int mpi_get_bit( const mpi *X, size_t pos ); +int esp_mpi_get_bit( const mpi *X, size_t pos ); /** * \brief Set a bit of X to a specific value of 0 or 1 @@ -278,7 +277,7 @@ int mpi_get_bit( const mpi *X, size_t pos ); * ERR_MPI_ALLOC_FAILED if memory allocation failed, * ERR_MPI_BAD_INPUT_DATA if val is not 0 or 1 */ -int mpi_set_bit( mpi *X, size_t pos, unsigned char val ); +int esp_mpi_set_bit( mpi *X, size_t pos, unsigned char val ); /** * \brief Return the number of zero-bits before the least significant @@ -288,7 +287,7 @@ int mpi_set_bit( mpi *X, size_t pos, unsigned char val ); * * \param X MPI to use */ -size_t mpi_lsb( const mpi *X ); +size_t esp_mpi_lsb( const mpi *X ); /** * \brief Return the number of bits up to and including the most @@ -298,14 +297,14 @@ size_t mpi_lsb( const mpi *X ); * * \param X MPI to use */ -size_t mpi_bitlen( const mpi *X ); +size_t esp_mpi_bitlen( const mpi *X ); /** * \brief Return the total size in bytes * * \param X MPI to use */ -size_t mpi_size( const mpi *X ); +size_t esp_mpi_size( const mpi *X ); /** * \brief Import from an ASCII string @@ -316,7 +315,7 @@ size_t mpi_size( const mpi *X ); * * \return 0 if successful, or a ERR_MPI_XXX error code */ -int mpi_read_string( mpi *X, int radix, const char *s ); +int esp_mpi_read_string( mpi *X, int radix, const char *s ); /** * \brief Export into an ASCII string @@ -334,7 +333,7 @@ int mpi_read_string( mpi *X, int radix, const char *s ); * \note Call this function with buflen = 0 to obtain the * minimum required buffer size in *olen. */ -int mpi_write_string( const mpi *X, int radix, +int esp_mpi_write_string( const mpi *X, int radix, char *buf, size_t buflen, size_t *olen ); #if defined(FS_IO) @@ -349,7 +348,7 @@ int mpi_write_string( const mpi *X, int radix, * the file read buffer is too small or a * ERR_MPI_XXX error code */ -int mpi_read_file( mpi *X, int radix, FILE *fin ); +int esp_mpi_read_file( mpi *X, int radix, FILE *fin ); /** * \brief Write X into an opened file, or stdout if fout is NULL @@ -363,7 +362,7 @@ int mpi_read_file( mpi *X, int radix, FILE *fin ); * * \note Set fout == NULL to print X on the console. */ -int mpi_write_file( const char *p, const mpi *X, int radix, FILE *fout ); +int esp_mpi_write_file( const char *p, const mpi *X, int radix, FILE *fout ); #endif /* FS_IO */ /** @@ -376,7 +375,7 @@ int mpi_write_file( const char *p, const mpi *X, int radix, FILE *fout ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ); +int esp_mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ); /** * \brief Export X into unsigned binary data, big endian. @@ -390,7 +389,7 @@ int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ); * \return 0 if successful, * ERR_MPI_BUFFER_TOO_SMALL if buf isn't large enough */ -int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ); +int esp_mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ); /** * \brief Left-shift: X <<= count @@ -401,7 +400,7 @@ int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_shift_l( mpi *X, size_t count ); +int esp_mpi_shift_l( mpi *X, size_t count ); /** * \brief Right-shift: X >>= count @@ -412,7 +411,7 @@ int mpi_shift_l( mpi *X, size_t count ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_shift_r( mpi *X, size_t count ); +int esp_mpi_shift_r( mpi *X, size_t count ); /** * \brief Compare unsigned values @@ -424,7 +423,7 @@ int mpi_shift_r( mpi *X, size_t count ); * -1 if |X| is lesser than |Y| or * 0 if |X| is equal to |Y| */ -int mpi_cmp_abs( const mpi *X, const mpi *Y ); +int esp_mpi_cmp_abs( const mpi *X, const mpi *Y ); /** * \brief Compare signed values @@ -436,7 +435,7 @@ int mpi_cmp_abs( const mpi *X, const mpi *Y ); * -1 if X is lesser than Y or * 0 if X is equal to Y */ -int mpi_cmp_mpi( const mpi *X, const mpi *Y ); +int esp_mpi_cmp_mpi( const mpi *X, const mpi *Y ); /** * \brief Compare signed values @@ -448,7 +447,7 @@ int mpi_cmp_mpi( const mpi *X, const mpi *Y ); * -1 if X is lesser than z or * 0 if X is equal to z */ -int mpi_cmp_int( const mpi *X, mpi_sint z ); +int esp_mpi_cmp_int( const mpi *X, esp_mpi_sint z ); /** * \brief Unsigned addition: X = |A| + |B| @@ -460,7 +459,7 @@ int mpi_cmp_int( const mpi *X, mpi_sint z ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ); +int esp_mpi_add_abs( mpi *X, const mpi *A, const mpi *B ); /** * \brief Unsigned subtraction: X = |A| - |B| @@ -472,7 +471,7 @@ int mpi_add_abs( mpi *X, const mpi *A, const mpi *B ); * \return 0 if successful, * ERR_MPI_NEGATIVE_VALUE if B is greater than A */ -int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ); +int esp_mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ); /** * \brief Signed addition: X = A + B @@ -484,7 +483,7 @@ int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ); +int esp_mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ); /** * \brief Signed subtraction: X = A - B @@ -496,7 +495,7 @@ int mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ); +int esp_mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ); /** * \brief Signed addition: X = A + b @@ -508,7 +507,7 @@ int mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_add_int( mpi *X, const mpi *A, mpi_sint b ); +int esp_mpi_add_int( mpi *X, const mpi *A, esp_mpi_sint b ); /** * \brief Signed subtraction: X = A - b @@ -520,7 +519,7 @@ int mpi_add_int( mpi *X, const mpi *A, mpi_sint b ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_sub_int( mpi *X, const mpi *A, mpi_sint b ); +int esp_mpi_sub_int( mpi *X, const mpi *A, esp_mpi_sint b ); /** * \brief Baseline multiplication: X = A * B @@ -532,7 +531,7 @@ int mpi_sub_int( mpi *X, const mpi *A, mpi_sint b ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ); +int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ); /** * \brief Baseline multiplication: X = A * b @@ -546,7 +545,7 @@ int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_mul_int( mpi *X, const mpi *A, mpi_uint b ); +int esp_mpi_mul_int( mpi *X, const mpi *A, esp_mpi_uint b ); /** * \brief Division by mpi: A = Q * B + R @@ -562,7 +561,7 @@ int mpi_mul_int( mpi *X, const mpi *A, mpi_uint b ); * * \note Either Q or R can be NULL. */ -int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ); +int esp_mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ); /** * \brief Division by int: A = Q * b + R @@ -578,7 +577,7 @@ int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ); * * \note Either Q or R can be NULL. */ -int mpi_div_int( mpi *Q, mpi *R, const mpi *A, mpi_sint b ); +int esp_mpi_div_int( mpi *Q, mpi *R, const mpi *A, esp_mpi_sint b ); /** * \brief Modulo: R = A mod B @@ -592,12 +591,12 @@ int mpi_div_int( mpi *Q, mpi *R, const mpi *A, mpi_sint b ); * ERR_MPI_DIVISION_BY_ZERO if B == 0, * ERR_MPI_NEGATIVE_VALUE if B < 0 */ -int mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ); +int esp_mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ); /** * \brief Modulo: r = A mod b * - * \param r Destination mpi_uint + * \param r Destination esp_mpi_uint * \param A Left-hand MPI * \param b Integer to divide by * @@ -606,7 +605,7 @@ int mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ); * ERR_MPI_DIVISION_BY_ZERO if b == 0, * ERR_MPI_NEGATIVE_VALUE if b < 0 */ -int mpi_mod_int( mpi_uint *r, const mpi *A, mpi_sint b ); +int esp_mpi_mod_int( esp_mpi_uint *r, const mpi *A, esp_mpi_sint b ); /** * \brief Sliding-window exponentiation: X = A^E mod N @@ -626,7 +625,7 @@ int mpi_mod_int( mpi_uint *r, const mpi *A, mpi_sint b ); * multiple calls, which speeds up things a bit. It can * be set to NULL if the extra performance is unneeded. */ -int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ); +int esp_mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ); /** * \brief Fill an MPI X with size bytes of random @@ -639,7 +638,7 @@ int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ); * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_fill_random( mpi *X, size_t size, +int esp_mpi_fill_random( mpi *X, size_t size, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); @@ -653,7 +652,7 @@ int mpi_fill_random( mpi *X, size_t size, * \return 0 if successful, * ERR_MPI_ALLOC_FAILED if memory allocation failed */ -int mpi_gcd( mpi *G, const mpi *A, const mpi *B ); +int esp_mpi_gcd( mpi *G, const mpi *A, const mpi *B ); /** * \brief Modular inverse: X = A^-1 mod N @@ -667,7 +666,7 @@ int mpi_gcd( mpi *G, const mpi *A, const mpi *B ); * ERR_MPI_BAD_INPUT_DATA if N is negative or nil ERR_MPI_NOT_ACCEPTABLE if A has no inverse mod N */ -int mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ); +int esp_mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ); /** * \brief Miller-Rabin primality test @@ -680,7 +679,7 @@ int mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ); * ERR_MPI_ALLOC_FAILED if memory allocation failed, * ERR_MPI_NOT_ACCEPTABLE if X is not prime */ -int mpi_is_prime( const mpi *X, +int esp_mpi_is_prime( const mpi *X, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); @@ -698,7 +697,7 @@ int mpi_is_prime( const mpi *X, * ERR_MPI_ALLOC_FAILED if memory allocation failed, * ERR_MPI_BAD_INPUT_DATA if nbits is < 3 */ -int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, +int esp_mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); #endif diff --git a/components/esp32/include/esp_thread.h b/components/esp32/include/esp_thread.h new file mode 100644 index 000000000..7716f00f1 --- /dev/null +++ b/components/esp32/include/esp_thread.h @@ -0,0 +1,56 @@ +#ifndef _MULTI_THREAD_H_ +#define _MULTI_THREAD_H_ + +#include "c_types.h" +#include "rom/ets_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum { + AES_MUTEX = 0, + BIGNUM_MUTEX, + SHA_MUTEX, + + MUTEX_MAX_NUM, +}; + +int esp_thread_init(void); + +void esp_thread_lock(unsigned int num); +void esp_thread_unlock(unsigned int num); + +void esp_thread_take(unsigned int num); +void esp_thread_give(unsigned int num); +bool esp_thread_is_used(unsigned int num); + +#define MUTEX_LOCK(num) esp_thread_lock(num) +#define MUTEX_UNLOCK(num) esp_thread_unlock(num) + +#define SIG_TAKE(num) esp_thread_take(num) +#define SIG_GIVE(num) esp_thread_give(num) +#define SIG_IS_USED(num) esp_thread_is_used(num) + +#define AES_LOCK() MUTEX_LOCK(AES_MUTEX) +#define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) +#define BIGNUM_LOCK() MUTEX_LOCK(BIGNUM_MUTEX) +#define BIGNUM_UNLOCK() MUTEX_UNLOCK(BIGNUM_MUTEX) +#define SHA_LOCK() MUTEX_LOCK(SHA_MUTEX) +#define SHA_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) + +#define AES_TAKE() SIG_TAKE(AES_MUTEX) +#define AES_GIVE() SIG_GIVE(AES_MUTEX) +#define AES_IS_USED() SIG_IS_USED(AES_MUTEX) +#define BIGNUM_TAKE() SIG_TAKE(BIGNUM_MUTEX) +#define BIGNUM_GIVE() SIG_GIVE(BIGNUM_MUTEX) +#define BIGNUM_IS_USED() SIG_IS_USED(BIGNUM_MUTEX) +#define SHA_TAKE() SIG_TAKE(SHA_MUTEX) +#define SHA_GIVE() SIG_GIVE(SHA_MUTEX) +#define SHA_IS_USED() SIG_IS_USED(SHA_MUTEX) + +#ifdef __cplusplus +} +#endif + +#endif /* esp_thread.h */ diff --git a/components/esp32/include/sha.h b/components/esp32/include/sha.h new file mode 100644 index 000000000..661354c1d --- /dev/null +++ b/components/esp32/include/sha.h @@ -0,0 +1,224 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ +#ifndef _ESP_SHA_H_ +#define _ESP_SHA_H_ + +#include "c_types.h" +#include "rom/ets_sys.h" +#include "rom/sha.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-1 context structure + */ +typedef struct{ + SHA_CTX context; + int context_type; +} sha_context; + +typedef sha_context SHA1_CTX; + +/** + * \brief Initialize SHA-1 context + * + * \param ctx SHA-1 context to be initialized + */ +void esp_sha1_init( SHA1_CTX *ctx ); + +/** + * \brief Clear SHA-1 context + * + * \param ctx SHA-1 context to be cleared + */ +void esp_sha1_free( SHA1_CTX *ctx ); + +/** + * \brief Clone (the state of) a SHA-1 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ); + +void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]); + +/** + * \brief SHA-1 context setup + * + * \param ctx context to be initialized + */ +void esp_sha1_starts( SHA1_CTX *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ); + +/** + * \brief Output = SHA-1( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + */ +void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ); + +/// +#define SHA256 SHA2_256 +#define SHA224 4 + +/** + * \brief SHA-256 context structure + */ + +typedef sha_context SHA256_CTX; + +/** + * \brief Initialize SHA-256 context + * + * \param ctx SHA-256 context to be initialized + */ +void esp_sha256_init( SHA256_CTX *ctx ); + +/** + * \brief Clear SHA-256 context + * + * \param ctx SHA-256 context to be cleared + */ +void esp_sha256_free( SHA256_CTX *ctx ); +void esp_sha256_process(SHA256_CTX *ctx, const unsigned char data[64]); + +/** + * \brief Clone (the state of) a SHA-256 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ); + +/** + * \brief SHA-256 context setup + * + * \param ctx context to be initialized + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void esp_sha256_starts( SHA256_CTX *ctx, int is224 ); + +/** + * \brief SHA-256 process buffer + * + * \param ctx SHA-256 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-256 final digest + * + * \param ctx SHA-256 context + * \param output SHA-224/256 checksum result + */ +void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ); + +/** + * \brief Output = SHA-256( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-224/256 checksum result + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ); + +// + +/** + * \brief SHA-512 context structure + */ + +typedef sha_context SHA512_CTX; + +/** + * \brief Initialize SHA-512 context + * + * \param ctx SHA-512 context to be initialized + */ +void esp_sha512_init( SHA512_CTX *ctx ); + +/** + * \brief Clear SHA-512 context + * + * \param ctx SHA-512 context to be cleared + */ +void esp_sha512_free( SHA512_CTX *ctx ); + +/** + * \brief Clone (the state of) a SHA-512 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ); + +/** + * \brief SHA-512 context setup + * + * \param ctx context to be initialized + * \param is384 0 = use SHA512, 1 = use SHA384 + */ +void esp_sha512_starts( SHA512_CTX *ctx, int is384 ); + +/** + * \brief SHA-512 process buffer + * + * \param ctx SHA-512 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-512 final digest + * + * \param ctx SHA-512 context + * \param output SHA-384/512 checksum result + */ +void esp_sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ); + +/** + * \brief Output = SHA-512( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-384/512 checksum result + * \param is384 0 = use SHA512, 1 = use SHA384 + */ +void esp_sha512_output( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ); + +// + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/components/esp32/sha.c b/components/esp32/sha.c new file mode 100644 index 000000000..9c28ca9c4 --- /dev/null +++ b/components/esp32/sha.c @@ -0,0 +1,285 @@ +/* + * FIPS-180-1 compliant SHA-1 implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ + +#include "sha.h" + +#include +#include "esp_thread.h" + +/* Implementation that should never be optimized out by the compiler */ +static void esp_sha_zeroize( void *v, size_t n ) { + volatile unsigned char *p = v; while( n-- ) *p++ = 0; +} + +void esp_sha1_init( SHA1_CTX *ctx ) +{ + memset( ctx, 0, sizeof( SHA1_CTX ) ); + + SHA_LOCK(); + SHA_TAKE(); + ets_sha_enable(); + SHA_UNLOCK(); +} + +void esp_sha1_free( SHA1_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + esp_sha_zeroize( ctx, sizeof( SHA1_CTX ) ); + + SHA_LOCK(); + SHA_GIVE(); + if (false == SHA_IS_USED()) + ets_sha_disable(); + SHA_UNLOCK(); +} + +void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) +{ + *dst = *src; +} + +void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) +{ + +} + +/* + * SHA-1 context setup + */ +void esp_sha1_starts( SHA1_CTX *ctx ) +{ + SHA_LOCK(); + ets_sha_init(&ctx->context); + SHA_UNLOCK(); + + ctx->context_type = SHA1; +} + +/* + * SHA-1 process buffer + */ +void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) +{ + SHA_LOCK(); + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); +} + +/* + * SHA-1 final digest + */ +void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) +{ + ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA_UNLOCK(); +} + +/* + * output = SHA-1( input buffer ) + */ +void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ) +{ + SHA1_CTX ctx; + + esp_sha1_init( &ctx ); + esp_sha1_starts( &ctx ); + esp_sha1_update( &ctx, input, ilen ); + esp_sha1_finish( &ctx, output ); + esp_sha1_free( &ctx ); +} + +///// +/* Implementation that should never be optimized out by the compiler */ +void esp_sha256_init( SHA256_CTX *ctx ) +{ + memset( ctx, 0, sizeof( SHA256_CTX ) ); + + SHA_LOCK(); + SHA_TAKE(); + ets_sha_enable(); + SHA_UNLOCK(); +} + +void esp_sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) +{ + +} + +void esp_sha256_free( SHA256_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + esp_sha_zeroize( ctx, sizeof( SHA256_CTX ) ); + + SHA_LOCK(); + SHA_GIVE(); + if (false == SHA_IS_USED()) + ets_sha_disable(); + SHA_UNLOCK(); +} + +void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) +{ + *dst = *src; +} + +/* + * SHA-256 context setup + */ +void esp_sha256_starts( SHA256_CTX *ctx, int is224 ) +{ + SHA_LOCK(); + ets_sha_init(&ctx->context); + SHA_UNLOCK(); + + if( is224 == 0 ) + { + /* SHA-256 */ + ctx->context_type = SHA256; + }else{ + /* SHA-224 */ + ctx->context_type = SHA224; + } +} + +/* + * SHA-256 process buffer + */ +void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) +{ + SHA_LOCK(); + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); +} + +/* + * SHA-256 final digest + */ +void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) +{ + ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA_UNLOCK(); +} + +/* + * output = SHA-256( input buffer ) + */ +void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ) +{ + SHA256_CTX ctx; + + esp_sha256_init( &ctx ); + esp_sha256_starts( &ctx, is224 ); + esp_sha256_update( &ctx, input, ilen ); + esp_sha256_finish( &ctx, output ); + esp_sha256_free( &ctx ); +} + + +///// +void esp_sha512_init( SHA512_CTX *ctx ) +{ + memset( ctx, 0, sizeof( SHA512_CTX ) ); + + SHA_LOCK(); + SHA_TAKE(); + ets_sha_enable(); + SHA_UNLOCK(); +} + +void esp_sha512_free( SHA512_CTX *ctx ) +{ + if( ctx == NULL ) + return; + + esp_sha_zeroize( ctx, sizeof( SHA512_CTX ) ); + + SHA_LOCK(); + SHA_GIVE(); + if (false == SHA_IS_USED()) + ets_sha_disable(); + SHA_UNLOCK(); +} + +void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) +{ + *dst = *src; +} + +/* + * SHA-512 context setup + */ +void esp_sha512_starts( SHA512_CTX *ctx, int is384 ) +{ + SHA_LOCK(); + ets_sha_init(&ctx->context); + SHA_UNLOCK(); + if( is384 == 0 ) + { + /* SHA-512 */ + ctx->context_type = SHA2_512; + } + else + { + /* SHA-384 */ + ctx->context_type = SHA2_384; + } +} + +/* + * SHA-512 process buffer + */ +void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) +{ + SHA_LOCK(); + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); +} + +/* + * SHA-512 final digest + */ +void esp_sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) +{ + ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA_UNLOCK(); +} + +/* + * output = SHA-512( input buffer ) + */ +void esp_sha512_output( const unsigned char *input, size_t ilen,unsigned char output[64], int is384 ) +{ + SHA512_CTX ctx; + + esp_sha512_init( &ctx ); + esp_sha512_starts( &ctx, is384 ); + esp_sha512_update( &ctx, input, ilen ); + esp_sha512_finish( &ctx, output ); + esp_sha512_free( &ctx ); +} + +//// + diff --git a/components/mbedtls/Makefile b/components/mbedtls/Makefile old mode 100755 new mode 100644 diff --git a/components/mbedtls/include/mbedtls/aes.h b/components/mbedtls/include/mbedtls/aes.h index f5e1600b3..a36e825a2 100644 --- a/components/mbedtls/include/mbedtls/aes.h +++ b/components/mbedtls/include/mbedtls/aes.h @@ -276,27 +276,7 @@ void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, #endif #else /* MBEDTLS_AES_ALT */ -#include "port/aes_alt.h" - -typedef AES_CTX mbedtls_aes_context; - -#define mbedtls_aes_init aes_init -#define mbedtls_aes_free aes_free -#define mbedtls_aes_setkey_enc aes_setkey_enc -#define mbedtls_aes_setkey_dec aes_setkey_dec -#define mbedtls_aes_crypt_ecb aes_crypt_ecb -#if defined(MBEDTLS_CIPHER_MODE_CBC) -#define mbedtls_aes_crypt_cbc aes_crypt_cbc -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) -#define mbedtls_aes_crypt_cfb128 aes_crypt_cfb128 -#define mbedtls_aes_crypt_cfb8 aes_crypt_cfb8 -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) -#define mbedtls_aes_crypt_ctr aes_crypt_ctr -#endif -#define mbedtls_aes_encrypt aes_encrypt -#define mbedtls_aes_decrypt aes_decrypt +#include "aes_alt.h" #endif /* MBEDTLS_AES_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/mbedtls/bignum.h b/components/mbedtls/include/mbedtls/bignum.h index d062a7511..46f250762 100644 --- a/components/mbedtls/include/mbedtls/bignum.h +++ b/components/mbedtls/include/mbedtls/bignum.h @@ -705,52 +705,7 @@ int mbedtls_mpi_gen_prime( mbedtls_mpi *X, size_t nbits, int dh_flag, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); #else /* MBEDTLS_BIGNUM_ALT */ -#include "port/bignum_alt.h" - -typedef mpi mbedtls_mpi; - -#define mbedtls_mpi_init mpi_init -#define mbedtls_mpi_free mpi_free -#define mbedtls_mpi_grow mpi_grow -#define mbedtls_mpi_shrink mpi_shrink -#define mbedtls_mpi_copy mpi_copy -#define mbedtls_mpi_swap mpi_swap -#define mbedtls_mpi_safe_cond_assign mpi_safe_cond_assign -#define mbedtls_mpi_safe_cond_swap mpi_safe_cond_swap -#define mbedtls_mpi_lset mpi_lset -#define mbedtls_mpi_get_bit mpi_get_bit -#define mbedtls_mpi_set_bit mpi_set_bit -#define mbedtls_mpi_lsb mpi_lsb -#define mbedtls_mpi_bitlen mpi_bitlen -#define mbedtls_mpi_size mpi_size -#define mbedtls_mpi_read_string mpi_read_string -#define mbedtls_mpi_write_string mpi_write_string -#define mbedtls_mpi_read_binary mpi_read_binary -#define mbedtls_mpi_write_binary mpi_write_binary -#define mbedtls_mpi_shift_l mpi_shift_l -#define mbedtls_mpi_shift_r mpi_shift_r -#define mbedtls_mpi_cmp_abs mpi_cmp_abs -#define mbedtls_mpi_cmp_mpi mpi_cmp_mpi -#define mbedtls_mpi_cmp_int mpi_cmp_int -#define mbedtls_mpi_add_abs mpi_add_abs -#define mbedtls_mpi_sub_abs mpi_sub_abs -#define mbedtls_mpi_add_mpi mpi_add_mpi -#define mbedtls_mpi_sub_mpi mpi_sub_mpi -#define mbedtls_mpi_add_int mpi_add_int -#define mbedtls_mpi_sub_int mpi_sub_int -#define mbedtls_mpi_mul_mpi mpi_mul_mpi -#define mbedtls_mpi_mul_int mpi_mul_int -#define mbedtls_mpi_div_mpi mpi_div_mpi -#define mbedtls_mpi_div_int mpi_div_int -#define mbedtls_mpi_mod_mpi mpi_mod_mpi -#define mbedtls_mpi_mod_int mpi_mod_int -#define mbedtls_mpi_exp_mod mpi_exp_mod -#define mbedtls_mpi_fill_random mpi_fill_random -#define mbedtls_mpi_gcd mpi_gcd -#define mbedtls_mpi_inv_mod mpi_inv_mod -#define mbedtls_mpi_is_prime mpi_is_prime -#define mbedtls_mpi_gen_prime mpi_gen_prime - +#include "bignum_alt.h" #endif /* MBEDTLS_BIGNUM_ALT */ /** diff --git a/components/mbedtls/include/mbedtls/esp_config.h b/components/mbedtls/include/mbedtls/esp_config.h index 614e8018b..1ea607681 100644 --- a/components/mbedtls/include/mbedtls/esp_config.h +++ b/components/mbedtls/include/mbedtls/esp_config.h @@ -2466,8 +2466,7 @@ //#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ /* SSL options */ -extern unsigned int max_content_len; -#define MBEDTLS_SSL_MAX_CONTENT_LEN max_content_len /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */ +#define MBEDTLS_SSL_MAX_CONTENT_LEN 3072 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */ //#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */ //#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */ //#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ diff --git a/components/mbedtls/include/mbedtls/sha1.h b/components/mbedtls/include/mbedtls/sha1.h index 2d85a59f7..7a67c6c1f 100644 --- a/components/mbedtls/include/mbedtls/sha1.h +++ b/components/mbedtls/include/mbedtls/sha1.h @@ -106,17 +106,7 @@ void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[6 #endif #else /* MBEDTLS_SHA1_ALT */ -#include "port/sha1_alt.h" - -typedef SHA1_CTX mbedtls_sha1_context; - -#define mbedtls_sha1_init sha1_init -#define mbedtls_sha1_starts sha1_starts -#define mbedtls_sha1_clone sha1_clone -#define mbedtls_sha1_update sha1_update -#define mbedtls_sha1_finish sha1_finish -#define mbedtls_sha1_free sha1_free -#define mbedtls_sha1_process sha1_process +#include "sha1_alt.h" #endif /* MBEDTLS_SHA1_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/mbedtls/sha256.h b/components/mbedtls/include/mbedtls/sha256.h index 4ab444e8d..f8041adf0 100644 --- a/components/mbedtls/include/mbedtls/sha256.h +++ b/components/mbedtls/include/mbedtls/sha256.h @@ -109,17 +109,7 @@ void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char da #endif #else /* MBEDTLS_SHA256_ALT */ -#include "port/sha256_alt.h" - -typedef SHA256_CTX mbedtls_sha256_context; - -#define mbedtls_sha256_init sha256_init -#define mbedtls_sha256_clone sha256_clone -#define mbedtls_sha256_starts sha256_starts -#define mbedtls_sha256_update sha256_update -#define mbedtls_sha256_finish sha256_finish -#define mbedtls_sha256_free sha256_free -#define mbedtls_sha256_process sha256_process +#include "sha256_alt.h" #endif /* MBEDTLS_SHA256_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/mbedtls/sha512.h b/components/mbedtls/include/mbedtls/sha512.h index 0ebc092f4..627694f42 100644 --- a/components/mbedtls/include/mbedtls/sha512.h +++ b/components/mbedtls/include/mbedtls/sha512.h @@ -106,17 +106,7 @@ void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, unsigned char output[64 #endif #else /* MBEDTLS_SHA512_ALT */ -#include "port/sha512_alt.h" - -typedef SHA512_CTX mbedtls_sha512_context; - -#define mbedtls_sha512_init sha512_init -#define mbedtls_sha512_clone sha512_clone -#define mbedtls_sha512_starts sha512_starts -#define mbedtls_sha512_update sha512_update -#define mbedtls_sha512_finish sha512_finish -#define mbedtls_sha512_free sha512_free - +#include "sha512_alt.h" #endif /* MBEDTLS_SHA512_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/include/port/multi_thread.h b/components/mbedtls/include/port/multi_thread.h deleted file mode 100644 index 6732eedde..000000000 --- a/components/mbedtls/include/port/multi_thread.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef _MULTI_THREAD_H_ -#define _MULTI_THREAD_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -enum { - AES_MUTEX = 0, - BIGNUM_MUTEX, - SHA_MUTEX, - - MUTEX_MAX_NUM, -}; - -int multi_thread_init(void); - -void multi_thread_lock(unsigned int num); -void multi_thread_unlock(unsigned int num); - -void multi_thread_take(unsigned int num); -void multi_thread_give(unsigned int num); -bool multi_thread_is_used(num); - -#define MUTEX_LOCK(num) multi_thread_lock(num) -#define MUTEX_UNLOCK(num) multi_thread_unlock(num) - -#define SIG_TAKE(num) multi_thread_take(num) -#define SIG_GIVE(num) multi_thread_give(num) -#define SIG_IS_USED(num) multi_thread_is_used(num) - -#define AES_LOCK() MUTEX_LOCK(AES_MUTEX) -#define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) -#define BIGNUM_LOCK() MUTEX_LOCK(BIGNUM_MUTEX) -#define BIGNUM_UNLOCK() MUTEX_UNLOCK(BIGNUM_MUTEX) -#define SHA1_LOCK() MUTEX_LOCK(SHA_MUTEX) -#define SHA1_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) -#define SHA256_LOCK() MUTEX_LOCK(SHA_MUTEX) -#define SHA256_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) -#define SHA512_LOCK() MUTEX_LOCK(SHA_MUTEX) -#define SHA512_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) - -#define AES_TAKE() SIG_TAKE(AES_MUTEX) -#define AES_GIVE() SIG_GIVE(AES_MUTEX) -#define AES_IS_USED() SIG_IS_USED(AES_MUTEX) -#define BIGNUM_TAKE() SIG_TAKE(BIGNUM_MUTEX) -#define BIGNUM_GIVE() SIG_GIVE(BIGNUM_MUTEX) -#define BIGNUM_IS_USED() SIG_IS_USED(BIGNUM_MUTEX) -#define SHA1_TAKE() SIG_TAKE(SHA_MUTEX) -#define SHA1_GIVE() SIG_GIVE(SHA_MUTEX) -#define SHA1_IS_USED() SIG_IS_USED(SHA_MUTEX) -#define SHA256_TAKE() SIG_TAKE(SHA_MUTEX) -#define SHA256_GIVE() SIG_GIVE(SHA_MUTEX) -#define SHA256_IS_USED() SIG_IS_USED(SHA_MUTEX) -#define SHA512_TAKE() SIG_TAKE(SHA_MUTEX) -#define SHA512_GIVE() SIG_GIVE(SHA_MUTEX) -#define SHA512_IS_USED() SIG_IS_USED(SHA_MUTEX) - -#ifdef __cplusplus -} -#endif - -#endif /* multi_thread.h */ diff --git a/components/mbedtls/include/port/sha1_alt.h b/components/mbedtls/include/port/sha1_alt.h deleted file mode 100644 index 918798627..000000000 --- a/components/mbedtls/include/port/sha1_alt.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * - * esf Link List Descriptor - */ -#ifndef _SHA1_H_ -#define _SHA1_H_ - -#include "c_types.h" -#include "rom/ets_sys.h" -#include "rom/sha.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ESP_SHA1_C - -#define SHA1 0 - -/** - * \brief SHA-1 context structure - */ -typedef struct{ - SHA_CTX context; - int context_type; -} sha1_context; - -typedef sha1_context SHA1_CTX; - -/** - * \brief Initialize SHA-1 context - * - * \param ctx SHA-1 context to be initialized - */ -void sha1_init( SHA1_CTX *ctx ); - -/** - * \brief Clear SHA-1 context - * - * \param ctx SHA-1 context to be cleared - */ -void sha1_free( SHA1_CTX *ctx ); - -/** - * \brief Clone (the state of) a SHA-1 context - * - * \param dst The destination context - * \param src The context to be cloned - */ -void sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ); - -void sha1_process(SHA1_CTX *ctx, const unsigned char data[64]); - -/** - * \brief SHA-1 context setup - * - * \param ctx context to be initialized - */ -void sha1_starts( SHA1_CTX *ctx ); - -/** - * \brief SHA-1 process buffer - * - * \param ctx SHA-1 context - * \param input buffer holding the data - * \param ilen length of the input data - */ -void sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ); - -/** - * \brief SHA-1 final digest - * - * \param ctx SHA-1 context - * \param output SHA-1 checksum result - */ -void sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ); - -/** - * \brief Output = SHA-1( input buffer ) - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output SHA-1 checksum result - */ -void sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/components/mbedtls/include/port/sha256_alt.h b/components/mbedtls/include/port/sha256_alt.h deleted file mode 100644 index bc661d393..000000000 --- a/components/mbedtls/include/port/sha256_alt.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * - * esf Link List Descriptor - */ - -#ifndef _SHA256_H_ -#define _SHA256_H_ - -#include "c_types.h" -#include "rom/ets_sys.h" -#include "rom/sha.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ESP_SHA256_C - -#define SHA256 SHA2_256 -#define SHA224 4 - -/** - * \brief SHA-256 context structure - */ -typedef struct{ - SHA_CTX context; - int context_type; -}sha256_context; - -typedef sha256_context SHA256_CTX; - -/** - * \brief Initialize SHA-256 context - * - * \param ctx SHA-256 context to be initialized - */ -void sha256_init( SHA256_CTX *ctx ); - -/** - * \brief Clear SHA-256 context - * - * \param ctx SHA-256 context to be cleared - */ -void sha256_free( SHA256_CTX *ctx ); -void sha256_process(SHA256_CTX *ctx, const unsigned char data[64]); - -/** - * \brief Clone (the state of) a SHA-256 context - * - * \param dst The destination context - * \param src The context to be cloned - */ -void sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ); - -/** - * \brief SHA-256 context setup - * - * \param ctx context to be initialized - * \param is224 0 = use SHA256, 1 = use SHA224 - */ -void sha256_starts( SHA256_CTX *ctx, int is224 ); - -/** - * \brief SHA-256 process buffer - * - * \param ctx SHA-256 context - * \param input buffer holding the data - * \param ilen length of the input data - */ -void sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ); - -/** - * \brief SHA-256 final digest - * - * \param ctx SHA-256 context - * \param output SHA-224/256 checksum result - */ -void sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ); - -/** - * \brief Output = SHA-256( input buffer ) - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output SHA-224/256 checksum result - * \param is224 0 = use SHA256, 1 = use SHA224 - */ -void sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ); - -#ifdef __cplusplus -} -#endif - -#endif /* sha256.h */ diff --git a/components/mbedtls/include/port/sha512_alt.h b/components/mbedtls/include/port/sha512_alt.h deleted file mode 100644 index a3e1c50c6..000000000 --- a/components/mbedtls/include/port/sha512_alt.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * - * esf Link List Descriptor - */ - -#ifndef _SHA512_H_ -#define _SHA512_H_ - -#include "c_types.h" -#include "rom/ets_sys.h" -#include "rom/sha.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define ESP_SHA512_C - -/** - * \brief SHA-512 context structure - */ -typedef struct{ - SHA_CTX context; - int context_type; -}sha512_context; - -typedef sha512_context SHA512_CTX; - -/** - * \brief Initialize SHA-512 context - * - * \param ctx SHA-512 context to be initialized - */ -void sha512_init( SHA512_CTX *ctx ); - -/** - * \brief Clear SHA-512 context - * - * \param ctx SHA-512 context to be cleared - */ -void sha512_free( SHA512_CTX *ctx ); - -/** - * \brief Clone (the state of) a SHA-512 context - * - * \param dst The destination context - * \param src The context to be cloned - */ -void sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ); - -/** - * \brief SHA-512 context setup - * - * \param ctx context to be initialized - * \param is384 0 = use SHA512, 1 = use SHA384 - */ -void sha512_starts( SHA512_CTX *ctx, int is384 ); - -/** - * \brief SHA-512 process buffer - * - * \param ctx SHA-512 context - * \param input buffer holding the data - * \param ilen length of the input data - */ -void sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen ); - -/** - * \brief SHA-512 final digest - * - * \param ctx SHA-512 context - * \param output SHA-384/512 checksum result - */ -void sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ); - -/** - * \brief Output = SHA-512( input buffer ) - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output SHA-384/512 checksum result - * \param is384 0 = use SHA512, 1 = use SHA384 - */ -void sha512_output( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ); - - -#ifdef __cplusplus -} -#endif - -#endif /* sha512.h */ diff --git a/components/mbedtls/port/include/aes_alt.h b/components/mbedtls/port/include/aes_alt.h new file mode 100644 index 000000000..90e659483 --- /dev/null +++ b/components/mbedtls/port/include/aes_alt.h @@ -0,0 +1,59 @@ +/** + * \file aes_alt.h + * + * \brief AES block cipher + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef AES_ALT_H +#define AES_ALT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_AES_ALT) +#include "aes.h" + +typedef AES_CTX mbedtls_aes_context; + +#define mbedtls_aes_init esp_aes_init +#define mbedtls_aes_free esp_aes_free +#define mbedtls_aes_setkey_enc esp_aes_setkey_enc +#define mbedtls_aes_setkey_dec esp_aes_setkey_dec +#define mbedtls_aes_crypt_ecb esp_aes_crypt_ecb +#if defined(MBEDTLS_CIPHER_MODE_CBC) +#define mbedtls_aes_crypt_cbc esp_aes_crypt_cbc +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) +#define mbedtls_aes_crypt_cfb128 esp_aes_crypt_cfb128 +#define mbedtls_aes_crypt_cfb8 esp_aes_crypt_cfb8 +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) +#define mbedtls_aes_crypt_ctr esp_aes_crypt_ctr +#endif +#define mbedtls_aes_encrypt esp_aes_encrypt +#define mbedtls_aes_decrypt esp_aes_decrypt +#endif /* MBEDTLS_AES_ALT */ + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/components/mbedtls/port/include/bignum_alt.h b/components/mbedtls/port/include/bignum_alt.h new file mode 100644 index 000000000..a4ac0db3e --- /dev/null +++ b/components/mbedtls/port/include/bignum_alt.h @@ -0,0 +1,77 @@ +/** + * \file bignum_alt.h + * + * \brief Multi-precision integer library + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef BIGNUM_ALT_H +#define BIGNUM_ALT_H + +#include "bignum.h" + +#if defined(MBEDTLS_BIGNUM_ALT) + +typedef MPI_CTX mbedtls_mpi; + +#define mbedtls_mpi_init esp_mpi_init +#define mbedtls_mpi_free esp_mpi_free +#define mbedtls_mpi_grow esp_mpi_grow +#define mbedtls_mpi_shrink esp_mpi_shrink +#define mbedtls_mpi_copy esp_mpi_copy +#define mbedtls_mpi_swap esp_mpi_swap +#define mbedtls_mpi_safe_cond_assign esp_mpi_safe_cond_assign +#define mbedtls_mpi_safe_cond_swap esp_mpi_safe_cond_swap +#define mbedtls_mpi_lset esp_mpi_lset +#define mbedtls_mpi_get_bit esp_mpi_get_bit +#define mbedtls_mpi_set_bit esp_mpi_set_bit +#define mbedtls_mpi_lsb esp_mpi_lsb +#define mbedtls_mpi_bitlen esp_mpi_bitlen +#define mbedtls_mpi_size esp_mpi_size +#define mbedtls_mpi_read_string esp_mpi_read_string +#define mbedtls_mpi_write_string esp_mpi_write_string +#define mbedtls_mpi_read_binary esp_mpi_read_binary +#define mbedtls_mpi_write_binary esp_mpi_write_binary +#define mbedtls_mpi_shift_l esp_mpi_shift_l +#define mbedtls_mpi_shift_r esp_mpi_shift_r +#define mbedtls_mpi_cmp_abs esp_mpi_cmp_abs +#define mbedtls_mpi_cmp_mpi esp_mpi_cmp_mpi +#define mbedtls_mpi_cmp_int esp_mpi_cmp_int +#define mbedtls_mpi_add_abs esp_mpi_add_abs +#define mbedtls_mpi_sub_abs esp_mpi_sub_abs +#define mbedtls_mpi_add_mpi esp_mpi_add_mpi +#define mbedtls_mpi_sub_mpi esp_mpi_sub_mpi +#define mbedtls_mpi_add_int esp_mpi_add_int +#define mbedtls_mpi_sub_int esp_mpi_sub_int +#define mbedtls_mpi_mul_mpi esp_mpi_mul_mpi +#define mbedtls_mpi_mul_int esp_mpi_mul_int +#define mbedtls_mpi_div_mpi esp_mpi_div_mpi +#define mbedtls_mpi_div_int esp_mpi_div_int +#define mbedtls_mpi_mod_mpi esp_mpi_mod_mpi +#define mbedtls_mpi_mod_int esp_mpi_mod_int +#define mbedtls_mpi_exp_mod esp_mpi_exp_mod +#define mbedtls_mpi_fill_random esp_mpi_fill_random +#define mbedtls_mpi_gcd esp_mpi_gcd +#define mbedtls_mpi_inv_mod esp_mpi_inv_mod +#define mbedtls_mpi_is_prime esp_mpi_is_prime +#define mbedtls_mpi_gen_prime esp_mpi_gen_prime + +#endif + +#endif + diff --git a/components/mbedtls/port/include/sha1_alt.h b/components/mbedtls/port/include/sha1_alt.h new file mode 100644 index 000000000..2cb0e926d --- /dev/null +++ b/components/mbedtls/port/include/sha1_alt.h @@ -0,0 +1,34 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ +#ifndef _SHA1_ALT_H_ +#define _SHA1_ALT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_SHA1_ALT) + +#include "sha.h" + +typedef SHA1_CTX mbedtls_sha1_context; + +#define mbedtls_sha1_init esp_sha1_init +#define mbedtls_sha1_starts esp_sha1_starts +#define mbedtls_sha1_clone esp_sha1_clone +#define mbedtls_sha1_update esp_sha1_update +#define mbedtls_sha1_finish esp_sha1_finish +#define mbedtls_sha1_free esp_sha1_free +#define mbedtls_sha1_process esp_sha1_process + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/components/mbedtls/port/include/sha256_alt.h b/components/mbedtls/port/include/sha256_alt.h new file mode 100644 index 000000000..00beb2d28 --- /dev/null +++ b/components/mbedtls/port/include/sha256_alt.h @@ -0,0 +1,34 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ + +#ifndef _SHA256_ALT_H_ +#define _SHA256_ALT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_SHA256_ALT) + +#include "sha.h" + +typedef SHA256_CTX mbedtls_sha256_context; + +#define mbedtls_sha256_init esp_sha256_init +#define mbedtls_sha256_clone esp_sha256_clone +#define mbedtls_sha256_starts esp_sha256_starts +#define mbedtls_sha256_update esp_sha256_update +#define mbedtls_sha256_finish esp_sha256_finish +#define mbedtls_sha256_free esp_sha256_free +#define mbedtls_sha256_process esp_sha256_process + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* sha256.h */ diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h new file mode 100644 index 000000000..b4e17259e --- /dev/null +++ b/components/mbedtls/port/include/sha512_alt.h @@ -0,0 +1,32 @@ +/* + * copyright (c) 2010 - 2012 Espressif System + * + * esf Link List Descriptor + */ + +#ifndef _SHA512_ALT_H_ +#define _SHA512_ALT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_SHA512_ALT) +#include "sha.h" + +typedef SHA512_CTX mbedtls_sha512_context; + +#define mbedtls_sha512_init esp_sha512_init +#define mbedtls_sha512_clone esp_sha512_clone +#define mbedtls_sha512_starts esp_sha512_starts +#define mbedtls_sha512_update esp_sha512_update +#define mbedtls_sha512_finish esp_sha512_finish +#define mbedtls_sha512_free esp_sha512_free + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* sha512.h */ diff --git a/components/mbedtls/port/multi_thread.c b/components/mbedtls/port/multi_thread.c deleted file mode 100644 index 31cf1ea6d..000000000 --- a/components/mbedtls/port/multi_thread.c +++ /dev/null @@ -1,53 +0,0 @@ -#include "multi_thread.h" -#include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" - -static xSemaphoreHandle multi_thread_mutex[MUTEX_MAX_NUM]; -static int multi_thread_sig[MUTEX_MAX_NUM]; - -int multi_thread_init(void) -{ - int i; - - for (i = 0; i < MUTEX_MAX_NUM; i++) { - multi_thread_mutex[i] = xSemaphoreCreateMutex(); - if (!multi_thread_mutex[i]) { - goto failed1; - } - multi_thread_sig[i] = 0; - } - - return 0; - -failed1: - for (i--; i >= 0; i--) - vQueueDelete(multi_thread_mutex[i]); - - return -1; -} - -void multi_thread_lock(unsigned int num) -{ - xSemaphoreTake(multi_thread_mutex[num], portMAX_DELAY); -} - -void multi_thread_unlock(unsigned int num) -{ - xSemaphoreGive(multi_thread_mutex[num]); -} - -void multi_thread_take(unsigned int num) -{ - multi_thread_sig[num]++; -} - -void multi_thread_give(unsigned int num) -{ - multi_thread_sig[num]--; -} - -bool multi_thread_is_used(num) -{ - return (multi_thread_sig[num] != 0) ? true : false; -} - diff --git a/components/mbedtls/port/sha1_alt.c b/components/mbedtls/port/sha1_alt.c deleted file mode 100644 index b73d03ffa..000000000 --- a/components/mbedtls/port/sha1_alt.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * FIPS-180-1 compliant SHA-1 implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ -/* - * The SHA-1 standard was published by NIST in 1993. - * - * http://www.itl.nist.gov/fipspubs/fip180-1.htm - */ - -#include "port/sha1_alt.h" - -#if defined(ESP_SHA1_C) -#include -#include "multi_thread.h" - -/* Implementation that should never be optimized out by the compiler */ -static void sha1_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; -} - -void sha1_init( SHA1_CTX *ctx ) -{ - memset( ctx, 0, sizeof( SHA1_CTX ) ); - - SHA1_LOCK(); - SHA1_TAKE(); - ets_sha_enable(); - SHA1_UNLOCK(); -} - -void sha1_free( SHA1_CTX *ctx ) -{ - if( ctx == NULL ) - return; - - sha1_zeroize( ctx, sizeof( SHA1_CTX ) ); - - SHA1_LOCK(); - SHA1_GIVE(); - if (false == SHA1_IS_USED()) - ets_sha_disable(); - SHA1_UNLOCK(); -} - -void sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) -{ - *dst = *src; -} - -void sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) -{ - -} - -/* - * SHA-1 context setup - */ -void sha1_starts( SHA1_CTX *ctx ) -{ - SHA1_LOCK(); - ets_sha_init(&ctx->context); - SHA1_UNLOCK(); - - ctx->context_type = SHA1; -} - -/* - * SHA-1 process buffer - */ -void sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) -{ - SHA1_LOCK(); - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); -} - -/* - * SHA-1 final digest - */ -void sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) -{ - ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA1_UNLOCK(); -} - -/* - * output = SHA-1( input buffer ) - */ -void sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ) -{ - SHA1_CTX ctx; - - sha1_init( &ctx ); - sha1_starts( &ctx ); - sha1_update( &ctx, input, ilen ); - sha1_finish( &ctx, output ); - sha1_free( &ctx ); -} - -#endif /* _SHA1_C */ - - diff --git a/components/mbedtls/port/sha256_alt.c b/components/mbedtls/port/sha256_alt.c deleted file mode 100644 index fc8769d1b..000000000 --- a/components/mbedtls/port/sha256_alt.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * FIPS-180-2 compliant SHA-256 implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ -/* - * The SHA-256 Secure Hash Standard was published by NIST in 2002. - * - * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf - */ - -#include "port/sha256_alt.h" - -#if defined(ESP_SHA256_C) -#include -#include "multi_thread.h" - -/* Implementation that should never be optimized out by the compiler */ -static void sha256_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; -} - -void sha256_init( SHA256_CTX *ctx ) -{ - memset( ctx, 0, sizeof( SHA256_CTX ) ); - - SHA256_LOCK(); - SHA256_TAKE(); - ets_sha_enable(); - SHA256_UNLOCK(); -} - -void sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) -{ - -} - -void sha256_free( SHA256_CTX *ctx ) -{ - if( ctx == NULL ) - return; - - sha256_zeroize( ctx, sizeof( SHA256_CTX ) ); - - SHA256_LOCK(); - SHA256_GIVE(); - if (false == SHA256_IS_USED()) - ets_sha_disable(); - SHA256_UNLOCK(); -} - -void sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) -{ - *dst = *src; -} - -/* - * SHA-256 context setup - */ -void sha256_starts( SHA256_CTX *ctx, int is224 ) -{ - SHA256_LOCK(); - ets_sha_init(&ctx->context); - SHA256_UNLOCK(); - - if( is224 == 0 ) - { - /* SHA-256 */ - ctx->context_type = SHA256; - }else{ - /* SHA-224 */ - ctx->context_type = SHA224; - } -} - -/* - * SHA-256 process buffer - */ -void sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) -{ - SHA256_LOCK(); - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); -} - -/* - * SHA-256 final digest - */ -void sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) -{ - ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA256_UNLOCK(); -} - -/* - * output = SHA-256( input buffer ) - */ -void sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ) -{ - SHA256_CTX ctx; - - sha256_init( &ctx ); - sha256_starts( &ctx, is224 ); - sha256_update( &ctx, input, ilen ); - sha256_finish( &ctx, output ); - sha256_free( &ctx ); -} - -#endif /* SHA256_C */ diff --git a/components/mbedtls/port/sha512_alt.c b/components/mbedtls/port/sha512_alt.c deleted file mode 100644 index 02d315681..000000000 --- a/components/mbedtls/port/sha512_alt.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * FIPS-180-2 compliant SHA-384/512 implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ -/* - * The SHA-512 Secure Hash Standard was published by NIST in 2002. - * - * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf - */ -#include "port/sha512_alt.h" - -#if defined(ESP_SHA512_C) -#include -#include "multi_thread.h" - -/* Implementation that should never be optimized out by the compiler */ -static void sha512_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; -} - -void sha512_init( SHA512_CTX *ctx ) -{ - memset( ctx, 0, sizeof( SHA512_CTX ) ); - - SHA512_LOCK(); - SHA512_TAKE(); - ets_sha_enable(); - SHA512_UNLOCK(); -} - -void sha512_free( SHA512_CTX *ctx ) -{ - if( ctx == NULL ) - return; - - sha512_zeroize( ctx, sizeof( SHA512_CTX ) ); - - SHA512_LOCK(); - SHA512_GIVE(); - if (false == SHA512_IS_USED()) - ets_sha_disable(); - SHA512_UNLOCK(); -} - -void sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) -{ - *dst = *src; -} - -/* - * SHA-512 context setup - */ -void sha512_starts( SHA512_CTX *ctx, int is384 ) -{ - SHA512_LOCK(); - ets_sha_init(&ctx->context); - SHA512_UNLOCK(); - if( is384 == 0 ) - { - /* SHA-512 */ - ctx->context_type = SHA2_512; - } - else - { - /* SHA-384 */ - ctx->context_type = SHA2_384; - } -} - -/* - * SHA-512 process buffer - */ -void sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) -{ - SHA512_LOCK(); - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); -} - -/* - * SHA-512 final digest - */ -void sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) -{ - ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA512_UNLOCK(); -} - -/* - * output = SHA-512( input buffer ) - */ -void sha512_output( const unsigned char *input, size_t ilen,unsigned char output[64], int is384 ) -{ - SHA512_CTX ctx; - - sha512_init( &ctx ); - sha512_starts( &ctx, is384 ); - sha512_update( &ctx, input, ilen ); - sha512_finish( &ctx, output ); - sha512_free( &ctx ); -} - -#endif /* SHA512_C */ From 0f83831c743801960242525bc19ed15383e091e7 Mon Sep 17 00:00:00 2001 From: liuhan Date: Mon, 15 Aug 2016 21:04:57 +0800 Subject: [PATCH 04/57] 1. multi thread verify bignum AES and SHA --- components/esp32/aes.c | 54 ++++----- components/esp32/bignum.c | 107 +++++++++++++++--- components/esp32/esp_crypto.c | 64 +++++++++++ components/esp32/esp_thread.c | 53 --------- components/esp32/include/bignum.h | 6 +- .../include/{esp_thread.h => esp_crypto.h} | 28 ++--- components/esp32/sha.c | 24 ++-- components/mbedtls/library/aes.c | 24 +++- components/mbedtls/library/sha1.c | 9 +- components/mbedtls/library/sha256.c | 9 +- components/mbedtls/library/sha512.c | 10 +- 11 files changed, 238 insertions(+), 150 deletions(-) create mode 100644 components/esp32/esp_crypto.c delete mode 100644 components/esp32/esp_thread.c rename components/esp32/include/{esp_thread.h => esp_crypto.h} (61%) diff --git a/components/esp32/aes.c b/components/esp32/aes.c index 10a5025a5..0b0a7ce3c 100644 --- a/components/esp32/aes.c +++ b/components/esp32/aes.c @@ -24,16 +24,14 @@ * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ - -#include "aes.h" - #include -#include "esp_thread.h" +#include "aes.h" +#include "esp_crypto.h" /* Implementation that should never be optimized out by the compiler */ -static void esp_aes_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; -} +//static void bzero( void *v, size_t n ) { +// volatile unsigned char *p = v; while( n-- ) *p++ = 0; +//} void esp_aes_init( AES_CTX *ctx ) { @@ -50,7 +48,7 @@ void esp_aes_free( AES_CTX *ctx ) if( ctx == NULL ) return; - esp_aes_zeroize( ctx, sizeof( AES_CTX ) ); + bzero( ctx, sizeof( AES_CTX ) ); AES_LOCK(); AES_GIVE(); @@ -84,8 +82,9 @@ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, ctx->enc.keybites = keybits; memset(ctx->enc.key, 0, sizeof(ctx->enc.key)); memcpy(ctx->enc.key, key, keybyte); + } else { + ets_aes_setkey_enc(key, keybit); } - ets_aes_setkey_enc(key, keybit); return 0; } @@ -114,8 +113,9 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, ctx->dec.keybites = keybits; memset(ctx->dec.key, 0, sizeof(ctx->dec.key)); memcpy(ctx->dec.key, key, keybyte); + } else { + ets_aes_setkey_dec(key, keybit); } - ets_aes_setkey_dec(key, keybit); return 0; } @@ -169,10 +169,19 @@ int esp_aes_crypt_ecb( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ) { + AES_LOCK(); + + esp_aes_process_enable(ctx, mode); + if( mode == AES_ENCRYPT ) esp_aes_encrypt( ctx, input, output ); else esp_aes_decrypt( ctx, input, output ); + + esp_aes_process_disable(ctx, mode); + + AES_UNLOCK(); + return 0; } @@ -193,9 +202,6 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, if( length % 16 ) return( ERR_AES_INVALID_INPUT_LENGTH ); - AES_LOCK(); - - esp_aes_process_enable(ctx, mode); if( mode == AES_DECRYPT ) { while( length > 0 ) @@ -228,9 +234,6 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, length -= 16; } } - esp_aes_process_disable(ctx, mode); - - AES_UNLOCK(); return 0; } @@ -249,9 +252,6 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, int c; size_t n = *iv_off; - AES_LOCK(); - - esp_aes_process_enable(ctx, mode); if( mode == AES_DECRYPT ) { while( length-- ) @@ -280,9 +280,6 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, } *iv_off = n; - esp_aes_process_disable(ctx, mode); - - AES_UNLOCK(); return 0; } @@ -300,9 +297,6 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, unsigned char c; unsigned char ov[17]; - AES_LOCK(); - - esp_aes_process_enable(ctx, mode); while( length-- ) { memcpy( ov, iv, 16 ); @@ -318,9 +312,6 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, memcpy( iv, ov + 1, 16 ); } - esp_aes_process_disable(ctx, mode); - - AES_UNLOCK(); return 0; } @@ -339,10 +330,6 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, int c, i; size_t n = *nc_off; - AES_LOCK(); - - esp_aes_process_enable(ctx, AES_ENCRYPT); - while( length-- ) { if( n == 0 ) { @@ -359,9 +346,6 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, } *nc_off = n; - esp_aes_process_disable(ctx, AES_ENCRYPT); - - AES_UNLOCK(); return 0; } diff --git a/components/esp32/bignum.c b/components/esp32/bignum.c index 02d5a9c3d..049116206 100644 --- a/components/esp32/bignum.c +++ b/components/esp32/bignum.c @@ -33,17 +33,16 @@ * https://gmplib.org/manual/index.html * */ -#include "bignum.h" -#if defined(ESP_BIGNUM_ALT) #include #include -#include "esp_thread.h" +#include "bignum.h" +#include "esp_crypto.h" /* Implementation that should never be optimized out by the compiler */ -static void esp_mpi_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; -} +//static void bzero( void *v, size_t n ) { +// volatile unsigned char *p = v; while( n-- ) *p++ = 0; +//} #define ciL (sizeof(esp_mpi_uint)) /* chars in limb */ #define biL (ciL << 3) /* bits in limb */ @@ -85,7 +84,7 @@ void esp_mpi_free( mpi *X ) if( X->p != NULL ) { - esp_mpi_zeroize( X->p, X->n * ciL ); + bzero( X->p, X->n * ciL ); free( X->p ); } @@ -117,7 +116,7 @@ int esp_mpi_grow( mpi *X, size_t nblimbs ) if( X->p != NULL ) { memcpy( p, X->p, X->n * ciL ); - esp_mpi_zeroize( X->p, X->n * ciL ); + bzero( X->p, X->n * ciL ); free( X->p ); } @@ -155,7 +154,7 @@ int esp_mpi_shrink( mpi *X, size_t nblimbs ) if( X->p != NULL ) { memcpy( p, X->p, i * ciL ); - esp_mpi_zeroize( X->p, X->n * ciL ); + bzero( X->p, X->n * ciL ); free( X->p ); } @@ -1015,11 +1014,76 @@ static void esp_mpi_mul_hlp( size_t i, esp_mpi_uint *s, esp_mpi_uint *d, esp_mpi /* * Baseline multiplication: X = A * B (HAC 14.12) */ + +static int mul_pram_alloc( mpi *X, const mpi *A, const mpi *B, char **pA, char **pB, char **pX, size_t *bites) +{ + char *sa, *sb, *sx; + int algn; + int words, bytes; + int abytes, bbytes, cbytes; + + if (A->n > B->n) + words = A->n; + else + words = B->n; + + bytes = (words / 16 + ((words % 16) ? 1 : 0 )) * 16 * 4 * 2; + + abytes = A->n * 4; + bbytes = B->n * 4; + + sa = malloc(bytes); + if (!sa) { + return -1; + } + + sb = malloc(bytes); + if (!sb) { + free(sa); + return -1; + } + + sx = malloc(bytes); + if (!sx) { + free(sa); + free(sb); + return -1; + } + + memcpy(sa, A->p, abytes); + memset(sa + abytes, 0, bytes - abytes); + + memcpy(sb, B->p, bbytes); + memset(sb + bbytes, 0, bytes - bbytes); + + *pA = sa; + *pB = sb; + + *pX = sx; + + *bites = bytes * 4; + + return 0; +} + +void mul_pram_free(char **pA, char **pB, char **pX) +{ + free(*pA); + *pA = NULL; + + free(*pB); + *pB = NULL; + + free(*pX); + *pX = NULL; +} + int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) { - int ret; + int ret = -1; size_t i, j; - size_t n = 0; + char *s1 = NULL, *s2 = NULL, *dest = NULL; + size_t bites; mpi TA, TB; @@ -1039,14 +1103,19 @@ int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) MPI_CHK( esp_mpi_grow( X, i + j ) ); MPI_CHK( esp_mpi_lset( X, 0 ) ); - n = j; -// for( i++; j > 0; j-- ) - esp_mpi_mul_hlp( i - 1, A->p, X->p + j - 1, B->p[j - 1] ); + if (mul_pram_alloc(X, A, B, &s1, &s2, &dest, &bites)) { + goto cleanup; + } - BIGNUM_LOCK(); - if (ets_bigint_mult_prepare(A->p, B->p, n)){ - ets_bigint_wait_finish(); - ets_bigint_mult_getz(X->p, n); + BIGNUM_LOCK(); + if (ets_bigint_mult_prepare((uint32_t *)s1, (uint32_t *)s2, bites)){ + ets_bigint_wait_finish(); + if (ets_bigint_mult_getz((uint32_t *)dest, bites) == true) { + memcpy(X->p, dest, (i + j) * 4); + ret = 0; + } else { + esp_mpi_printf("ets_bigint_mult_getz failed\n"); + } } else{ esp_mpi_printf("Baseline multiplication failed\n"); } @@ -1054,6 +1123,8 @@ int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) X->s = A->s * B->s; + mul_pram_free(&s1, &s2, &dest); + cleanup: esp_mpi_free( &TB ); esp_mpi_free( &TA ); diff --git a/components/esp32/esp_crypto.c b/components/esp32/esp_crypto.c new file mode 100644 index 000000000..f0e2cdcb1 --- /dev/null +++ b/components/esp32/esp_crypto.c @@ -0,0 +1,64 @@ +#include "esp_crypto.h" +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +static SemaphoreHandle_t esp_crypto_mutex[MUTEX_MAX_NUM]; +static int esp_crypto_sig[MUTEX_MAX_NUM]; + +#if 0 + #define ESP_DEBUG ets_printf +#else + #define ESP_DEBUG(...) +#endif + +int esp_crypto_init(void) +{ + int i; + + for (i = 0; i < MUTEX_MAX_NUM; i++) { + esp_crypto_mutex[i] = xSemaphoreCreateMutex(); + ESP_DEBUG("init num %d mutex %p\n", i, esp_crypto_mutex[i]); + if (!esp_crypto_mutex[i]) { + goto failed1; + } + esp_crypto_sig[i] = 0; + } + + return 0; + +failed1: + ESP_DEBUG("esp_crypto_init failed\n"); + for (i--; i >= 0; i--) + vQueueDelete(esp_crypto_mutex[i]); + + return -1; +} + +void esp_crypto_lock(unsigned int num) +{ + ESP_DEBUG("1num %d, mutex %p\n", num, esp_crypto_mutex[num]); + xSemaphoreTake(esp_crypto_mutex[num], portMAX_DELAY); +} + +void esp_crypto_unlock(unsigned int num) +{ + ESP_DEBUG("2num %d, mutex %p\n", num, esp_crypto_mutex[num]); + xSemaphoreGive(esp_crypto_mutex[num]); +} + +void esp_crypto_take(unsigned int num) +{ + esp_crypto_sig[num]++; +} + +void esp_crypto_give(unsigned int num) +{ + if (esp_crypto_sig[num]) + esp_crypto_sig[num]--; +} + +bool esp_crypto_is_used(unsigned int num) +{ + return (esp_crypto_sig[num] != 0) ? true : false; +} + diff --git a/components/esp32/esp_thread.c b/components/esp32/esp_thread.c deleted file mode 100644 index e72dc996b..000000000 --- a/components/esp32/esp_thread.c +++ /dev/null @@ -1,53 +0,0 @@ -#include "esp_thread.h" -#include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" - -static xSemaphoreHandle esp_thread_mutex[MUTEX_MAX_NUM]; -static int esp_thread_sig[MUTEX_MAX_NUM]; - -int esp_thread_init(void) -{ - int i; - - for (i = 0; i < MUTEX_MAX_NUM; i++) { - esp_thread_mutex[i] = xSemaphoreCreateMutex(); - if (!esp_thread_mutex[i]) { - goto failed1; - } - esp_thread_sig[i] = 0; - } - - return 0; - -failed1: - for (i--; i >= 0; i--) - vQueueDelete(esp_thread_mutex[i]); - - return -1; -} - -void esp_thread_lock(unsigned int num) -{ - xSemaphoreTake(esp_thread_mutex[num], portMAX_DELAY); -} - -void esp_thread_unlock(unsigned int num) -{ - xSemaphoreGive(esp_thread_mutex[num]); -} - -void esp_thread_take(unsigned int num) -{ - esp_thread_sig[num]++; -} - -void esp_thread_give(unsigned int num) -{ - esp_thread_sig[num]--; -} - -bool esp_thread_is_used(unsigned int num) -{ - return (esp_thread_sig[num] != 0) ? true : false; -} - diff --git a/components/esp32/include/bignum.h b/components/esp32/include/bignum.h index 4cb1ca88f..fc1a5932c 100644 --- a/components/esp32/include/bignum.h +++ b/components/esp32/include/bignum.h @@ -27,9 +27,9 @@ #include "rom/ets_sys.h" #include "rom/bigint.h" -#define ESP_BIGNUM_ALT + #define MPI_DEBUG_ALT -#if defined(ESP_BIGNUM_ALT) + #define ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error occurred while reading from or writing to a file. */ #define ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input parameters to function. */ @@ -700,7 +700,7 @@ int esp_mpi_is_prime( const mpi *X, int esp_mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ); -#endif + #endif diff --git a/components/esp32/include/esp_thread.h b/components/esp32/include/esp_crypto.h similarity index 61% rename from components/esp32/include/esp_thread.h rename to components/esp32/include/esp_crypto.h index 7716f00f1..ef6d86ac0 100644 --- a/components/esp32/include/esp_thread.h +++ b/components/esp32/include/esp_crypto.h @@ -1,5 +1,5 @@ -#ifndef _MULTI_THREAD_H_ -#define _MULTI_THREAD_H_ +#ifndef _MULTI_CRYPTO_H_ +#define _MULTI_CRYPTO_H_ #include "c_types.h" #include "rom/ets_sys.h" @@ -16,21 +16,21 @@ enum { MUTEX_MAX_NUM, }; -int esp_thread_init(void); +int esp_crypto_init(void); -void esp_thread_lock(unsigned int num); -void esp_thread_unlock(unsigned int num); +void esp_crypto_lock(unsigned int num); +void esp_crypto_unlock(unsigned int num); -void esp_thread_take(unsigned int num); -void esp_thread_give(unsigned int num); -bool esp_thread_is_used(unsigned int num); +void esp_crypto_take(unsigned int num); +void esp_crypto_give(unsigned int num); +bool esp_crypto_is_used(unsigned int num); -#define MUTEX_LOCK(num) esp_thread_lock(num) -#define MUTEX_UNLOCK(num) esp_thread_unlock(num) +#define MUTEX_LOCK(num) esp_crypto_lock(num) +#define MUTEX_UNLOCK(num) esp_crypto_unlock(num) -#define SIG_TAKE(num) esp_thread_take(num) -#define SIG_GIVE(num) esp_thread_give(num) -#define SIG_IS_USED(num) esp_thread_is_used(num) +#define SIG_TAKE(num) esp_crypto_take(num) +#define SIG_GIVE(num) esp_crypto_give(num) +#define SIG_IS_USED(num) esp_crypto_is_used(num) #define AES_LOCK() MUTEX_LOCK(AES_MUTEX) #define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) @@ -53,4 +53,4 @@ bool esp_thread_is_used(unsigned int num); } #endif -#endif /* esp_thread.h */ +#endif /* esp_crypto.h */ diff --git a/components/esp32/sha.c b/components/esp32/sha.c index 9c28ca9c4..2e98de369 100644 --- a/components/esp32/sha.c +++ b/components/esp32/sha.c @@ -23,15 +23,14 @@ * http://www.itl.nist.gov/fipspubs/fip180-1.htm */ -#include "sha.h" - #include -#include "esp_thread.h" +#include "sha.h" +#include "esp_crypto.h" /* Implementation that should never be optimized out by the compiler */ -static void esp_sha_zeroize( void *v, size_t n ) { - volatile unsigned char *p = v; while( n-- ) *p++ = 0; -} +//static void bzero( void *v, size_t n ) { +// volatile unsigned char *p = v; while( n-- ) *p++ = 0; +//} void esp_sha1_init( SHA1_CTX *ctx ) { @@ -48,7 +47,7 @@ void esp_sha1_free( SHA1_CTX *ctx ) if( ctx == NULL ) return; - esp_sha_zeroize( ctx, sizeof( SHA1_CTX ) ); + bzero( ctx, sizeof( SHA1_CTX ) ); SHA_LOCK(); SHA_GIVE(); @@ -74,7 +73,6 @@ void esp_sha1_starts( SHA1_CTX *ctx ) { SHA_LOCK(); ets_sha_init(&ctx->context); - SHA_UNLOCK(); ctx->context_type = SHA1; } @@ -84,7 +82,6 @@ void esp_sha1_starts( SHA1_CTX *ctx ) */ void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) { - SHA_LOCK(); ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -133,7 +130,7 @@ void esp_sha256_free( SHA256_CTX *ctx ) if( ctx == NULL ) return; - esp_sha_zeroize( ctx, sizeof( SHA256_CTX ) ); + bzero( ctx, sizeof( SHA256_CTX ) ); SHA_LOCK(); SHA_GIVE(); @@ -154,7 +151,6 @@ void esp_sha256_starts( SHA256_CTX *ctx, int is224 ) { SHA_LOCK(); ets_sha_init(&ctx->context); - SHA_UNLOCK(); if( is224 == 0 ) { @@ -171,7 +167,6 @@ void esp_sha256_starts( SHA256_CTX *ctx, int is224 ) */ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) { - SHA_LOCK(); ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -215,7 +210,7 @@ void esp_sha512_free( SHA512_CTX *ctx ) if( ctx == NULL ) return; - esp_sha_zeroize( ctx, sizeof( SHA512_CTX ) ); + bzero( ctx, sizeof( SHA512_CTX ) ); SHA_LOCK(); SHA_GIVE(); @@ -236,7 +231,7 @@ void esp_sha512_starts( SHA512_CTX *ctx, int is384 ) { SHA_LOCK(); ets_sha_init(&ctx->context); - SHA_UNLOCK(); + if( is384 == 0 ) { /* SHA-512 */ @@ -254,7 +249,6 @@ void esp_sha512_starts( SHA512_CTX *ctx, int is384 ) */ void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) { - SHA_LOCK(); ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } diff --git a/components/mbedtls/library/aes.c b/components/mbedtls/library/aes.c index a186dee98..690358519 100644 --- a/components/mbedtls/library/aes.c +++ b/components/mbedtls/library/aes.c @@ -1237,9 +1237,8 @@ int mbedtls_aes_self_test( int verbose ) unsigned char stream_block[16]; #endif mbedtls_aes_context ctx; - - memset( key, 0, 32 ); - mbedtls_aes_init( &ctx ); + + memset( key, 0, 32 ); /* * ECB mode @@ -1255,6 +1254,8 @@ int mbedtls_aes_self_test( int verbose ) memset( buf, 0, 16 ); + mbedtls_aes_init( &ctx ); + if( v == MBEDTLS_AES_DECRYPT ) { mbedtls_aes_setkey_dec( &ctx, key, 128 + u * 64 ); @@ -1267,6 +1268,7 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_aes_free( &ctx ); ret = 1; goto exit; } @@ -1283,6 +1285,8 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_aes_free( &ctx ); + ret = 1; goto exit; } @@ -1290,6 +1294,8 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "passed\n" ); + + mbedtls_aes_free( &ctx ); } if( verbose != 0 ) @@ -1312,6 +1318,8 @@ int mbedtls_aes_self_test( int verbose ) memset( prv, 0, 16 ); memset( buf, 0, 16 ); + mbedtls_aes_init( &ctx ); + if( v == MBEDTLS_AES_DECRYPT ) { mbedtls_aes_setkey_dec( &ctx, key, 128 + u * 64 ); @@ -1324,6 +1332,8 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_aes_free( &ctx ); + ret = 1; goto exit; } @@ -1348,6 +1358,8 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_aes_free( &ctx ); + ret = 1; goto exit; } @@ -1355,6 +1367,8 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "passed\n" ); + + mbedtls_aes_free( &ctx ); } if( verbose != 0 ) @@ -1377,6 +1391,8 @@ int mbedtls_aes_self_test( int verbose ) memcpy( iv, aes_test_cfb128_iv, 16 ); memcpy( key, aes_test_cfb128_key[u], 16 + u * 8 ); + mbedtls_aes_init( &ctx ); + offset = 0; mbedtls_aes_setkey_enc( &ctx, key, 128 + u * 64 ); @@ -1433,6 +1449,8 @@ int mbedtls_aes_self_test( int verbose ) memcpy( nonce_counter, aes_test_ctr_nonce_counter[u], 16 ); memcpy( key, aes_test_ctr_key[u], 16 ); + mbedtls_aes_init( &ctx ); + offset = 0; mbedtls_aes_setkey_enc( &ctx, key, 128 ); diff --git a/components/mbedtls/library/sha1.c b/components/mbedtls/library/sha1.c index 2ccf2a2f5..46ed34f94 100644 --- a/components/mbedtls/library/sha1.c +++ b/components/mbedtls/library/sha1.c @@ -396,13 +396,13 @@ int mbedtls_sha1_self_test( int verbose ) unsigned char sha1sum[20]; mbedtls_sha1_context ctx; - mbedtls_sha1_init( &ctx ); - /* * SHA-1 */ for( i = 0; i < 3; i++ ) { + mbedtls_sha1_init( &ctx ); + if( verbose != 0 ) mbedtls_printf( " SHA-1 test #%d: ", i + 1 ); @@ -426,19 +426,22 @@ int mbedtls_sha1_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_sha1_free( &ctx ); + ret = 1; goto exit; } if( verbose != 0 ) mbedtls_printf( "passed\n" ); + + mbedtls_sha1_free( &ctx ); } if( verbose != 0 ) mbedtls_printf( "\n" ); exit: - mbedtls_sha1_free( &ctx ); return( ret ); } diff --git a/components/mbedtls/library/sha256.c b/components/mbedtls/library/sha256.c index 4e82c0b79..cc6bd335d 100644 --- a/components/mbedtls/library/sha256.c +++ b/components/mbedtls/library/sha256.c @@ -393,13 +393,13 @@ int mbedtls_sha256_self_test( int verbose ) unsigned char sha256sum[32]; mbedtls_sha256_context ctx; - mbedtls_sha256_init( &ctx ); - for( i = 0; i < 6; i++ ) { j = i % 3; k = i < 3; + mbedtls_sha256_init( &ctx ); + if( verbose != 0 ) mbedtls_printf( " SHA-%d test #%d: ", 256 - k * 32, j + 1 ); @@ -423,19 +423,22 @@ int mbedtls_sha256_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_sha256_free( &ctx ); + ret = 1; goto exit; } if( verbose != 0 ) mbedtls_printf( "passed\n" ); + + mbedtls_sha256_free( &ctx ); } if( verbose != 0 ) mbedtls_printf( "\n" ); exit: - mbedtls_sha256_free( &ctx ); return( ret ); } diff --git a/components/mbedtls/library/sha512.c b/components/mbedtls/library/sha512.c index 0f9e1e535..245ede0eb 100644 --- a/components/mbedtls/library/sha512.c +++ b/components/mbedtls/library/sha512.c @@ -449,13 +449,13 @@ int mbedtls_sha512_self_test( int verbose ) unsigned char sha512sum[64]; mbedtls_sha512_context ctx; - mbedtls_sha512_init( &ctx ); - for( i = 0; i < 6; i++ ) { j = i % 3; k = i < 3; + mbedtls_sha512_init( &ctx ); + if( verbose != 0 ) mbedtls_printf( " SHA-%d test #%d: ", 512 - k * 128, j + 1 ); @@ -479,19 +479,23 @@ int mbedtls_sha512_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); + mbedtls_sha512_free( &ctx ); + ret = 1; goto exit; } if( verbose != 0 ) mbedtls_printf( "passed\n" ); + + mbedtls_sha512_free( &ctx ); } if( verbose != 0 ) mbedtls_printf( "\n" ); exit: - mbedtls_sha512_free( &ctx ); + return( ret ); } From 2d80fada70e2096781e8fd49586841c81a5751a0 Mon Sep 17 00:00:00 2001 From: liuhan Date: Tue, 30 Aug 2016 20:40:58 +0800 Subject: [PATCH 05/57] components/mbedtls: MBEDTLS Handshake result check modify esp_config.h add some feature for support http2.0 protocol, TLS Handshake OK. --- components/esp32/aes.c | 4 +- components/esp32/bignum.c | 7 +- components/esp32/include/aes.h | 6 +- components/esp32/include/bignum.h | 2 +- components/esp32/include/esp_crypto.h | 2 +- components/esp32/include/sha.h | 4 +- components/esp32/sha.c | 5 + .../mbedtls/include/mbedtls/esp_config.h | 147 ++--- components/mbedtls/port/esp_hardware.c | 45 ++ components/mbedtls/port/include/sha512_alt.h | 1 + components/mbedtls/port/net.c | 522 ++++++++++++++++++ 11 files changed, 659 insertions(+), 86 deletions(-) create mode 100644 components/mbedtls/port/esp_hardware.c create mode 100644 components/mbedtls/port/net.c diff --git a/components/esp32/aes.c b/components/esp32/aes.c index 0b0a7ce3c..3767dd7ee 100644 --- a/components/esp32/aes.c +++ b/components/esp32/aes.c @@ -64,7 +64,7 @@ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { enum AES_BITS keybit; - uint16 keybyte = keybits / 8; + uint16_t keybyte = keybits / 8; switch (keybits){ case 128: keybit = AES128; @@ -95,7 +95,7 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { enum AES_BITS keybit; - uint16 keybyte = keybits / 8; + uint16_t keybyte = keybits / 8; switch (keybits){ case 128: keybit = AES128; diff --git a/components/esp32/bignum.c b/components/esp32/bignum.c index 049116206..dbfa418ec 100644 --- a/components/esp32/bignum.c +++ b/components/esp32/bignum.c @@ -1018,9 +1018,9 @@ static void esp_mpi_mul_hlp( size_t i, esp_mpi_uint *s, esp_mpi_uint *d, esp_mpi static int mul_pram_alloc( mpi *X, const mpi *A, const mpi *B, char **pA, char **pB, char **pX, size_t *bites) { char *sa, *sb, *sx; - int algn; +// int algn; int words, bytes; - int abytes, bbytes, cbytes; + int abytes, bbytes; if (A->n > B->n) words = A->n; @@ -2178,6 +2178,3 @@ cleanup: return( ret ); } - -#endif /* ESP_BIGNUM_ALT */ - diff --git a/components/esp32/include/aes.h b/components/esp32/include/aes.h index aa81e1b5f..b1a47eb4e 100644 --- a/components/esp32/include/aes.h +++ b/components/esp32/include/aes.h @@ -24,7 +24,7 @@ #ifndef ESP_AES_H #define ESP_AES_H -#include "c_types.h" +#include "esp_types.h" #include "rom/ets_sys.h" #include "rom/aes.h" @@ -41,8 +41,8 @@ extern "C" { typedef struct{ bool flag; - uint16 keybites; - uint8 key[32]; + uint16_t keybites; + uint8_t key[32]; }key_context, KEY_CTX; /** diff --git a/components/esp32/include/bignum.h b/components/esp32/include/bignum.h index fc1a5932c..e077fe2ed 100644 --- a/components/esp32/include/bignum.h +++ b/components/esp32/include/bignum.h @@ -23,7 +23,7 @@ #ifndef _ESP_BIGNUM_H #define _ESP_BIGNUM_H -#include "c_types.h" +#include "esp_types.h" #include "rom/ets_sys.h" #include "rom/bigint.h" diff --git a/components/esp32/include/esp_crypto.h b/components/esp32/include/esp_crypto.h index ef6d86ac0..5accfe838 100644 --- a/components/esp32/include/esp_crypto.h +++ b/components/esp32/include/esp_crypto.h @@ -1,7 +1,7 @@ #ifndef _MULTI_CRYPTO_H_ #define _MULTI_CRYPTO_H_ -#include "c_types.h" +#include "esp_types.h" #include "rom/ets_sys.h" #ifdef __cplusplus diff --git a/components/esp32/include/sha.h b/components/esp32/include/sha.h index 661354c1d..301d893ae 100644 --- a/components/esp32/include/sha.h +++ b/components/esp32/include/sha.h @@ -6,7 +6,7 @@ #ifndef _ESP_SHA_H_ #define _ESP_SHA_H_ -#include "c_types.h" +#include "esp_types.h" #include "rom/ets_sys.h" #include "rom/sha.h" @@ -164,6 +164,8 @@ typedef sha_context SHA512_CTX; */ void esp_sha512_init( SHA512_CTX *ctx ); +void esp_sha512_process( SHA512_CTX *ctx, const unsigned char data[128] ); + /** * \brief Clear SHA-512 context * diff --git a/components/esp32/sha.c b/components/esp32/sha.c index 2e98de369..e7d7e0be9 100644 --- a/components/esp32/sha.c +++ b/components/esp32/sha.c @@ -205,6 +205,11 @@ void esp_sha512_init( SHA512_CTX *ctx ) SHA_UNLOCK(); } +void esp_sha512_process( SHA512_CTX *ctx, const unsigned char data[128] ) +{ + +} + void esp_sha512_free( SHA512_CTX *ctx ) { if( ctx == NULL ) diff --git a/components/mbedtls/include/mbedtls/esp_config.h b/components/mbedtls/include/mbedtls/esp_config.h index 1ea607681..0bf7e14d1 100644 --- a/components/mbedtls/include/mbedtls/esp_config.h +++ b/components/mbedtls/include/mbedtls/esp_config.h @@ -225,7 +225,7 @@ * Uncomment a macro to enable alternate implementation of the corresponding * module. */ -#define MBEDTLS_AES_ALT +//#define MBEDTLS_AES_ALT //#define MBEDTLS_ARC4_ALT //#define MBEDTLS_BLOWFISH_ALT //#define MBEDTLS_CAMELLIA_ALT @@ -235,11 +235,11 @@ //#define MBEDTLS_MD4_ALT //#define MBEDTLS_MD5_ALT //#define MBEDTLS_RIPEMD160_ALT -#define MBEDTLS_SHA1_ALT -#define MBEDTLS_SHA256_ALT -#define MBEDTLS_SHA512_ALT +//#define MBEDTLS_SHA1_ALT +//#define MBEDTLS_SHA256_ALT +//#define MBEDTLS_SHA512_ALT -#define MBEDTLS_BIGNUM_ALT +//#define MBEDTLS_BIGNUM_ALT /** * \def MBEDTLS_MD2_PROCESS_ALT * @@ -374,10 +374,10 @@ * * Enable padding modes in the cipher layer. */ -//#define MBEDTLS_CIPHER_PADDING_PKCS7 -//#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS -//#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN -//#define MBEDTLS_CIPHER_PADDING_ZEROS +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#define MBEDTLS_CIPHER_PADDING_ZEROS /** * \def MBEDTLS_ENABLE_WEAK_CIPHERSUITES @@ -415,18 +415,18 @@ * * Comment macros to disable the curve and functions for it */ -//#define MBEDTLS_ECP_DP_SECP192R1_ENABLED -//#define MBEDTLS_ECP_DP_SECP224R1_ENABLED -//#define MBEDTLS_ECP_DP_SECP256R1_ENABLED -//#define MBEDTLS_ECP_DP_SECP384R1_ENABLED -//#define MBEDTLS_ECP_DP_SECP521R1_ENABLED -//#define MBEDTLS_ECP_DP_SECP192K1_ENABLED -//#define MBEDTLS_ECP_DP_SECP224K1_ENABLED -//#define MBEDTLS_ECP_DP_SECP256K1_ENABLED -//#define MBEDTLS_ECP_DP_BP256R1_ENABLED -//#define MBEDTLS_ECP_DP_BP384R1_ENABLED -//#define MBEDTLS_ECP_DP_BP512R1_ENABLED -//#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED /** * \def MBEDTLS_ECP_NIST_OPTIM @@ -437,7 +437,7 @@ * * Comment this macro to disable NIST curves optimisation. */ -//#define MBEDTLS_ECP_NIST_OPTIM +#define MBEDTLS_ECP_NIST_OPTIM /** * \def MBEDTLS_ECDSA_DETERMINISTIC @@ -451,7 +451,7 @@ * * Comment this macro to disable deterministic ECDSA. */ -//#define MBEDTLS_ECDSA_DETERMINISTIC +#define MBEDTLS_ECDSA_DETERMINISTIC /** * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED @@ -473,7 +473,7 @@ * MBEDTLS_TLS_PSK_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA */ -//#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED @@ -497,7 +497,7 @@ * MBEDTLS_TLS_DHE_PSK_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_DHE_PSK_WITH_RC4_128_SHA */ -//#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED @@ -517,7 +517,7 @@ * MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA */ -//#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED @@ -596,7 +596,7 @@ * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA * MBEDTLS_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA */ -//#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED @@ -621,7 +621,7 @@ * MBEDTLS_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_ECDHE_RSA_WITH_RC4_128_SHA */ -//#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED @@ -645,7 +645,7 @@ * MBEDTLS_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA * MBEDTLS_TLS_ECDHE_ECDSA_WITH_RC4_128_SHA */ -//#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED @@ -669,7 +669,7 @@ * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 */ -//#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED @@ -693,7 +693,7 @@ * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 */ -//#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED /** * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED @@ -946,7 +946,7 @@ * * Comment this macro to disable support for Encrypt-then-MAC */ -//#define MBEDTLS_SSL_ENCRYPT_THEN_MAC +#define MBEDTLS_SSL_ENCRYPT_THEN_MAC /** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET * @@ -964,7 +964,7 @@ * * Comment this macro to disable support for Extended Master Secret. */ -//#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET +#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET /** * \def MBEDTLS_SSL_FALLBACK_SCSV @@ -981,7 +981,7 @@ * * Comment this macro to disable support for FALLBACK_SCSV */ -//#define MBEDTLS_SSL_FALLBACK_SCSV +#define MBEDTLS_SSL_FALLBACK_SCSV /** * \def MBEDTLS_SSL_HW_RECORD_ACCEL @@ -1018,7 +1018,7 @@ * * Comment this to disable support for renegotiation. */ -//#define MBEDTLS_SSL_RENEGOTIATION +#define MBEDTLS_SSL_RENEGOTIATION /** * \def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO @@ -1047,7 +1047,7 @@ * * Comment this macro to disable support for the max_fragment_length extension */ -//#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH /** * \def MBEDTLS_SSL_PROTO_SSL3 @@ -1059,7 +1059,7 @@ * * Comment this macro to disable support for SSL 3.0 */ -//#define MBEDTLS_SSL_PROTO_SSL3 +#define MBEDTLS_SSL_PROTO_SSL3 /** * \def MBEDTLS_SSL_PROTO_TLS1 @@ -1110,7 +1110,7 @@ * * Comment this macro to disable support for DTLS */ -//#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_PROTO_DTLS /** * \def MBEDTLS_SSL_ALPN @@ -1119,7 +1119,7 @@ * * Comment this macro to disable support for ALPN. */ -//#define MBEDTLS_SSL_ALPN +#define MBEDTLS_SSL_ALPN /** * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY @@ -1134,7 +1134,7 @@ * * Comment this to disable anti-replay in DTLS. */ -//#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY /** * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY @@ -1152,7 +1152,7 @@ * * Comment this to disable support for HelloVerifyRequest. */ -//#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY /** * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE @@ -1168,7 +1168,7 @@ * * Comment this to disable support for clients reusing the source port. */ -//#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE /** * \def MBEDTLS_SSL_DTLS_BADMAC_LIMIT @@ -1179,7 +1179,7 @@ * * Requires: MBEDTLS_SSL_PROTO_DTLS */ -//#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT +#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT /** * \def MBEDTLS_SSL_SESSION_TICKETS @@ -1193,7 +1193,7 @@ * * Comment this macro to disable support for SSL session tickets */ -//#define MBEDTLS_SSL_SESSION_TICKETS +#define MBEDTLS_SSL_SESSION_TICKETS /** * \def MBEDTLS_SSL_EXPORT_KEYS @@ -1203,7 +1203,7 @@ * * Comment this macro to disable support for key export */ -//#define MBEDTLS_SSL_EXPORT_KEYS +#define MBEDTLS_SSL_EXPORT_KEYS /** * \def MBEDTLS_SSL_SERVER_NAME_INDICATION @@ -1223,7 +1223,7 @@ * * Comment this macro to disable support for truncated HMAC in SSL */ -//#define MBEDTLS_SSL_TRUNCATED_HMAC +#define MBEDTLS_SSL_TRUNCATED_HMAC /** * \def MBEDTLS_THREADING_ALT @@ -1258,7 +1258,7 @@ * * Comment this to disable run-time checking and save ROM space */ -//#define MBEDTLS_VERSION_FEATURES +#define MBEDTLS_VERSION_FEATURES /** * \def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3 @@ -1294,7 +1294,7 @@ * * Comment to skip keyUsage checking for both CA and leaf certificates. */ -//#define MBEDTLS_X509_CHECK_KEY_USAGE +#define MBEDTLS_X509_CHECK_KEY_USAGE /** * \def MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE @@ -1307,7 +1307,7 @@ * * Comment to skip extendedKeyUsage checking for certificates. */ -//#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE +#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE /** * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT @@ -1317,7 +1317,7 @@ * * Comment this macro to disallow using RSASSA-PSS in certificates. */ -//#define MBEDTLS_X509_RSASSA_PSS_SUPPORT +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT /** * \def MBEDTLS_ZLIB_SUPPORT @@ -1459,7 +1459,7 @@ * MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA * MBEDTLS_TLS_PSK_WITH_RC4_128_SHA */ -//#define MBEDTLS_ARC4_C +#define MBEDTLS_ARC4_C /** * \def MBEDTLS_ASN1_PARSE_C @@ -1524,7 +1524,7 @@ * * Module: library/blowfish.c */ -//#define MBEDTLS_BLOWFISH_C +#define MBEDTLS_BLOWFISH_C /** * \def MBEDTLS_CAMELLIA_C @@ -1579,7 +1579,7 @@ * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 */ -//#define MBEDTLS_CAMELLIA_C +#define MBEDTLS_CAMELLIA_C /** * \def MBEDTLS_CCM_C @@ -1593,7 +1593,7 @@ * This module enables the AES-CCM ciphersuites, if other requisites are * enabled as well. */ -//#define MBEDTLS_CCM_C +#define MBEDTLS_CCM_C /** * \def MBEDTLS_CERTS_C @@ -1605,7 +1605,7 @@ * * This module is used for testing (ssl_client/server). */ -//#define MBEDTLS_CERTS_C +#define MBEDTLS_CERTS_C /** * \def MBEDTLS_CIPHER_C @@ -1645,7 +1645,7 @@ * * This module provides debugging functions. */ -//#define MBEDTLS_DEBUG_C +#define MBEDTLS_DEBUG_C /** * \def MBEDTLS_DES_C @@ -1671,7 +1671,7 @@ * * PEM_PARSE uses DES/3DES for decrypting encrypted keys. */ -//#define MBEDTLS_DES_C +#define MBEDTLS_DES_C /** * \def MBEDTLS_DHM_C @@ -1685,7 +1685,7 @@ * This module is used by the following key exchanges: * DHE-RSA, DHE-PSK */ -//#define MBEDTLS_DHM_C +#define MBEDTLS_DHM_C /** * \def MBEDTLS_ECDH_C @@ -1701,7 +1701,7 @@ * * Requires: MBEDTLS_ECP_C */ -//#define MBEDTLS_ECDH_C +#define MBEDTLS_ECDH_C /** * \def MBEDTLS_ECDSA_C @@ -1716,7 +1716,7 @@ * * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C */ -//#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECDSA_C /** * \def MBEDTLS_ECJPAKE_C @@ -1749,7 +1749,7 @@ * * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED */ -//#define MBEDTLS_ECP_C +#define MBEDTLS_ECP_C /** * \def MBEDTLS_ENTROPY_C @@ -1775,7 +1775,7 @@ * * This module enables mbedtls_strerror(). */ -//#define MBEDTLS_ERROR_C +#define MBEDTLS_ERROR_C /** * \def MBEDTLS_GCM_C @@ -1789,7 +1789,7 @@ * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other * requisites are enabled as well. */ -//#define MBEDTLS_GCM_C //764 Byte +#define MBEDTLS_GCM_C /** * \def MBEDTLS_HAVEGE_C @@ -1826,7 +1826,7 @@ * * Uncomment to enable the HMAC_DRBG random number geerator. */ -//#define MBEDTLS_HMAC_DRBG_C +#define MBEDTLS_HMAC_DRBG_C /** * \def MBEDTLS_MD_C @@ -1941,7 +1941,7 @@ * * This modules adds support for the VIA PadLock on x86. */ -//#define MBEDTLS_PADLOCK_C +#define MBEDTLS_PADLOCK_C /** * \def MBEDTLS_PEM_PARSE_C @@ -2033,7 +2033,7 @@ * * This module adds support for the PKCS#5 functions. */ -//#define MBEDTLS_PKCS5_C +#define MBEDTLS_PKCS5_C /** * \def MBEDTLS_PKCS11_C @@ -2064,7 +2064,7 @@ * * This module enables PKCS#12 functions. */ -//#define MBEDTLS_PKCS12_C +#define MBEDTLS_PKCS12_C /** * \def MBEDTLS_PLATFORM_C @@ -2084,7 +2084,7 @@ * * This module enables abstraction of common (libc) functions. */ -//#define MBEDTLS_PLATFORM_C +#define MBEDTLS_PLATFORM_C /** * \def MBEDTLS_RIPEMD160_C @@ -2095,7 +2095,7 @@ * Caller: library/mbedtls_md.c * */ -//#define MBEDTLS_RIPEMD160_C +#define MBEDTLS_RIPEMD160_C /** * \def MBEDTLS_RSA_C @@ -2173,7 +2173,7 @@ * * Requires: MBEDTLS_SSL_CACHE_C */ -//#define MBEDTLS_SSL_CACHE_C +#define MBEDTLS_SSL_CACHE_C /** * \def MBEDTLS_SSL_COOKIE_C @@ -2183,7 +2183,7 @@ * Module: library/ssl_cookie.c * Caller: */ -//#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_SSL_COOKIE_C /** * \def MBEDTLS_SSL_TICKET_C @@ -2195,7 +2195,7 @@ * * Requires: MBEDTLS_CIPHER_C */ -//#define MBEDTLS_SSL_TICKET_C +#define MBEDTLS_SSL_TICKET_C /** * \def MBEDTLS_SSL_CLI_C @@ -2466,7 +2466,8 @@ //#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ /* SSL options */ -#define MBEDTLS_SSL_MAX_CONTENT_LEN 3072 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */ + +#define MBEDTLS_SSL_MAX_CONTENT_LEN 5120 /**< Maxium fragment length in bytes, determines the size of each of the two internal I/O buffers */ //#define MBEDTLS_SSL_DEFAULT_TICKET_LIFETIME 86400 /**< Lifetime of session tickets (if enabled) */ //#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */ //#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ diff --git a/components/mbedtls/port/esp_hardware.c b/components/mbedtls/port/esp_hardware.c new file mode 100644 index 000000000..c269a0e3f --- /dev/null +++ b/components/mbedtls/port/esp_hardware.c @@ -0,0 +1,45 @@ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include +#include +#include +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) +/** + * \brief Entropy poll callback for a hardware source + * + * \warning This is not provided by mbed TLS! + * See \c MBEDTLS_ENTROPY_HARDWARE_ALT in config.h. + * + * \note This must accept NULL as its first argument. + */ +static int os_get_random(unsigned char *buf, size_t len) +{ + int i, j; + unsigned long tmp; + for (i = 0; i < ((len + 3) & ~3) / 4; i ++){ + tmp = rand(); + for (j = 0; j < 4; j ++){ + if ((i * 4 + j) < len){ + buf[i * 4 + j] = (unsigned char)(tmp >> (j * 8)); + }else{ + break; + } + } + + } + return 0; +} + +int mbedtls_hardware_poll( void *data, + unsigned char *output, size_t len, size_t *olen ) +{ + os_get_random(output, len); + *olen = len; + return 0; +} +#endif + diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h index b4e17259e..7814bf19d 100644 --- a/components/mbedtls/port/include/sha512_alt.h +++ b/components/mbedtls/port/include/sha512_alt.h @@ -17,6 +17,7 @@ extern "C" { typedef SHA512_CTX mbedtls_sha512_context; #define mbedtls_sha512_init esp_sha512_init +#define mbedtls_sha512_process esp_sha512_process #define mbedtls_sha512_clone esp_sha512_clone #define mbedtls_sha512_starts esp_sha512_starts #define mbedtls_sha512_update esp_sha512_update diff --git a/components/mbedtls/port/net.c b/components/mbedtls/port/net.c new file mode 100644 index 000000000..f712d9a65 --- /dev/null +++ b/components/mbedtls/port/net.c @@ -0,0 +1,522 @@ +/* + * TCP/IP or UDP/IP networking functions + * modified for LWIP support on ESP32 + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2015 Angus Gratton + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if !defined(MBEDTLS_NET_C) + +#include "mbedtls/net.h" + +#include + +#include +#include +//#include +#include +#include +//#include + +#include +#include + +#include + +#include + +/* + * Prepare for using the sockets interface + */ +static int net_prepare( void ) +{ +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + WSADATA wsaData; + + if( wsa_init_done == 0 ) + { + if( WSAStartup( MAKEWORD(2,0), &wsaData ) != 0 ) + return( MBEDTLS_ERR_NET_SOCKET_FAILED ); + + wsa_init_done = 1; + } +#else +#endif + return( 0 ); +} + +/* + * Initialize a context + */ +void mbedtls_net_init( mbedtls_net_context *ctx ) +{ + ctx->fd = -1; +} + +/* + * Initiate a TCP connection with host:port and the given protocol + */ +int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char *port, int proto ) +{ + int ret; + struct addrinfo hints, *addr_list, *cur; + + if( ( ret = net_prepare() ) != 0 ) + return( ret ); + + /* Do name resolution with both IPv6 and IPv4 */ + memset( &hints, 0, sizeof( hints ) ); + hints.ai_family = AF_UNSPEC; + hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM; + hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP; + + if( getaddrinfo( host, port, &hints, &addr_list ) != 0 ) + return( MBEDTLS_ERR_NET_UNKNOWN_HOST ); + + /* Try the sockaddrs until a connection succeeds */ + ret = MBEDTLS_ERR_NET_UNKNOWN_HOST; + for( cur = addr_list; cur != NULL; cur = cur->ai_next ) + { + ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype, + cur->ai_protocol ); + if( ctx->fd < 0 ) + { + ret = MBEDTLS_ERR_NET_SOCKET_FAILED; + continue; + } + + if( connect( ctx->fd, cur->ai_addr, cur->ai_addrlen ) == 0 ) + { + ret = 0; + break; + } + + close( ctx->fd ); + ret = MBEDTLS_ERR_NET_CONNECT_FAILED; + } + + freeaddrinfo( addr_list ); + + return( ret ); +} + +/* + * Create a listening socket on bind_ip:port + */ +int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto ) +{ + int n, ret; + struct addrinfo hints, *addr_list, *cur; + + if( ( ret = net_prepare() ) != 0 ) + return( ret ); + + /* Bind to IPv6 and/or IPv4, but only in the desired protocol */ + memset( &hints, 0, sizeof( hints ) ); + hints.ai_family = AF_UNSPEC; + hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM; + hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP; + + if( getaddrinfo( bind_ip, port, &hints, &addr_list ) != 0 ) + return( MBEDTLS_ERR_NET_UNKNOWN_HOST ); + + /* Try the sockaddrs until a binding succeeds */ + ret = MBEDTLS_ERR_NET_UNKNOWN_HOST; + for( cur = addr_list; cur != NULL; cur = cur->ai_next ) + { + ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype, + cur->ai_protocol ); + if( ctx->fd < 0 ) + { + ret = MBEDTLS_ERR_NET_SOCKET_FAILED; + continue; + } + + /*SO_REUSEADDR option dafault is disable in source code(lwip)*/ +#if SO_REUSE + n = 1; + if( setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR, + (const char *) &n, sizeof( n ) ) != 0 ) + { + close( ctx->fd ); + ret = MBEDTLS_ERR_NET_SOCKET_FAILED; + continue; + } +#endif + /*bind interface dafault don't process the addr is 0xffffffff for TCP Protocol*/ + struct sockaddr_in *serv_addr = NULL; + serv_addr = (struct sockaddr_in *)cur->ai_addr; + serv_addr->sin_addr.s_addr = htonl(INADDR_ANY); /* Any incoming interface */ + if( bind( ctx->fd, (struct sockaddr *)serv_addr, cur->ai_addrlen ) != 0 ) + { + close( ctx->fd ); + ret = MBEDTLS_ERR_NET_BIND_FAILED; + continue; + } + + /* Listen only makes sense for TCP */ + if( proto == MBEDTLS_NET_PROTO_TCP ) + { + if( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 ) + { + close( ctx->fd ); + ret = MBEDTLS_ERR_NET_LISTEN_FAILED; + continue; + } + } + + /* I we ever get there, it's a success */ + ret = 0; + break; + } + + freeaddrinfo( addr_list ); + + return( ret ); + +} + +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) +/* + * Check if the requested operation would be blocking on a non-blocking socket + * and thus 'failed' with a negative return value. + */ +static int net_would_block( const mbedtls_net_context *ctx ) +{ + ((void) ctx); + return( WSAGetLastError() == WSAEWOULDBLOCK ); +} +#else +/* + * Check if the requested operation would be blocking on a non-blocking socket + * and thus 'failed' with a negative return value. + * + * Note: on a blocking socket this function always returns 0! + */ +static int net_would_block( const mbedtls_net_context *ctx ) +{ + /* + * Never return 'WOULD BLOCK' on a non-blocking socket + */ + if( ( fcntl( ctx->fd, F_GETFL, 0) & O_NONBLOCK ) != O_NONBLOCK ) + return( 0 ); + + int error = 0; + get_errno(ctx->fd, &error); + switch( error ) + { +#if defined EAGAIN + case EAGAIN: +#endif +#if defined EWOULDBLOCK && EWOULDBLOCK != EAGAIN + case EWOULDBLOCK: +#endif + return( 1 ); + } + return( 0 ); +} +#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */ + +/* + * Accept a connection from a remote client + */ +int mbedtls_net_accept( mbedtls_net_context *bind_ctx, + mbedtls_net_context *client_ctx, + void *client_ip, size_t buf_size, size_t *ip_len ) +{ + int ret; + int type; + + struct sockaddr_in client_addr; + + socklen_t n = (socklen_t) sizeof( client_addr ); + socklen_t type_len = (socklen_t) sizeof( type ); + + /* Is this a TCP or UDP socket? */ + if( getsockopt( bind_ctx->fd, SOL_SOCKET, SO_TYPE, + (void *) &type, (socklen_t *) &type_len ) != 0 || + ( type != SOCK_STREAM && type != SOCK_DGRAM ) ) + { + return( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + } + + if( type == SOCK_STREAM ) + { + /* TCP: actual accept() */ + ret = client_ctx->fd = (int) accept( bind_ctx->fd, + (struct sockaddr *) &client_addr, &n ); + } + else + { + /* UDP: wait for a message, but keep it in the queue */ + char buf[1] = { 0 }; + + ret = recvfrom( bind_ctx->fd, buf, sizeof( buf ), MSG_PEEK, + (struct sockaddr *) &client_addr, &n ); + +#if defined(_WIN32) + if( ret == SOCKET_ERROR && + WSAGetLastError() == WSAEMSGSIZE ) + { + /* We know buf is too small, thanks, just peeking here */ + ret = 0; + } +#endif + } + + if( ret < 0 ) + { + if( net_would_block( bind_ctx ) != 0 ) + return( MBEDTLS_ERR_SSL_WANT_READ ); + + return( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + } + + /* UDP: hijack the listening socket to communicate with the client, + * then bind a new socket to accept new connections */ + if( type != SOCK_STREAM ) + { + struct sockaddr_in local_addr; + int one = 1; + + if( connect( bind_ctx->fd, (struct sockaddr *) &client_addr, n ) != 0 ) + return( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + + client_ctx->fd = bind_ctx->fd; + bind_ctx->fd = -1; /* In case we exit early */ + + n = sizeof( struct sockaddr_in ); + if( getsockname( client_ctx->fd, + (struct sockaddr *) &local_addr, &n ) != 0 || + ( bind_ctx->fd = (int) socket( AF_INET, + SOCK_DGRAM, IPPROTO_UDP ) ) < 0 || + setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR, + (const char *) &one, sizeof( one ) ) != 0 ) + { + return( MBEDTLS_ERR_NET_SOCKET_FAILED ); + } + + if( bind( bind_ctx->fd, (struct sockaddr *) &local_addr, n ) != 0 ) + { + return( MBEDTLS_ERR_NET_BIND_FAILED ); + } + } + + if( client_ip != NULL ) + { + struct sockaddr_in *addr4 = (struct sockaddr_in *) &client_addr; + *ip_len = sizeof( addr4->sin_addr.s_addr ); + + if( buf_size < *ip_len ) + return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL ); + + memcpy( client_ip, &addr4->sin_addr.s_addr, *ip_len ); + } + + return( 0 ); +} + +/* + * Set the socket blocking or non-blocking + */ +int mbedtls_net_set_block( mbedtls_net_context *ctx ) +{ +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + u_long n = 0; + return( ioctlsocket( ctx->fd, FIONBIO, &n ) ); +#else + return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) & ~O_NONBLOCK ) ); +#endif +} + +int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) +{ +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + u_long n = 1; + return( ioctlsocket( ctx->fd, FIONBIO, &n ) ); +#else + return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) | O_NONBLOCK ) ); +#endif +} + +/* + * Portable usleep helper + */ +void mbedtls_net_usleep( unsigned long usec ) +{ +#if defined(_WIN32) + Sleep( ( usec + 999 ) / 1000 ); +#else + struct timeval tv; + tv.tv_sec = usec / 1000000; +#if defined(__unix__) || defined(__unix) || \ + ( defined(__APPLE__) && defined(__MACH__) ) + tv.tv_usec = (suseconds_t) usec % 1000000; +#else + tv.tv_usec = usec % 1000000; +#endif + select( 0, NULL, NULL, NULL, &tv ); +#endif +} + +/* + * Read at most 'len' characters + */ +int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) +{ + int ret; + int fd = ((mbedtls_net_context *) ctx)->fd; + int error = 0; + get_errno(fd, &error); + if( fd < 0 ) + return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + + ret = (int) read( fd, buf, len ); + + if( ret < 0 ) + { + if( net_would_block( ctx ) != 0 ) + return( MBEDTLS_ERR_SSL_WANT_READ ); + +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + if( WSAGetLastError() == WSAECONNRESET ) + return( MBEDTLS_ERR_NET_CONN_RESET ); +#else + if( error == EPIPE || error == ECONNRESET ) + return( MBEDTLS_ERR_NET_CONN_RESET ); + + if( error == EINTR ) + return( MBEDTLS_ERR_SSL_WANT_READ ); +#endif + + return( MBEDTLS_ERR_NET_RECV_FAILED ); + } + + return( ret ); +} + +/* + * Read at most 'len' characters, blocking for at most 'timeout' ms + */ +int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len, + uint32_t timeout ) +{ + int ret; + struct timeval tv; + fd_set read_fds; + int fd = ((mbedtls_net_context *) ctx)->fd; + + if( fd < 0 ) + return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + + FD_ZERO( &read_fds ); + FD_SET( fd, &read_fds ); + + tv.tv_sec = timeout / 1000; + tv.tv_usec = ( timeout % 1000 ) * 1000; + + ret = select( fd + 1, &read_fds, NULL, NULL, timeout == 0 ? NULL : &tv ); + + /* Zero fds ready means we timed out */ + if( ret == 0 ) + return( MBEDTLS_ERR_SSL_TIMEOUT ); + + if( ret < 0 ) + { +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + if( WSAGetLastError() == WSAEINTR ) + return( MBEDTLS_ERR_SSL_WANT_READ ); +#else + if( errno == EINTR ) + return( MBEDTLS_ERR_SSL_WANT_READ ); +#endif + + return( MBEDTLS_ERR_NET_RECV_FAILED ); + } + + /* This call will not block */ + return( mbedtls_net_recv( ctx, buf, len ) ); +} + +/* + * Write at most 'len' characters + */ +int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) +{ + int ret; + int fd = ((mbedtls_net_context *) ctx)->fd; + + int error = 0; + get_errno(fd, &error); + + if( fd < 0 ) + return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + + ret = (int) write( fd, buf, len ); + + if( ret < 0 ) + { + if( net_would_block( ctx ) != 0 ) + return( MBEDTLS_ERR_SSL_WANT_WRITE ); + +#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + if( WSAGetLastError() == WSAECONNRESET ) + return( MBEDTLS_ERR_NET_CONN_RESET ); +#else + if( error == EPIPE || error == ECONNRESET ) + return( MBEDTLS_ERR_NET_CONN_RESET ); + + if( error == EINTR ) + return( MBEDTLS_ERR_SSL_WANT_WRITE ); +#endif + + return( MBEDTLS_ERR_NET_SEND_FAILED ); + } + + return( ret ); +} + +/* + * Gracefully close the connection + */ +void mbedtls_net_free( mbedtls_net_context *ctx ) +{ + if( ctx->fd == -1 ) + return; + + shutdown( ctx->fd, 2 ); + close( ctx->fd ); + + ctx->fd = -1; +} + +#endif /* MBEDTLS_NET_C */ From 1900c50d3b2bf017bf27f981e6caa8a991b11035 Mon Sep 17 00:00:00 2001 From: liuhan Date: Wed, 31 Aug 2016 11:43:48 +0800 Subject: [PATCH 06/57] components/mbedtls: modify hardware encryption feature rename "flag" and "keybites" in aes file, rename "xxx_starts" and add license in sha file. --- components/esp32/aes.c | 16 ++++++------- components/esp32/include/aes.h | 4 ++-- components/esp32/include/sha.h | 25 +++++++++++++------- components/esp32/sha.c | 12 +++++----- components/mbedtls/port/include/sha1_alt.h | 2 +- components/mbedtls/port/include/sha256_alt.h | 2 +- components/mbedtls/port/include/sha512_alt.h | 2 +- 7 files changed, 36 insertions(+), 27 deletions(-) diff --git a/components/esp32/aes.c b/components/esp32/aes.c index 3767dd7ee..bcc4eb2fd 100644 --- a/components/esp32/aes.c +++ b/components/esp32/aes.c @@ -77,9 +77,9 @@ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, break; default : return( ERR_AES_INVALID_KEY_LENGTH ); } - if (ctx->enc.flag == false){ - ctx->enc.flag = true; - ctx->enc.keybites = keybits; + if (ctx->enc.keyflag == false){ + ctx->enc.keyflag = true; + ctx->enc.keybits = keybits; memset(ctx->enc.key, 0, sizeof(ctx->enc.key)); memcpy(ctx->enc.key, key, keybyte); } else { @@ -108,9 +108,9 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, break; default : return( ERR_AES_INVALID_KEY_LENGTH ); } - if (ctx->dec.flag == false){ - ctx->dec.flag = true; - ctx->dec.keybites = keybits; + if (ctx->dec.keyflag == false){ + ctx->dec.keyflag = true; + ctx->dec.keybits = keybits; memset(ctx->dec.key, 0, sizeof(ctx->dec.key)); memcpy(ctx->dec.key, key, keybyte); } else { @@ -123,9 +123,9 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, static void esp_aes_process_enable(AES_CTX *ctx, int mode) { if( mode == AES_ENCRYPT ){ - esp_aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybites); + esp_aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybits); }else{ - esp_aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybites); + esp_aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybits); } return; } diff --git a/components/esp32/include/aes.h b/components/esp32/include/aes.h index b1a47eb4e..c3409cbaf 100644 --- a/components/esp32/include/aes.h +++ b/components/esp32/include/aes.h @@ -40,8 +40,8 @@ extern "C" { #define ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ typedef struct{ - bool flag; - uint16_t keybites; + bool keyflag; + uint16_t keybits; uint8_t key[32]; }key_context, KEY_CTX; diff --git a/components/esp32/include/sha.h b/components/esp32/include/sha.h index 301d893ae..93aed46e8 100644 --- a/components/esp32/include/sha.h +++ b/components/esp32/include/sha.h @@ -1,8 +1,17 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * - * esf Link List Descriptor - */ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #ifndef _ESP_SHA_H_ #define _ESP_SHA_H_ @@ -53,7 +62,7 @@ void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]); * * \param ctx context to be initialized */ -void esp_sha1_starts( SHA1_CTX *ctx ); +void esp_sha1_start( SHA1_CTX *ctx ); /** * \brief SHA-1 process buffer @@ -120,7 +129,7 @@ void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ); * \param ctx context to be initialized * \param is224 0 = use SHA256, 1 = use SHA224 */ -void esp_sha256_starts( SHA256_CTX *ctx, int is224 ); +void esp_sha256_start( SHA256_CTX *ctx, int is224 ); /** * \brief SHA-256 process buffer @@ -187,7 +196,7 @@ void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ); * \param ctx context to be initialized * \param is384 0 = use SHA512, 1 = use SHA384 */ -void esp_sha512_starts( SHA512_CTX *ctx, int is384 ); +void esp_sha512_start( SHA512_CTX *ctx, int is384 ); /** * \brief SHA-512 process buffer diff --git a/components/esp32/sha.c b/components/esp32/sha.c index e7d7e0be9..1a09ab7b5 100644 --- a/components/esp32/sha.c +++ b/components/esp32/sha.c @@ -69,7 +69,7 @@ void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) /* * SHA-1 context setup */ -void esp_sha1_starts( SHA1_CTX *ctx ) +void esp_sha1_start( SHA1_CTX *ctx ) { SHA_LOCK(); ets_sha_init(&ctx->context); @@ -102,7 +102,7 @@ void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char out SHA1_CTX ctx; esp_sha1_init( &ctx ); - esp_sha1_starts( &ctx ); + esp_sha1_start( &ctx ); esp_sha1_update( &ctx, input, ilen ); esp_sha1_finish( &ctx, output ); esp_sha1_free( &ctx ); @@ -147,7 +147,7 @@ void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) /* * SHA-256 context setup */ -void esp_sha256_starts( SHA256_CTX *ctx, int is224 ) +void esp_sha256_start( SHA256_CTX *ctx, int is224 ) { SHA_LOCK(); ets_sha_init(&ctx->context); @@ -187,7 +187,7 @@ void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char o SHA256_CTX ctx; esp_sha256_init( &ctx ); - esp_sha256_starts( &ctx, is224 ); + esp_sha256_start( &ctx, is224 ); esp_sha256_update( &ctx, input, ilen ); esp_sha256_finish( &ctx, output ); esp_sha256_free( &ctx ); @@ -232,7 +232,7 @@ void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) /* * SHA-512 context setup */ -void esp_sha512_starts( SHA512_CTX *ctx, int is384 ) +void esp_sha512_start( SHA512_CTX *ctx, int is384 ) { SHA_LOCK(); ets_sha_init(&ctx->context); @@ -274,7 +274,7 @@ void esp_sha512_output( const unsigned char *input, size_t ilen,unsigned char ou SHA512_CTX ctx; esp_sha512_init( &ctx ); - esp_sha512_starts( &ctx, is384 ); + esp_sha512_start( &ctx, is384 ); esp_sha512_update( &ctx, input, ilen ); esp_sha512_finish( &ctx, output ); esp_sha512_free( &ctx ); diff --git a/components/mbedtls/port/include/sha1_alt.h b/components/mbedtls/port/include/sha1_alt.h index 2cb0e926d..98cbf5b62 100644 --- a/components/mbedtls/port/include/sha1_alt.h +++ b/components/mbedtls/port/include/sha1_alt.h @@ -17,7 +17,7 @@ extern "C" { typedef SHA1_CTX mbedtls_sha1_context; #define mbedtls_sha1_init esp_sha1_init -#define mbedtls_sha1_starts esp_sha1_starts +#define mbedtls_sha1_starts esp_sha1_start #define mbedtls_sha1_clone esp_sha1_clone #define mbedtls_sha1_update esp_sha1_update #define mbedtls_sha1_finish esp_sha1_finish diff --git a/components/mbedtls/port/include/sha256_alt.h b/components/mbedtls/port/include/sha256_alt.h index 00beb2d28..e8585e976 100644 --- a/components/mbedtls/port/include/sha256_alt.h +++ b/components/mbedtls/port/include/sha256_alt.h @@ -19,7 +19,7 @@ typedef SHA256_CTX mbedtls_sha256_context; #define mbedtls_sha256_init esp_sha256_init #define mbedtls_sha256_clone esp_sha256_clone -#define mbedtls_sha256_starts esp_sha256_starts +#define mbedtls_sha256_starts esp_sha256_start #define mbedtls_sha256_update esp_sha256_update #define mbedtls_sha256_finish esp_sha256_finish #define mbedtls_sha256_free esp_sha256_free diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h index 7814bf19d..117660dcd 100644 --- a/components/mbedtls/port/include/sha512_alt.h +++ b/components/mbedtls/port/include/sha512_alt.h @@ -19,7 +19,7 @@ typedef SHA512_CTX mbedtls_sha512_context; #define mbedtls_sha512_init esp_sha512_init #define mbedtls_sha512_process esp_sha512_process #define mbedtls_sha512_clone esp_sha512_clone -#define mbedtls_sha512_starts esp_sha512_starts +#define mbedtls_sha512_starts esp_sha512_start #define mbedtls_sha512_update esp_sha512_update #define mbedtls_sha512_finish esp_sha512_finish #define mbedtls_sha512_free esp_sha512_free From 09aa6ebc856667e0914155aae0104f65a4d6c4a9 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 1 Sep 2016 08:28:03 +1000 Subject: [PATCH 07/57] lwip Makefile: Add POSIX headers to include path to #include , etc, works. --- components/lwip/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/lwip/Makefile b/components/lwip/Makefile index e159c25c2..cf9c361f5 100644 --- a/components/lwip/Makefile +++ b/components/lwip/Makefile @@ -2,7 +2,7 @@ # Component Makefile # -COMPONENT_ADD_INCLUDEDIRS := include/lwip include/lwip/port +COMPONENT_ADD_INCLUDEDIRS := include/lwip include/lwip/port include/lwip/posix COMPONENT_SRCDIRS := api apps/sntp apps core/ipv4 core/ipv6 core netif port/freertos port/netif port From f4ff32977df57f67a3fb036d8efff632ca918943 Mon Sep 17 00:00:00 2001 From: liuhan Date: Thu, 1 Sep 2016 10:53:23 +0800 Subject: [PATCH 08/57] components/mbedtls: modify MBEDTLS net feature modify get the connection's 'errno' info by calling getsockopt function. --- components/mbedtls/port/net.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/components/mbedtls/port/net.c b/components/mbedtls/port/net.c index f712d9a65..61162a78e 100644 --- a/components/mbedtls/port/net.c +++ b/components/mbedtls/port/net.c @@ -68,6 +68,14 @@ static int net_prepare( void ) return( 0 ); } +static int mbedtls_net_errno(int fd) +{ + int sock_errno = 0; + u32_t optlen = sizeof(sock_errno); + getsockopt(fd, SOL_SOCKET, SO_ERROR, &sock_errno, &optlen); + return sock_errno; +} + /* * Initialize a context */ @@ -225,8 +233,8 @@ static int net_would_block( const mbedtls_net_context *ctx ) if( ( fcntl( ctx->fd, F_GETFL, 0) & O_NONBLOCK ) != O_NONBLOCK ) return( 0 ); - int error = 0; - get_errno(ctx->fd, &error); + int error = mbedtls_net_errno(ctx->fd); + switch( error ) { #if defined EAGAIN @@ -393,7 +401,7 @@ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) int ret; int fd = ((mbedtls_net_context *) ctx)->fd; int error = 0; - get_errno(fd, &error); + if( fd < 0 ) return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); @@ -404,6 +412,7 @@ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) if( net_would_block( ctx ) != 0 ) return( MBEDTLS_ERR_SSL_WANT_READ ); + error = mbedtls_net_errno(fd); #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) if( WSAGetLastError() == WSAECONNRESET ) @@ -475,7 +484,6 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) int fd = ((mbedtls_net_context *) ctx)->fd; int error = 0; - get_errno(fd, &error); if( fd < 0 ) return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); @@ -487,6 +495,7 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) if( net_would_block( ctx ) != 0 ) return( MBEDTLS_ERR_SSL_WANT_WRITE ); + error = mbedtls_net_errno(fd); #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) if( WSAGetLastError() == WSAECONNRESET ) From fc2bfc1f4911c6b5310d51f3b7b3d0dcaa4f93f5 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Fri, 2 Sep 2016 11:31:38 +0800 Subject: [PATCH 09/57] mbedtls: just format related files method from !46 --- components/esp32/aes.c | 347 ++++++++++--------- components/esp32/esp_crypto.c | 50 +-- components/esp32/include/aes.h | 61 ++-- components/esp32/include/esp_crypto.h | 48 +-- components/esp32/include/sha.h | 10 +- components/esp32/sha.c | 96 ++--- components/mbedtls/port/esp_hardware.c | 36 +- components/mbedtls/port/include/aes_alt.h | 26 +- components/mbedtls/port/include/bignum_alt.h | 90 ++--- components/mbedtls/port/include/sha1_alt.h | 20 +- components/mbedtls/port/include/sha256_alt.h | 20 +- components/mbedtls/port/include/sha512_alt.h | 22 +- components/mbedtls/port/net.c | 296 ++++++++-------- 13 files changed, 574 insertions(+), 548 deletions(-) diff --git a/components/esp32/aes.c b/components/esp32/aes.c index bcc4eb2fd..e22c08a37 100644 --- a/components/esp32/aes.c +++ b/components/esp32/aes.c @@ -39,100 +39,112 @@ void esp_aes_init( AES_CTX *ctx ) AES_LOCK(); AES_TAKE(); - ets_aes_enable(); - AES_UNLOCK(); + ets_aes_enable(); + AES_UNLOCK(); } void esp_aes_free( AES_CTX *ctx ) { - if( ctx == NULL ) + if ( ctx == NULL ) { return; + } bzero( ctx, sizeof( AES_CTX ) ); AES_LOCK(); AES_GIVE(); - if (false == AES_IS_USED()) - ets_aes_disable(); - AES_UNLOCK(); + + if (false == AES_IS_USED()) { + ets_aes_disable(); + } + + AES_UNLOCK(); } /* * AES key schedule (encryption) */ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { - enum AES_BITS keybit; - uint16_t keybyte = keybits / 8; - switch (keybits){ - case 128: - keybit = AES128; - break; - case 192: - keybit = AES192; - break; - case 256: - keybit = AES256; - break; - default : return( ERR_AES_INVALID_KEY_LENGTH ); - } - if (ctx->enc.keyflag == false){ - ctx->enc.keyflag = true; - ctx->enc.keybits = keybits; - memset(ctx->enc.key, 0, sizeof(ctx->enc.key)); - memcpy(ctx->enc.key, key, keybyte); - } else { - ets_aes_setkey_enc(key, keybit); - } - return 0; + enum AES_BITS keybit; + uint16_t keybyte = keybits / 8; + + switch (keybits) { + case 128: + keybit = AES128; + break; + case 192: + keybit = AES192; + break; + case 256: + keybit = AES256; + break; + default: + return ( ERR_AES_INVALID_KEY_LENGTH ); + } + + if (ctx->enc.keyflag == false) { + ctx->enc.keyflag = true; + ctx->enc.keybits = keybits; + memset(ctx->enc.key, 0, sizeof(ctx->enc.key)); + memcpy(ctx->enc.key, key, keybyte); + } else { + ets_aes_setkey_enc(key, keybit); + } + + return 0; } /* * AES key schedule (decryption) */ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, - unsigned int keybits ) + unsigned int keybits ) { - enum AES_BITS keybit; - uint16_t keybyte = keybits / 8; - switch (keybits){ - case 128: - keybit = AES128; - break; - case 192: - keybit = AES192; - break; - case 256: - keybit = AES256; - break; - default : return( ERR_AES_INVALID_KEY_LENGTH ); - } - if (ctx->dec.keyflag == false){ - ctx->dec.keyflag = true; - ctx->dec.keybits = keybits; - memset(ctx->dec.key, 0, sizeof(ctx->dec.key)); - memcpy(ctx->dec.key, key, keybyte); - } else { - ets_aes_setkey_dec(key, keybit); - } - return 0; + enum AES_BITS keybit; + uint16_t keybyte = keybits / 8; + switch (keybits) { + case 128: + keybit = AES128; + break; + case 192: + keybit = AES192; + break; + case 256: + keybit = AES256; + break; + default: + return ( ERR_AES_INVALID_KEY_LENGTH ); + } + + if (ctx->dec.keyflag == false) { + ctx->dec.keyflag = true; + ctx->dec.keybits = keybits; + memset(ctx->dec.key, 0, sizeof(ctx->dec.key)); + memcpy(ctx->dec.key, key, keybyte); + } else { + ets_aes_setkey_dec(key, keybit); + } + + return 0; } static void esp_aes_process_enable(AES_CTX *ctx, int mode) { - if( mode == AES_ENCRYPT ){ - esp_aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybits); - }else{ - esp_aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybits); - } - return; + if ( mode == AES_ENCRYPT ) { + esp_aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybits); + } else { + esp_aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybits); + } + + return; } static void esp_aes_process_disable(AES_CTX *ctx, int mode) { - + } /* @@ -140,11 +152,12 @@ static void esp_aes_process_disable(AES_CTX *ctx, int mode) */ void esp_aes_encrypt( AES_CTX *ctx, - const unsigned char input[16], - unsigned char output[16] ) + const unsigned char input[16], + unsigned char output[16] ) { - ets_aes_crypt(input, output); - return ; + ets_aes_crypt(input, output); + + return ; } @@ -153,11 +166,12 @@ void esp_aes_encrypt( AES_CTX *ctx, */ void esp_aes_decrypt( AES_CTX *ctx, - const unsigned char input[16], - unsigned char output[16] ) + const unsigned char input[16], + unsigned char output[16] ) { - ets_aes_crypt(input, output); - return ; + ets_aes_crypt(input, output); + + return ; } @@ -165,24 +179,25 @@ void esp_aes_decrypt( AES_CTX *ctx, * AES-ECB block encryption/decryption */ int esp_aes_crypt_ecb( AES_CTX *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) + int mode, + const unsigned char input[16], + unsigned char output[16] ) { - AES_LOCK(); - - esp_aes_process_enable(ctx, mode); + AES_LOCK(); - if( mode == AES_ENCRYPT ) + esp_aes_process_enable(ctx, mode); + + if ( mode == AES_ENCRYPT ) { esp_aes_encrypt( ctx, input, output ); - else + } else { esp_aes_decrypt( ctx, input, output ); + } - esp_aes_process_disable(ctx, mode); - - AES_UNLOCK(); - - return 0; + esp_aes_process_disable(ctx, mode); + + AES_UNLOCK(); + + return 0; } @@ -190,27 +205,27 @@ int esp_aes_crypt_ecb( AES_CTX *ctx, * AES-CBC buffer encryption/decryption */ int esp_aes_crypt_cbc( AES_CTX *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - int i; + int i; unsigned char temp[16]; - if( length % 16 ) - return( ERR_AES_INVALID_INPUT_LENGTH ); + if ( length % 16 ) { + return ( ERR_AES_INVALID_INPUT_LENGTH ); + } - if( mode == AES_DECRYPT ) - { - while( length > 0 ) - { + if ( mode == AES_DECRYPT ) { + while ( length > 0 ) { memcpy( temp, input, 16 ); esp_aes_crypt_ecb( ctx, mode, input, output ); - for( i = 0; i < 16; i++ ) + for ( i = 0; i < 16; i++ ) { output[i] = (unsigned char)( output[i] ^ iv[i] ); + } memcpy( iv, temp, 16 ); @@ -218,13 +233,11 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, output += 16; length -= 16; } - } - else - { - while( length > 0 ) - { - for( i = 0; i < 16; i++ ) + } else { + while ( length > 0 ) { + for ( i = 0; i < 16; i++ ) { output[i] = (unsigned char)( input[i] ^ iv[i] ); + } esp_aes_crypt_ecb( ctx, mode, output, output ); memcpy( iv, output, 16 ); @@ -235,85 +248,83 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, } } - return 0; + return 0; } /* * AES-CFB128 buffer encryption/decryption */ int esp_aes_crypt_cfb128( AES_CTX *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - int c; - size_t n = *iv_off; + int c; + size_t n = *iv_off; - if( mode == AES_DECRYPT ) - { - while( length-- ) - { - if( n == 0 ) - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + if ( mode == AES_DECRYPT ) { + while ( length-- ) { + if ( n == 0 ) { + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + } - c = *input++; - *output++ = (unsigned char)( c ^ iv[n] ); - iv[n] = (unsigned char) c; - - n = ( n + 1 ) & 0x0F; - } - } - else - { - while( length-- ) - { - if( n == 0 ) - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); - - iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); - - n = ( n + 1 ) & 0x0F; - } - } - - *iv_off = n; + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; - return 0; + n = ( n + 1 ) & 0x0F; + } + } else { + while ( length-- ) { + if ( n == 0 ) { + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + } + + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + + n = ( n + 1 ) & 0x0F; + } + } + + *iv_off = n; + + return 0; } /* * AES-CFB8 buffer encryption/decryption */ int esp_aes_crypt_cfb8( AES_CTX *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ) + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) { - unsigned char c; - unsigned char ov[17]; + unsigned char c; + unsigned char ov[17]; - while( length-- ) - { - memcpy( ov, iv, 16 ); - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); - - if( mode == AES_DECRYPT ) - ov[16] = *input; - - c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + while ( length-- ) { + memcpy( ov, iv, 16 ); + esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); - if( mode == AES_ENCRYPT ) - ov[16] = c; - - memcpy( iv, ov + 1, 16 ); - } + if ( mode == AES_DECRYPT ) { + ov[16] = *input; + } - return 0; + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if ( mode == AES_ENCRYPT ) { + ov[16] = c; + } + + memcpy( iv, ov + 1, 16 ); + } + + return 0; } /* @@ -326,18 +337,18 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, unsigned char stream_block[16], const unsigned char *input, unsigned char *output ) -{ - int c, i; +{ + int c, i; size_t n = *nc_off; - while( length-- ) - { - if( n == 0 ) { + while ( length-- ) { + if ( n == 0 ) { esp_aes_crypt_ecb( ctx, AES_ENCRYPT, nonce_counter, stream_block ); - for( i = 16; i > 0; i-- ) - if( ++nonce_counter[i - 1] != 0 ) + for ( i = 16; i > 0; i-- ) + if ( ++nonce_counter[i - 1] != 0 ) { break; + } } c = *input++; *output++ = (unsigned char)( c ^ stream_block[n] ); @@ -347,6 +358,6 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, *nc_off = n; - return 0; + return 0; } diff --git a/components/esp32/esp_crypto.c b/components/esp32/esp_crypto.c index f0e2cdcb1..0a5cd2f47 100644 --- a/components/esp32/esp_crypto.c +++ b/components/esp32/esp_crypto.c @@ -6,59 +6,61 @@ static SemaphoreHandle_t esp_crypto_mutex[MUTEX_MAX_NUM]; static int esp_crypto_sig[MUTEX_MAX_NUM]; #if 0 - #define ESP_DEBUG ets_printf +#define ESP_DEBUG ets_printf #else - #define ESP_DEBUG(...) +#define ESP_DEBUG(...) #endif int esp_crypto_init(void) { - int i; + int i; - for (i = 0; i < MUTEX_MAX_NUM; i++) { - esp_crypto_mutex[i] = xSemaphoreCreateMutex(); - ESP_DEBUG("init num %d mutex %p\n", i, esp_crypto_mutex[i]); - if (!esp_crypto_mutex[i]) { - goto failed1; - } - esp_crypto_sig[i] = 0; - } + for (i = 0; i < MUTEX_MAX_NUM; i++) { + esp_crypto_mutex[i] = xSemaphoreCreateMutex(); + ESP_DEBUG("init num %d mutex %p\n", i, esp_crypto_mutex[i]); + if (!esp_crypto_mutex[i]) { + goto failed1; + } + esp_crypto_sig[i] = 0; + } - return 0; + return 0; failed1: - ESP_DEBUG("esp_crypto_init failed\n"); - for (i--; i >= 0; i--) - vQueueDelete(esp_crypto_mutex[i]); + ESP_DEBUG("esp_crypto_init failed\n"); + for (i--; i >= 0; i--) { + vQueueDelete(esp_crypto_mutex[i]); + } - return -1; + return -1; } void esp_crypto_lock(unsigned int num) { - ESP_DEBUG("1num %d, mutex %p\n", num, esp_crypto_mutex[num]); - xSemaphoreTake(esp_crypto_mutex[num], portMAX_DELAY); + ESP_DEBUG("1num %d, mutex %p\n", num, esp_crypto_mutex[num]); + xSemaphoreTake(esp_crypto_mutex[num], portMAX_DELAY); } void esp_crypto_unlock(unsigned int num) { - ESP_DEBUG("2num %d, mutex %p\n", num, esp_crypto_mutex[num]); - xSemaphoreGive(esp_crypto_mutex[num]); + ESP_DEBUG("2num %d, mutex %p\n", num, esp_crypto_mutex[num]); + xSemaphoreGive(esp_crypto_mutex[num]); } void esp_crypto_take(unsigned int num) { - esp_crypto_sig[num]++; + esp_crypto_sig[num]++; } void esp_crypto_give(unsigned int num) { - if (esp_crypto_sig[num]) - esp_crypto_sig[num]--; + if (esp_crypto_sig[num]) { + esp_crypto_sig[num]--; + } } bool esp_crypto_is_used(unsigned int num) { - return (esp_crypto_sig[num] != 0) ? true : false; + return (esp_crypto_sig[num] != 0) ? true : false; } diff --git a/components/esp32/include/aes.h b/components/esp32/include/aes.h index c3409cbaf..76ea47c55 100644 --- a/components/esp32/include/aes.h +++ b/components/esp32/include/aes.h @@ -18,9 +18,9 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * + * */ - + #ifndef ESP_AES_H #define ESP_AES_H @@ -39,11 +39,11 @@ extern "C" { #define ERR_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ #define ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ -typedef struct{ - bool keyflag; - uint16_t keybits; +typedef struct { + bool keyflag; + uint16_t keybits; uint8_t key[32]; -}key_context, KEY_CTX; +} key_context, KEY_CTX; /** * \brief AES context structure @@ -53,13 +53,12 @@ typedef struct{ * - to simplify key expansion in the 256-bit case by * generating an extra round key */ -typedef struct -{ +typedef struct { int nr; /*!< number of rounds */ uint32_t *rk; /*!< AES round keys */ - KEY_CTX enc; - KEY_CTX dec; -}aes_context, AES_CTX; + KEY_CTX enc; + KEY_CTX dec; +} aes_context, AES_CTX; /** * \brief Initialize AES context @@ -84,7 +83,7 @@ void esp_aes_free( AES_CTX *ctx ); * * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH */ -int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); +int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -95,7 +94,7 @@ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key,unsigned int keyb * * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH */ -int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key,unsigned int keybits ); +int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -107,7 +106,7 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key,unsigned int keyb * * \return 0 if successful */ -int esp_aes_crypt_ecb( AES_CTX *ctx,int mode,const unsigned char input[16],unsigned char output[16] ); +int esp_aes_crypt_ecb( AES_CTX *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); /** * \brief AES-CBC buffer encryption/decryption @@ -132,11 +131,11 @@ int esp_aes_crypt_ecb( AES_CTX *ctx,int mode,const unsigned char input[16],unsig * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH */ int esp_aes_crypt_cbc( AES_CTX *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** @@ -165,12 +164,12 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, * \return 0 if successful */ int esp_aes_crypt_cfb128( AES_CTX *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** * \brief AES-CFB8 buffer encryption/decryption. @@ -197,11 +196,11 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, * \return 0 if successful */ int esp_aes_crypt_cfb8( AES_CTX *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output ); + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); /** * \brief AES-CTR buffer encryption/decryption @@ -243,7 +242,7 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, * \param input Plaintext block * \param output Output (ciphertext) block */ -void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16],unsigned char output[16] ); +void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ); /** * \brief Internal AES block decryption function diff --git a/components/esp32/include/esp_crypto.h b/components/esp32/include/esp_crypto.h index 5accfe838..bac07ceac 100644 --- a/components/esp32/include/esp_crypto.h +++ b/components/esp32/include/esp_crypto.h @@ -9,11 +9,11 @@ extern "C" { #endif enum { - AES_MUTEX = 0, - BIGNUM_MUTEX, - SHA_MUTEX, + AES_MUTEX = 0, + BIGNUM_MUTEX, + SHA_MUTEX, - MUTEX_MAX_NUM, + MUTEX_MAX_NUM, }; int esp_crypto_init(void); @@ -25,29 +25,29 @@ void esp_crypto_take(unsigned int num); void esp_crypto_give(unsigned int num); bool esp_crypto_is_used(unsigned int num); -#define MUTEX_LOCK(num) esp_crypto_lock(num) -#define MUTEX_UNLOCK(num) esp_crypto_unlock(num) +#define MUTEX_LOCK(num) esp_crypto_lock(num) +#define MUTEX_UNLOCK(num) esp_crypto_unlock(num) -#define SIG_TAKE(num) esp_crypto_take(num) -#define SIG_GIVE(num) esp_crypto_give(num) -#define SIG_IS_USED(num) esp_crypto_is_used(num) +#define SIG_TAKE(num) esp_crypto_take(num) +#define SIG_GIVE(num) esp_crypto_give(num) +#define SIG_IS_USED(num) esp_crypto_is_used(num) -#define AES_LOCK() MUTEX_LOCK(AES_MUTEX) -#define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) -#define BIGNUM_LOCK() MUTEX_LOCK(BIGNUM_MUTEX) -#define BIGNUM_UNLOCK() MUTEX_UNLOCK(BIGNUM_MUTEX) -#define SHA_LOCK() MUTEX_LOCK(SHA_MUTEX) -#define SHA_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) +#define AES_LOCK() MUTEX_LOCK(AES_MUTEX) +#define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) +#define BIGNUM_LOCK() MUTEX_LOCK(BIGNUM_MUTEX) +#define BIGNUM_UNLOCK() MUTEX_UNLOCK(BIGNUM_MUTEX) +#define SHA_LOCK() MUTEX_LOCK(SHA_MUTEX) +#define SHA_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) -#define AES_TAKE() SIG_TAKE(AES_MUTEX) -#define AES_GIVE() SIG_GIVE(AES_MUTEX) -#define AES_IS_USED() SIG_IS_USED(AES_MUTEX) -#define BIGNUM_TAKE() SIG_TAKE(BIGNUM_MUTEX) -#define BIGNUM_GIVE() SIG_GIVE(BIGNUM_MUTEX) -#define BIGNUM_IS_USED() SIG_IS_USED(BIGNUM_MUTEX) -#define SHA_TAKE() SIG_TAKE(SHA_MUTEX) -#define SHA_GIVE() SIG_GIVE(SHA_MUTEX) -#define SHA_IS_USED() SIG_IS_USED(SHA_MUTEX) +#define AES_TAKE() SIG_TAKE(AES_MUTEX) +#define AES_GIVE() SIG_GIVE(AES_MUTEX) +#define AES_IS_USED() SIG_IS_USED(AES_MUTEX) +#define BIGNUM_TAKE() SIG_TAKE(BIGNUM_MUTEX) +#define BIGNUM_GIVE() SIG_GIVE(BIGNUM_MUTEX) +#define BIGNUM_IS_USED() SIG_IS_USED(BIGNUM_MUTEX) +#define SHA_TAKE() SIG_TAKE(SHA_MUTEX) +#define SHA_GIVE() SIG_GIVE(SHA_MUTEX) +#define SHA_IS_USED() SIG_IS_USED(SHA_MUTEX) #ifdef __cplusplus } diff --git a/components/esp32/include/sha.h b/components/esp32/include/sha.h index 93aed46e8..2ee667cf7 100644 --- a/components/esp32/include/sha.h +++ b/components/esp32/include/sha.h @@ -26,9 +26,9 @@ extern "C" { /** * \brief SHA-1 context structure */ -typedef struct{ - SHA_CTX context; - int context_type; +typedef struct { + SHA_CTX context; + int context_type; } sha_context; typedef sha_context SHA1_CTX; @@ -91,8 +91,8 @@ void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ); void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ); /// -#define SHA256 SHA2_256 -#define SHA224 4 +#define SHA256 SHA2_256 +#define SHA224 4 /** * \brief SHA-256 context structure diff --git a/components/esp32/sha.c b/components/esp32/sha.c index 1a09ab7b5..cc850f084 100644 --- a/components/esp32/sha.c +++ b/components/esp32/sha.c @@ -38,22 +38,26 @@ void esp_sha1_init( SHA1_CTX *ctx ) SHA_LOCK(); SHA_TAKE(); - ets_sha_enable(); - SHA_UNLOCK(); + ets_sha_enable(); + SHA_UNLOCK(); } void esp_sha1_free( SHA1_CTX *ctx ) { - if( ctx == NULL ) + if ( ctx == NULL ) { return; + } bzero( ctx, sizeof( SHA1_CTX ) ); SHA_LOCK(); SHA_GIVE(); - if (false == SHA_IS_USED()) - ets_sha_disable(); - SHA_UNLOCK(); + + if (false == SHA_IS_USED()) { + ets_sha_disable(); + } + + SHA_UNLOCK(); } void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) @@ -71,10 +75,10 @@ void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) */ void esp_sha1_start( SHA1_CTX *ctx ) { - SHA_LOCK(); - ets_sha_init(&ctx->context); + SHA_LOCK(); + ets_sha_init(&ctx->context); - ctx->context_type = SHA1; + ctx->context_type = SHA1; } /* @@ -82,7 +86,7 @@ void esp_sha1_start( SHA1_CTX *ctx ) */ void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) { - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } /* @@ -90,8 +94,8 @@ void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) */ void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) { - ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA_UNLOCK(); + ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA_UNLOCK(); } /* @@ -116,8 +120,8 @@ void esp_sha256_init( SHA256_CTX *ctx ) SHA_LOCK(); SHA_TAKE(); - ets_sha_enable(); - SHA_UNLOCK(); + ets_sha_enable(); + SHA_UNLOCK(); } void esp_sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) @@ -127,16 +131,20 @@ void esp_sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) void esp_sha256_free( SHA256_CTX *ctx ) { - if( ctx == NULL ) + if ( ctx == NULL ) { return; + } bzero( ctx, sizeof( SHA256_CTX ) ); SHA_LOCK(); SHA_GIVE(); - if (false == SHA_IS_USED()) - ets_sha_disable(); - SHA_UNLOCK(); + + if (false == SHA_IS_USED()) { + ets_sha_disable(); + } + + SHA_UNLOCK(); } void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) @@ -149,17 +157,16 @@ void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) */ void esp_sha256_start( SHA256_CTX *ctx, int is224 ) { - SHA_LOCK(); + SHA_LOCK(); ets_sha_init(&ctx->context); - if( is224 == 0 ) - { + if ( is224 == 0 ) { /* SHA-256 */ - ctx->context_type = SHA256; - }else{ - /* SHA-224 */ - ctx->context_type = SHA224; - } + ctx->context_type = SHA256; + } else { + /* SHA-224 */ + ctx->context_type = SHA224; + } } /* @@ -167,7 +174,7 @@ void esp_sha256_start( SHA256_CTX *ctx, int is224 ) */ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) { - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); + ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } /* @@ -175,8 +182,8 @@ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen */ void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) { - ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA_UNLOCK(); + ets_sha_finish(&ctx->context, ctx->context_type, output); + SHA_UNLOCK(); } /* @@ -201,8 +208,8 @@ void esp_sha512_init( SHA512_CTX *ctx ) SHA_LOCK(); SHA_TAKE(); - ets_sha_enable(); - SHA_UNLOCK(); + ets_sha_enable(); + SHA_UNLOCK(); } void esp_sha512_process( SHA512_CTX *ctx, const unsigned char data[128] ) @@ -212,16 +219,20 @@ void esp_sha512_process( SHA512_CTX *ctx, const unsigned char data[128] ) void esp_sha512_free( SHA512_CTX *ctx ) { - if( ctx == NULL ) + if ( ctx == NULL ) { return; + } bzero( ctx, sizeof( SHA512_CTX ) ); SHA_LOCK(); SHA_GIVE(); - if (false == SHA_IS_USED()) - ets_sha_disable(); - SHA_UNLOCK(); + + if (false == SHA_IS_USED()) { + ets_sha_disable(); + } + + SHA_UNLOCK(); } void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) @@ -234,16 +245,13 @@ void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) */ void esp_sha512_start( SHA512_CTX *ctx, int is384 ) { - SHA_LOCK(); - ets_sha_init(&ctx->context); + SHA_LOCK(); + ets_sha_init(&ctx->context); - if( is384 == 0 ) - { + if ( is384 == 0 ) { /* SHA-512 */ ctx->context_type = SHA2_512; - } - else - { + } else { /* SHA-384 */ ctx->context_type = SHA2_384; } @@ -252,7 +260,7 @@ void esp_sha512_start( SHA512_CTX *ctx, int is384 ) /* * SHA-512 process buffer */ -void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input,size_t ilen ) +void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen ) { ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -269,7 +277,7 @@ void esp_sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) /* * output = SHA-512( input buffer ) */ -void esp_sha512_output( const unsigned char *input, size_t ilen,unsigned char output[64], int is384 ) +void esp_sha512_output( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ) { SHA512_CTX ctx; diff --git a/components/mbedtls/port/esp_hardware.c b/components/mbedtls/port/esp_hardware.c index c269a0e3f..b83c4d7aa 100644 --- a/components/mbedtls/port/esp_hardware.c +++ b/components/mbedtls/port/esp_hardware.c @@ -7,6 +7,7 @@ #include #include #include + #if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) /** * \brief Entropy poll callback for a hardware source @@ -18,28 +19,31 @@ */ static int os_get_random(unsigned char *buf, size_t len) { - int i, j; - unsigned long tmp; - for (i = 0; i < ((len + 3) & ~3) / 4; i ++){ - tmp = rand(); - for (j = 0; j < 4; j ++){ - if ((i * 4 + j) < len){ - buf[i * 4 + j] = (unsigned char)(tmp >> (j * 8)); - }else{ - break; - } - } + int i, j; + unsigned long tmp; - } - return 0; + for (i = 0; i < ((len + 3) & ~3) / 4; i ++) { + tmp = rand(); + for (j = 0; j < 4; j ++) { + if ((i * 4 + j) < len) { + buf[i * 4 + j] = (unsigned char)(tmp >> (j * 8)); + } else { + break; + } + } + + } + + return 0; } int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen ) { - os_get_random(output, len); - *olen = len; - return 0; + os_get_random(output, len); + *olen = len; + + return 0; } #endif diff --git a/components/mbedtls/port/include/aes_alt.h b/components/mbedtls/port/include/aes_alt.h index 90e659483..daf30d72b 100644 --- a/components/mbedtls/port/include/aes_alt.h +++ b/components/mbedtls/port/include/aes_alt.h @@ -18,9 +18,9 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * + * */ - + #ifndef AES_ALT_H #define AES_ALT_H @@ -33,23 +33,23 @@ extern "C" { typedef AES_CTX mbedtls_aes_context; -#define mbedtls_aes_init esp_aes_init -#define mbedtls_aes_free esp_aes_free -#define mbedtls_aes_setkey_enc esp_aes_setkey_enc -#define mbedtls_aes_setkey_dec esp_aes_setkey_dec -#define mbedtls_aes_crypt_ecb esp_aes_crypt_ecb +#define mbedtls_aes_init esp_aes_init +#define mbedtls_aes_free esp_aes_free +#define mbedtls_aes_setkey_enc esp_aes_setkey_enc +#define mbedtls_aes_setkey_dec esp_aes_setkey_dec +#define mbedtls_aes_crypt_ecb esp_aes_crypt_ecb #if defined(MBEDTLS_CIPHER_MODE_CBC) -#define mbedtls_aes_crypt_cbc esp_aes_crypt_cbc +#define mbedtls_aes_crypt_cbc esp_aes_crypt_cbc #endif #if defined(MBEDTLS_CIPHER_MODE_CFB) -#define mbedtls_aes_crypt_cfb128 esp_aes_crypt_cfb128 -#define mbedtls_aes_crypt_cfb8 esp_aes_crypt_cfb8 +#define mbedtls_aes_crypt_cfb128 esp_aes_crypt_cfb128 +#define mbedtls_aes_crypt_cfb8 esp_aes_crypt_cfb8 #endif #if defined(MBEDTLS_CIPHER_MODE_CTR) -#define mbedtls_aes_crypt_ctr esp_aes_crypt_ctr +#define mbedtls_aes_crypt_ctr esp_aes_crypt_ctr #endif -#define mbedtls_aes_encrypt esp_aes_encrypt -#define mbedtls_aes_decrypt esp_aes_decrypt +#define mbedtls_aes_encrypt esp_aes_encrypt +#define mbedtls_aes_decrypt esp_aes_decrypt #endif /* MBEDTLS_AES_ALT */ #ifdef __cplusplus diff --git a/components/mbedtls/port/include/bignum_alt.h b/components/mbedtls/port/include/bignum_alt.h index a4ac0db3e..f30d7d25c 100644 --- a/components/mbedtls/port/include/bignum_alt.h +++ b/components/mbedtls/port/include/bignum_alt.h @@ -19,7 +19,7 @@ * limitations under the License. * */ - + #ifndef BIGNUM_ALT_H #define BIGNUM_ALT_H @@ -27,50 +27,50 @@ #if defined(MBEDTLS_BIGNUM_ALT) -typedef MPI_CTX mbedtls_mpi; - -#define mbedtls_mpi_init esp_mpi_init -#define mbedtls_mpi_free esp_mpi_free -#define mbedtls_mpi_grow esp_mpi_grow -#define mbedtls_mpi_shrink esp_mpi_shrink -#define mbedtls_mpi_copy esp_mpi_copy -#define mbedtls_mpi_swap esp_mpi_swap -#define mbedtls_mpi_safe_cond_assign esp_mpi_safe_cond_assign -#define mbedtls_mpi_safe_cond_swap esp_mpi_safe_cond_swap -#define mbedtls_mpi_lset esp_mpi_lset -#define mbedtls_mpi_get_bit esp_mpi_get_bit -#define mbedtls_mpi_set_bit esp_mpi_set_bit -#define mbedtls_mpi_lsb esp_mpi_lsb -#define mbedtls_mpi_bitlen esp_mpi_bitlen -#define mbedtls_mpi_size esp_mpi_size -#define mbedtls_mpi_read_string esp_mpi_read_string -#define mbedtls_mpi_write_string esp_mpi_write_string -#define mbedtls_mpi_read_binary esp_mpi_read_binary -#define mbedtls_mpi_write_binary esp_mpi_write_binary -#define mbedtls_mpi_shift_l esp_mpi_shift_l -#define mbedtls_mpi_shift_r esp_mpi_shift_r -#define mbedtls_mpi_cmp_abs esp_mpi_cmp_abs -#define mbedtls_mpi_cmp_mpi esp_mpi_cmp_mpi -#define mbedtls_mpi_cmp_int esp_mpi_cmp_int -#define mbedtls_mpi_add_abs esp_mpi_add_abs -#define mbedtls_mpi_sub_abs esp_mpi_sub_abs -#define mbedtls_mpi_add_mpi esp_mpi_add_mpi -#define mbedtls_mpi_sub_mpi esp_mpi_sub_mpi -#define mbedtls_mpi_add_int esp_mpi_add_int -#define mbedtls_mpi_sub_int esp_mpi_sub_int -#define mbedtls_mpi_mul_mpi esp_mpi_mul_mpi -#define mbedtls_mpi_mul_int esp_mpi_mul_int -#define mbedtls_mpi_div_mpi esp_mpi_div_mpi -#define mbedtls_mpi_div_int esp_mpi_div_int -#define mbedtls_mpi_mod_mpi esp_mpi_mod_mpi -#define mbedtls_mpi_mod_int esp_mpi_mod_int -#define mbedtls_mpi_exp_mod esp_mpi_exp_mod -#define mbedtls_mpi_fill_random esp_mpi_fill_random -#define mbedtls_mpi_gcd esp_mpi_gcd -#define mbedtls_mpi_inv_mod esp_mpi_inv_mod -#define mbedtls_mpi_is_prime esp_mpi_is_prime -#define mbedtls_mpi_gen_prime esp_mpi_gen_prime - +typedef MPI_CTX mbedtls_mpi; + +#define mbedtls_mpi_init esp_mpi_init +#define mbedtls_mpi_free esp_mpi_free +#define mbedtls_mpi_grow esp_mpi_grow +#define mbedtls_mpi_shrink esp_mpi_shrink +#define mbedtls_mpi_copy esp_mpi_copy +#define mbedtls_mpi_swap esp_mpi_swap +#define mbedtls_mpi_safe_cond_assign esp_mpi_safe_cond_assign +#define mbedtls_mpi_safe_cond_swap esp_mpi_safe_cond_swap +#define mbedtls_mpi_lset esp_mpi_lset +#define mbedtls_mpi_get_bit esp_mpi_get_bit +#define mbedtls_mpi_set_bit esp_mpi_set_bit +#define mbedtls_mpi_lsb esp_mpi_lsb +#define mbedtls_mpi_bitlen esp_mpi_bitlen +#define mbedtls_mpi_size esp_mpi_size +#define mbedtls_mpi_read_string esp_mpi_read_string +#define mbedtls_mpi_write_string esp_mpi_write_string +#define mbedtls_mpi_read_binary esp_mpi_read_binary +#define mbedtls_mpi_write_binary esp_mpi_write_binary +#define mbedtls_mpi_shift_l esp_mpi_shift_l +#define mbedtls_mpi_shift_r esp_mpi_shift_r +#define mbedtls_mpi_cmp_abs esp_mpi_cmp_abs +#define mbedtls_mpi_cmp_mpi esp_mpi_cmp_mpi +#define mbedtls_mpi_cmp_int esp_mpi_cmp_int +#define mbedtls_mpi_add_abs esp_mpi_add_abs +#define mbedtls_mpi_sub_abs esp_mpi_sub_abs +#define mbedtls_mpi_add_mpi esp_mpi_add_mpi +#define mbedtls_mpi_sub_mpi esp_mpi_sub_mpi +#define mbedtls_mpi_add_int esp_mpi_add_int +#define mbedtls_mpi_sub_int esp_mpi_sub_int +#define mbedtls_mpi_mul_mpi esp_mpi_mul_mpi +#define mbedtls_mpi_mul_int esp_mpi_mul_int +#define mbedtls_mpi_div_mpi esp_mpi_div_mpi +#define mbedtls_mpi_div_int esp_mpi_div_int +#define mbedtls_mpi_mod_mpi esp_mpi_mod_mpi +#define mbedtls_mpi_mod_int esp_mpi_mod_int +#define mbedtls_mpi_exp_mod esp_mpi_exp_mod +#define mbedtls_mpi_fill_random esp_mpi_fill_random +#define mbedtls_mpi_gcd esp_mpi_gcd +#define mbedtls_mpi_inv_mod esp_mpi_inv_mod +#define mbedtls_mpi_is_prime esp_mpi_is_prime +#define mbedtls_mpi_gen_prime esp_mpi_gen_prime + #endif #endif diff --git a/components/mbedtls/port/include/sha1_alt.h b/components/mbedtls/port/include/sha1_alt.h index 98cbf5b62..3cf39d2ff 100644 --- a/components/mbedtls/port/include/sha1_alt.h +++ b/components/mbedtls/port/include/sha1_alt.h @@ -1,6 +1,6 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * +/* + * copyright (c) 2010 - 2012 Espressif System + * * esf Link List Descriptor */ #ifndef _SHA1_ALT_H_ @@ -16,13 +16,13 @@ extern "C" { typedef SHA1_CTX mbedtls_sha1_context; -#define mbedtls_sha1_init esp_sha1_init -#define mbedtls_sha1_starts esp_sha1_start -#define mbedtls_sha1_clone esp_sha1_clone -#define mbedtls_sha1_update esp_sha1_update -#define mbedtls_sha1_finish esp_sha1_finish -#define mbedtls_sha1_free esp_sha1_free -#define mbedtls_sha1_process esp_sha1_process +#define mbedtls_sha1_init esp_sha1_init +#define mbedtls_sha1_starts esp_sha1_start +#define mbedtls_sha1_clone esp_sha1_clone +#define mbedtls_sha1_update esp_sha1_update +#define mbedtls_sha1_finish esp_sha1_finish +#define mbedtls_sha1_free esp_sha1_free +#define mbedtls_sha1_process esp_sha1_process #endif diff --git a/components/mbedtls/port/include/sha256_alt.h b/components/mbedtls/port/include/sha256_alt.h index e8585e976..15ea356ac 100644 --- a/components/mbedtls/port/include/sha256_alt.h +++ b/components/mbedtls/port/include/sha256_alt.h @@ -1,6 +1,6 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * +/* + * copyright (c) 2010 - 2012 Espressif System + * * esf Link List Descriptor */ @@ -17,13 +17,13 @@ extern "C" { typedef SHA256_CTX mbedtls_sha256_context; -#define mbedtls_sha256_init esp_sha256_init -#define mbedtls_sha256_clone esp_sha256_clone -#define mbedtls_sha256_starts esp_sha256_start -#define mbedtls_sha256_update esp_sha256_update -#define mbedtls_sha256_finish esp_sha256_finish -#define mbedtls_sha256_free esp_sha256_free -#define mbedtls_sha256_process esp_sha256_process +#define mbedtls_sha256_init esp_sha256_init +#define mbedtls_sha256_clone esp_sha256_clone +#define mbedtls_sha256_starts esp_sha256_start +#define mbedtls_sha256_update esp_sha256_update +#define mbedtls_sha256_finish esp_sha256_finish +#define mbedtls_sha256_free esp_sha256_free +#define mbedtls_sha256_process esp_sha256_process #endif diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h index 117660dcd..9e337c1b6 100644 --- a/components/mbedtls/port/include/sha512_alt.h +++ b/components/mbedtls/port/include/sha512_alt.h @@ -1,6 +1,6 @@ -/* - * copyright (c) 2010 - 2012 Espressif System - * +/* + * copyright (c) 2010 - 2012 Espressif System + * * esf Link List Descriptor */ @@ -14,15 +14,15 @@ extern "C" { #if defined(MBEDTLS_SHA512_ALT) #include "sha.h" -typedef SHA512_CTX mbedtls_sha512_context; +typedef SHA512_CTX mbedtls_sha512_context; -#define mbedtls_sha512_init esp_sha512_init -#define mbedtls_sha512_process esp_sha512_process -#define mbedtls_sha512_clone esp_sha512_clone -#define mbedtls_sha512_starts esp_sha512_start -#define mbedtls_sha512_update esp_sha512_update -#define mbedtls_sha512_finish esp_sha512_finish -#define mbedtls_sha512_free esp_sha512_free +#define mbedtls_sha512_init esp_sha512_init +#define mbedtls_sha512_process esp_sha512_process +#define mbedtls_sha512_clone esp_sha512_clone +#define mbedtls_sha512_starts esp_sha512_start +#define mbedtls_sha512_update esp_sha512_update +#define mbedtls_sha512_finish esp_sha512_finish +#define mbedtls_sha512_free esp_sha512_free #endif diff --git a/components/mbedtls/port/net.c b/components/mbedtls/port/net.c index 61162a78e..390513c17 100644 --- a/components/mbedtls/port/net.c +++ b/components/mbedtls/port/net.c @@ -56,24 +56,26 @@ static int net_prepare( void ) !defined(EFI32) WSADATA wsaData; - if( wsa_init_done == 0 ) - { - if( WSAStartup( MAKEWORD(2,0), &wsaData ) != 0 ) - return( MBEDTLS_ERR_NET_SOCKET_FAILED ); + if ( wsa_init_done == 0 ) { + if ( WSAStartup( MAKEWORD(2, 0), &wsaData ) != 0 ) { + return ( MBEDTLS_ERR_NET_SOCKET_FAILED ); + } wsa_init_done = 1; } #else #endif - return( 0 ); + return ( 0 ); } static int mbedtls_net_errno(int fd) { - int sock_errno = 0; - u32_t optlen = sizeof(sock_errno); - getsockopt(fd, SOL_SOCKET, SO_ERROR, &sock_errno, &optlen); - return sock_errno; + int sock_errno = 0; + u32_t optlen = sizeof(sock_errno); + + getsockopt(fd, SOL_SOCKET, SO_ERROR, &sock_errno, &optlen); + + return sock_errno; } /* @@ -92,8 +94,9 @@ int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char int ret; struct addrinfo hints, *addr_list, *cur; - if( ( ret = net_prepare() ) != 0 ) - return( ret ); + if ( ( ret = net_prepare() ) != 0 ) { + return ( ret ); + } /* Do name resolution with both IPv6 and IPv4 */ memset( &hints, 0, sizeof( hints ) ); @@ -101,23 +104,21 @@ int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM; hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP; - if( getaddrinfo( host, port, &hints, &addr_list ) != 0 ) - return( MBEDTLS_ERR_NET_UNKNOWN_HOST ); + if ( getaddrinfo( host, port, &hints, &addr_list ) != 0 ) { + return ( MBEDTLS_ERR_NET_UNKNOWN_HOST ); + } /* Try the sockaddrs until a connection succeeds */ ret = MBEDTLS_ERR_NET_UNKNOWN_HOST; - for( cur = addr_list; cur != NULL; cur = cur->ai_next ) - { + for ( cur = addr_list; cur != NULL; cur = cur->ai_next ) { ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype, - cur->ai_protocol ); - if( ctx->fd < 0 ) - { + cur->ai_protocol ); + if ( ctx->fd < 0 ) { ret = MBEDTLS_ERR_NET_SOCKET_FAILED; continue; } - if( connect( ctx->fd, cur->ai_addr, cur->ai_addrlen ) == 0 ) - { + if ( connect( ctx->fd, cur->ai_addr, cur->ai_addrlen ) == 0 ) { ret = 0; break; } @@ -128,7 +129,7 @@ int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char freeaddrinfo( addr_list ); - return( ret ); + return ( ret ); } /* @@ -139,8 +140,9 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char int n, ret; struct addrinfo hints, *addr_list, *cur; - if( ( ret = net_prepare() ) != 0 ) - return( ret ); + if ( ( ret = net_prepare() ) != 0 ) { + return ( ret ); + } /* Bind to IPv6 and/or IPv4, but only in the desired protocol */ memset( &hints, 0, sizeof( hints ) ); @@ -148,48 +150,43 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char hints.ai_socktype = proto == MBEDTLS_NET_PROTO_UDP ? SOCK_DGRAM : SOCK_STREAM; hints.ai_protocol = proto == MBEDTLS_NET_PROTO_UDP ? IPPROTO_UDP : IPPROTO_TCP; - if( getaddrinfo( bind_ip, port, &hints, &addr_list ) != 0 ) - return( MBEDTLS_ERR_NET_UNKNOWN_HOST ); + if ( getaddrinfo( bind_ip, port, &hints, &addr_list ) != 0 ) { + return ( MBEDTLS_ERR_NET_UNKNOWN_HOST ); + } /* Try the sockaddrs until a binding succeeds */ ret = MBEDTLS_ERR_NET_UNKNOWN_HOST; - for( cur = addr_list; cur != NULL; cur = cur->ai_next ) - { + for ( cur = addr_list; cur != NULL; cur = cur->ai_next ) { ctx->fd = (int) socket( cur->ai_family, cur->ai_socktype, - cur->ai_protocol ); - if( ctx->fd < 0 ) - { + cur->ai_protocol ); + if ( ctx->fd < 0 ) { ret = MBEDTLS_ERR_NET_SOCKET_FAILED; continue; } - /*SO_REUSEADDR option dafault is disable in source code(lwip)*/ + /*SO_REUSEADDR option dafault is disable in source code(lwip)*/ #if SO_REUSE n = 1; - if( setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR, - (const char *) &n, sizeof( n ) ) != 0 ) - { + if ( setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR, + (const char *) &n, sizeof( n ) ) != 0 ) { close( ctx->fd ); ret = MBEDTLS_ERR_NET_SOCKET_FAILED; continue; } #endif - /*bind interface dafault don't process the addr is 0xffffffff for TCP Protocol*/ - struct sockaddr_in *serv_addr = NULL; - serv_addr = (struct sockaddr_in *)cur->ai_addr; - serv_addr->sin_addr.s_addr = htonl(INADDR_ANY); /* Any incoming interface */ - if( bind( ctx->fd, (struct sockaddr *)serv_addr, cur->ai_addrlen ) != 0 ) - { + /*bind interface dafault don't process the addr is 0xffffffff for TCP Protocol*/ + struct sockaddr_in *serv_addr = NULL; + serv_addr = (struct sockaddr_in *)cur->ai_addr; + serv_addr->sin_addr.s_addr = htonl(INADDR_ANY); /* Any incoming interface */ + if ( bind( ctx->fd, (struct sockaddr *)serv_addr, cur->ai_addrlen ) != 0 ) { close( ctx->fd ); ret = MBEDTLS_ERR_NET_BIND_FAILED; continue; } /* Listen only makes sense for TCP */ - if( proto == MBEDTLS_NET_PROTO_TCP ) - { - if( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 ) - { + if ( proto == MBEDTLS_NET_PROTO_TCP ) { + if ( listen( ctx->fd, MBEDTLS_NET_LISTEN_BACKLOG ) != 0 ) { close( ctx->fd ); ret = MBEDTLS_ERR_NET_LISTEN_FAILED; continue; @@ -203,7 +200,7 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char freeaddrinfo( addr_list ); - return( ret ); + return ( ret ); } @@ -216,7 +213,7 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char static int net_would_block( const mbedtls_net_context *ctx ) { ((void) ctx); - return( WSAGetLastError() == WSAEWOULDBLOCK ); + return ( WSAGetLastError() == WSAEWOULDBLOCK ); } #else /* @@ -230,22 +227,22 @@ static int net_would_block( const mbedtls_net_context *ctx ) /* * Never return 'WOULD BLOCK' on a non-blocking socket */ - if( ( fcntl( ctx->fd, F_GETFL, 0) & O_NONBLOCK ) != O_NONBLOCK ) - return( 0 ); + if ( ( fcntl( ctx->fd, F_GETFL, 0) & O_NONBLOCK ) != O_NONBLOCK ) { + return ( 0 ); + } - int error = mbedtls_net_errno(ctx->fd); - - switch( error ) - { + int error = mbedtls_net_errno(ctx->fd); + + switch ( error ) { #if defined EAGAIN - case EAGAIN: + case EAGAIN: #endif #if defined EWOULDBLOCK && EWOULDBLOCK != EAGAIN - case EWOULDBLOCK: + case EWOULDBLOCK: #endif - return( 1 ); + return ( 1 ); } - return( 0 ); + return ( 0 ); } #endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */ @@ -265,21 +262,17 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, socklen_t type_len = (socklen_t) sizeof( type ); /* Is this a TCP or UDP socket? */ - if( getsockopt( bind_ctx->fd, SOL_SOCKET, SO_TYPE, - (void *) &type, (socklen_t *) &type_len ) != 0 || - ( type != SOCK_STREAM && type != SOCK_DGRAM ) ) - { - return( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + if ( getsockopt( bind_ctx->fd, SOL_SOCKET, SO_TYPE, + (void *) &type, (socklen_t *) &type_len ) != 0 || + ( type != SOCK_STREAM && type != SOCK_DGRAM ) ) { + return ( MBEDTLS_ERR_NET_ACCEPT_FAILED ); } - if( type == SOCK_STREAM ) - { + if ( type == SOCK_STREAM ) { /* TCP: actual accept() */ ret = client_ctx->fd = (int) accept( bind_ctx->fd, (struct sockaddr *) &client_addr, &n ); - } - else - { + } else { /* UDP: wait for a message, but keep it in the queue */ char buf[1] = { 0 }; @@ -287,65 +280,62 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, (struct sockaddr *) &client_addr, &n ); #if defined(_WIN32) - if( ret == SOCKET_ERROR && - WSAGetLastError() == WSAEMSGSIZE ) - { + if ( ret == SOCKET_ERROR && + WSAGetLastError() == WSAEMSGSIZE ) { /* We know buf is too small, thanks, just peeking here */ ret = 0; } #endif } - if( ret < 0 ) - { - if( net_would_block( bind_ctx ) != 0 ) - return( MBEDTLS_ERR_SSL_WANT_READ ); + if ( ret < 0 ) { + if ( net_would_block( bind_ctx ) != 0 ) { + return ( MBEDTLS_ERR_SSL_WANT_READ ); + } - return( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + return ( MBEDTLS_ERR_NET_ACCEPT_FAILED ); } /* UDP: hijack the listening socket to communicate with the client, * then bind a new socket to accept new connections */ - if( type != SOCK_STREAM ) - { + if ( type != SOCK_STREAM ) { struct sockaddr_in local_addr; int one = 1; - if( connect( bind_ctx->fd, (struct sockaddr *) &client_addr, n ) != 0 ) - return( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + if ( connect( bind_ctx->fd, (struct sockaddr *) &client_addr, n ) != 0 ) { + return ( MBEDTLS_ERR_NET_ACCEPT_FAILED ); + } client_ctx->fd = bind_ctx->fd; bind_ctx->fd = -1; /* In case we exit early */ n = sizeof( struct sockaddr_in ); - if( getsockname( client_ctx->fd, - (struct sockaddr *) &local_addr, &n ) != 0 || - ( bind_ctx->fd = (int) socket( AF_INET, - SOCK_DGRAM, IPPROTO_UDP ) ) < 0 || - setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR, - (const char *) &one, sizeof( one ) ) != 0 ) - { - return( MBEDTLS_ERR_NET_SOCKET_FAILED ); + if ( getsockname( client_ctx->fd, + (struct sockaddr *) &local_addr, &n ) != 0 || + ( bind_ctx->fd = (int) socket( AF_INET, + SOCK_DGRAM, IPPROTO_UDP ) ) < 0 || + setsockopt( bind_ctx->fd, SOL_SOCKET, SO_REUSEADDR, + (const char *) &one, sizeof( one ) ) != 0 ) { + return ( MBEDTLS_ERR_NET_SOCKET_FAILED ); } - if( bind( bind_ctx->fd, (struct sockaddr *) &local_addr, n ) != 0 ) - { - return( MBEDTLS_ERR_NET_BIND_FAILED ); + if ( bind( bind_ctx->fd, (struct sockaddr *) &local_addr, n ) != 0 ) { + return ( MBEDTLS_ERR_NET_BIND_FAILED ); } } - if( client_ip != NULL ) - { - struct sockaddr_in *addr4 = (struct sockaddr_in *) &client_addr; - *ip_len = sizeof( addr4->sin_addr.s_addr ); + if ( client_ip != NULL ) { + struct sockaddr_in *addr4 = (struct sockaddr_in *) &client_addr; + *ip_len = sizeof( addr4->sin_addr.s_addr ); - if( buf_size < *ip_len ) - return( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL ); + if ( buf_size < *ip_len ) { + return ( MBEDTLS_ERR_NET_BUFFER_TOO_SMALL ); + } - memcpy( client_ip, &addr4->sin_addr.s_addr, *ip_len ); + memcpy( client_ip, &addr4->sin_addr.s_addr, *ip_len ); } - return( 0 ); + return ( 0 ); } /* @@ -356,9 +346,9 @@ int mbedtls_net_set_block( mbedtls_net_context *ctx ) #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) u_long n = 0; - return( ioctlsocket( ctx->fd, FIONBIO, &n ) ); + return ( ioctlsocket( ctx->fd, FIONBIO, &n ) ); #else - return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) & ~O_NONBLOCK ) ); + return ( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) & ~O_NONBLOCK ) ); #endif } @@ -367,9 +357,9 @@ int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) u_long n = 1; - return( ioctlsocket( ctx->fd, FIONBIO, &n ) ); + return ( ioctlsocket( ctx->fd, FIONBIO, &n ) ); #else - return( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) | O_NONBLOCK ) ); + return ( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) | O_NONBLOCK ) ); #endif } @@ -401,49 +391,54 @@ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) int ret; int fd = ((mbedtls_net_context *) ctx)->fd; int error = 0; - - if( fd < 0 ) - return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + + if ( fd < 0 ) { + return ( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + } ret = (int) read( fd, buf, len ); - if( ret < 0 ) - { - if( net_would_block( ctx ) != 0 ) - return( MBEDTLS_ERR_SSL_WANT_READ ); + if ( ret < 0 ) { + if ( net_would_block( ctx ) != 0 ) { + return ( MBEDTLS_ERR_SSL_WANT_READ ); + } - error = mbedtls_net_errno(fd); + error = mbedtls_net_errno(fd); #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) - if( WSAGetLastError() == WSAECONNRESET ) - return( MBEDTLS_ERR_NET_CONN_RESET ); + if ( WSAGetLastError() == WSAECONNRESET ) { + return ( MBEDTLS_ERR_NET_CONN_RESET ); + } #else - if( error == EPIPE || error == ECONNRESET ) - return( MBEDTLS_ERR_NET_CONN_RESET ); + if ( error == EPIPE || error == ECONNRESET ) { + return ( MBEDTLS_ERR_NET_CONN_RESET ); + } - if( error == EINTR ) - return( MBEDTLS_ERR_SSL_WANT_READ ); + if ( error == EINTR ) { + return ( MBEDTLS_ERR_SSL_WANT_READ ); + } #endif - return( MBEDTLS_ERR_NET_RECV_FAILED ); + return ( MBEDTLS_ERR_NET_RECV_FAILED ); } - return( ret ); + return ( ret ); } /* * Read at most 'len' characters, blocking for at most 'timeout' ms */ int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len, - uint32_t timeout ) + uint32_t timeout ) { int ret; struct timeval tv; fd_set read_fds; int fd = ((mbedtls_net_context *) ctx)->fd; - if( fd < 0 ) - return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + if ( fd < 0 ) { + return ( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + } FD_ZERO( &read_fds ); FD_SET( fd, &read_fds ); @@ -454,25 +449,27 @@ int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len, ret = select( fd + 1, &read_fds, NULL, NULL, timeout == 0 ? NULL : &tv ); /* Zero fds ready means we timed out */ - if( ret == 0 ) - return( MBEDTLS_ERR_SSL_TIMEOUT ); + if ( ret == 0 ) { + return ( MBEDTLS_ERR_SSL_TIMEOUT ); + } - if( ret < 0 ) - { + if ( ret < 0 ) { #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) - if( WSAGetLastError() == WSAEINTR ) - return( MBEDTLS_ERR_SSL_WANT_READ ); + if ( WSAGetLastError() == WSAEINTR ) { + return ( MBEDTLS_ERR_SSL_WANT_READ ); + } #else - if( errno == EINTR ) - return( MBEDTLS_ERR_SSL_WANT_READ ); + if ( errno == EINTR ) { + return ( MBEDTLS_ERR_SSL_WANT_READ ); + } #endif - return( MBEDTLS_ERR_NET_RECV_FAILED ); + return ( MBEDTLS_ERR_NET_RECV_FAILED ); } /* This call will not block */ - return( mbedtls_net_recv( ctx, buf, len ) ); + return ( mbedtls_net_recv( ctx, buf, len ) ); } /* @@ -483,35 +480,39 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) int ret; int fd = ((mbedtls_net_context *) ctx)->fd; - int error = 0; + int error = 0; - if( fd < 0 ) - return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + if ( fd < 0 ) { + return ( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + } ret = (int) write( fd, buf, len ); - if( ret < 0 ) - { - if( net_would_block( ctx ) != 0 ) - return( MBEDTLS_ERR_SSL_WANT_WRITE ); + if ( ret < 0 ) { + if ( net_would_block( ctx ) != 0 ) { + return ( MBEDTLS_ERR_SSL_WANT_WRITE ); + } - error = mbedtls_net_errno(fd); + error = mbedtls_net_errno(fd); #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ !defined(EFI32) - if( WSAGetLastError() == WSAECONNRESET ) - return( MBEDTLS_ERR_NET_CONN_RESET ); + if ( WSAGetLastError() == WSAECONNRESET ) { + return ( MBEDTLS_ERR_NET_CONN_RESET ); + } #else - if( error == EPIPE || error == ECONNRESET ) - return( MBEDTLS_ERR_NET_CONN_RESET ); + if ( error == EPIPE || error == ECONNRESET ) { + return ( MBEDTLS_ERR_NET_CONN_RESET ); + } - if( error == EINTR ) - return( MBEDTLS_ERR_SSL_WANT_WRITE ); + if ( error == EINTR ) { + return ( MBEDTLS_ERR_SSL_WANT_WRITE ); + } #endif - return( MBEDTLS_ERR_NET_SEND_FAILED ); + return ( MBEDTLS_ERR_NET_SEND_FAILED ); } - return( ret ); + return ( ret ); } /* @@ -519,8 +520,9 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) */ void mbedtls_net_free( mbedtls_net_context *ctx ) { - if( ctx->fd == -1 ) + if ( ctx->fd == -1 ) { return; + } shutdown( ctx->fd, 2 ); close( ctx->fd ); From 4167b68eef84667593aff7e6f90da50f2358ee14 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 2 Sep 2016 14:40:43 +1000 Subject: [PATCH 10/57] esp32: Move hardware crypto implementation/headers to hwcrypto directories --- components/esp32/{ => hwcrypto}/aes.c | 0 components/esp32/{ => hwcrypto}/bignum.c | 0 components/esp32/{ => hwcrypto}/esp_crypto.c | 0 components/esp32/{ => hwcrypto}/sha.c | 0 components/esp32/include/{ => hwcrypto}/aes.h | 0 components/esp32/include/{ => hwcrypto}/bignum.h | 0 components/esp32/include/{ => hwcrypto}/esp_crypto.h | 0 components/esp32/include/{ => hwcrypto}/sha.h | 0 8 files changed, 0 insertions(+), 0 deletions(-) rename components/esp32/{ => hwcrypto}/aes.c (100%) rename components/esp32/{ => hwcrypto}/bignum.c (100%) rename components/esp32/{ => hwcrypto}/esp_crypto.c (100%) rename components/esp32/{ => hwcrypto}/sha.c (100%) rename components/esp32/include/{ => hwcrypto}/aes.h (100%) rename components/esp32/include/{ => hwcrypto}/bignum.h (100%) rename components/esp32/include/{ => hwcrypto}/esp_crypto.h (100%) rename components/esp32/include/{ => hwcrypto}/sha.h (100%) diff --git a/components/esp32/aes.c b/components/esp32/hwcrypto/aes.c similarity index 100% rename from components/esp32/aes.c rename to components/esp32/hwcrypto/aes.c diff --git a/components/esp32/bignum.c b/components/esp32/hwcrypto/bignum.c similarity index 100% rename from components/esp32/bignum.c rename to components/esp32/hwcrypto/bignum.c diff --git a/components/esp32/esp_crypto.c b/components/esp32/hwcrypto/esp_crypto.c similarity index 100% rename from components/esp32/esp_crypto.c rename to components/esp32/hwcrypto/esp_crypto.c diff --git a/components/esp32/sha.c b/components/esp32/hwcrypto/sha.c similarity index 100% rename from components/esp32/sha.c rename to components/esp32/hwcrypto/sha.c diff --git a/components/esp32/include/aes.h b/components/esp32/include/hwcrypto/aes.h similarity index 100% rename from components/esp32/include/aes.h rename to components/esp32/include/hwcrypto/aes.h diff --git a/components/esp32/include/bignum.h b/components/esp32/include/hwcrypto/bignum.h similarity index 100% rename from components/esp32/include/bignum.h rename to components/esp32/include/hwcrypto/bignum.h diff --git a/components/esp32/include/esp_crypto.h b/components/esp32/include/hwcrypto/esp_crypto.h similarity index 100% rename from components/esp32/include/esp_crypto.h rename to components/esp32/include/hwcrypto/esp_crypto.h diff --git a/components/esp32/include/sha.h b/components/esp32/include/hwcrypto/sha.h similarity index 100% rename from components/esp32/include/sha.h rename to components/esp32/include/hwcrypto/sha.h From 0647d1e9225de9284edd449b400dc08c2743a5d9 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 2 Sep 2016 18:36:26 +1000 Subject: [PATCH 11/57] esp32 hwcrypto: Rework hardware crypto locking Should protect against concurrent use of hardware crypto primitives, with good performance. Not necessary to call esp_aes_acquire_hardware(), esp_sha_acquire_hardware(), etc when using these APIs. These are provided for external users calling the hardware crypto hardware directly, to coexist with this implementation. --- components/esp32/hwcrypto/aes.c | 209 +++++++++--------- components/esp32/hwcrypto/bignum.c | 43 ++-- components/esp32/hwcrypto/esp_crypto.c | 66 ------ components/esp32/hwcrypto/sha.c | 109 +++------ components/esp32/include/hwcrypto/aes.h | 29 ++- components/esp32/include/hwcrypto/bignum.h | 29 ++- .../esp32/include/hwcrypto/esp_crypto.h | 56 ----- components/esp32/include/hwcrypto/sha.h | 34 ++- 8 files changed, 235 insertions(+), 340 deletions(-) delete mode 100644 components/esp32/hwcrypto/esp_crypto.c delete mode 100644 components/esp32/include/hwcrypto/esp_crypto.h diff --git a/components/esp32/hwcrypto/aes.c b/components/esp32/hwcrypto/aes.c index e22c08a37..e2ee67bec 100644 --- a/components/esp32/hwcrypto/aes.c +++ b/components/esp32/hwcrypto/aes.c @@ -1,8 +1,10 @@ /* - * FIPS-197 compliant AES implementation + * ESP32 hardware accelerated AES implementation + * based on mbedTLS FIPS-197 compliant version. * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -25,22 +27,30 @@ * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf */ #include -#include "aes.h" -#include "esp_crypto.h" +#include "hwcrypto/aes.h" +#include "rom/aes.h" +#include -/* Implementation that should never be optimized out by the compiler */ -//static void bzero( void *v, size_t n ) { -// volatile unsigned char *p = v; while( n-- ) *p++ = 0; -//} +static _lock_t aes_lock; + +void esp_aes_acquire_hardware( void ) +{ + /* newlib locks lazy initialize on ESP-IDF */ + _lock_acquire(&aes_lock); + ets_aes_enable(); +} + +void esp_aes_release_hardware( void ) +{ + uint8_t zero[256/8] = { 0 }; + ets_aes_setkey_enc(zero, AES256); + ets_aes_disable(); + _lock_release(&aes_lock); +} void esp_aes_init( AES_CTX *ctx ) { - memset( ctx, 0, sizeof( AES_CTX ) ); - - AES_LOCK(); - AES_TAKE(); - ets_aes_enable(); - AES_UNLOCK(); + bzero( ctx, sizeof( AES_CTX ) ); } void esp_aes_free( AES_CTX *ctx ) @@ -50,117 +60,94 @@ void esp_aes_free( AES_CTX *ctx ) } bzero( ctx, sizeof( AES_CTX ) ); +} - AES_LOCK(); - AES_GIVE(); - - if (false == AES_IS_USED()) { - ets_aes_disable(); +/* Translate number of bits to an AES_BITS enum */ +static int keybits_to_aesbits(unsigned int keybits) +{ + switch (keybits) { + case 128: + return AES128; + case 192: + return AES192; + break; + case 256: + return AES256; + default: + return ( ERR_AES_INVALID_KEY_LENGTH ); } - - AES_UNLOCK(); } /* * AES key schedule (encryption) + * */ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { - enum AES_BITS keybit; - uint16_t keybyte = keybits / 8; - - switch (keybits) { - case 128: - keybit = AES128; - break; - case 192: - keybit = AES192; - break; - case 256: - keybit = AES256; - break; - default: - return ( ERR_AES_INVALID_KEY_LENGTH ); + uint16_t keybytes = keybits / 8; + int aesbits = keybits_to_aesbits(keybits); + if (aesbits < 0) { + return aesbits; } - - if (ctx->enc.keyflag == false) { - ctx->enc.keyflag = true; - ctx->enc.keybits = keybits; - memset(ctx->enc.key, 0, sizeof(ctx->enc.key)); - memcpy(ctx->enc.key, key, keybyte); - } else { - ets_aes_setkey_enc(key, keybit); - } - + ctx->enc.aesbits = aesbits; + bzero(ctx->enc.key, sizeof(ctx->enc.key)); + memcpy(ctx->enc.key, key, keybytes); return 0; } /* * AES key schedule (decryption) + * */ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ) { - enum AES_BITS keybit; - uint16_t keybyte = keybits / 8; - - switch (keybits) { - case 128: - keybit = AES128; - break; - case 192: - keybit = AES192; - break; - case 256: - keybit = AES256; - break; - default: - return ( ERR_AES_INVALID_KEY_LENGTH ); + uint16_t keybytes = keybits / 8; + int aesbits = keybits_to_aesbits(keybits); + if (aesbits < 0) { + return aesbits; } - - if (ctx->dec.keyflag == false) { - ctx->dec.keyflag = true; - ctx->dec.keybits = keybits; - memset(ctx->dec.key, 0, sizeof(ctx->dec.key)); - memcpy(ctx->dec.key, key, keybyte); - } else { - ets_aes_setkey_dec(key, keybit); - } - + ctx->dec.aesbits = aesbits; + bzero(ctx->dec.key, sizeof(ctx->dec.key)); + memcpy(ctx->dec.key, key, keybytes); return 0; } -static void esp_aes_process_enable(AES_CTX *ctx, int mode) +/* + * Inner AES-ECB function. Call only when protected by esp_aes_acquire_hardware(). + * + * Optimisation to prevent overhead of locking each time when + * encrypting many blocks in sequence. + */ +static int esp_aes_crypt_ecb_inner( AES_CTX *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) { if ( mode == AES_ENCRYPT ) { - esp_aes_setkey_enc(ctx, ctx->enc.key, ctx->enc.keybits); + ets_aes_setkey_enc(ctx->enc.key, ctx->enc.aesbits); + ets_aes_crypt(input, output); } else { - esp_aes_setkey_dec(ctx, ctx->dec.key, ctx->dec.keybits); + ets_aes_setkey_dec(ctx->enc.key, ctx->enc.aesbits); + /* TODO: previous commit esp_aes_decrypt function calls this but this is not correct! */ + ets_aes_crypt(input, output); } - - return; -} - -static void esp_aes_process_disable(AES_CTX *ctx, int mode) -{ - + return 0; } /* * AES-ECB block encryption */ - void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ) { - ets_aes_crypt(input, output); - - return ; + esp_aes_acquire_hardware(); + esp_aes_crypt_ecb_inner(ctx, AES_ENCRYPT, input, output); + esp_aes_release_hardware(); } - /* * AES-ECB block decryption */ @@ -169,9 +156,9 @@ void esp_aes_decrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ) { - ets_aes_crypt(input, output); - - return ; + esp_aes_acquire_hardware(); + esp_aes_crypt_ecb_inner(ctx, AES_DECRYPT, input, output); + esp_aes_release_hardware(); } @@ -183,20 +170,9 @@ int esp_aes_crypt_ecb( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ) { - AES_LOCK(); - - esp_aes_process_enable(ctx, mode); - - if ( mode == AES_ENCRYPT ) { - esp_aes_encrypt( ctx, input, output ); - } else { - esp_aes_decrypt( ctx, input, output ); - } - - esp_aes_process_disable(ctx, mode); - - AES_UNLOCK(); - + esp_aes_acquire_hardware(); + esp_aes_crypt_ecb_inner(ctx, mode, input, output); + esp_aes_release_hardware(); return 0; } @@ -218,10 +194,12 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, return ( ERR_AES_INVALID_INPUT_LENGTH ); } + esp_aes_acquire_hardware(); + if ( mode == AES_DECRYPT ) { while ( length > 0 ) { memcpy( temp, input, 16 ); - esp_aes_crypt_ecb( ctx, mode, input, output ); + esp_aes_crypt_ecb_inner( ctx, mode, input, output ); for ( i = 0; i < 16; i++ ) { output[i] = (unsigned char)( output[i] ^ iv[i] ); @@ -239,7 +217,7 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, output[i] = (unsigned char)( input[i] ^ iv[i] ); } - esp_aes_crypt_ecb( ctx, mode, output, output ); + esp_aes_crypt_ecb_inner( ctx, mode, output, output ); memcpy( iv, output, 16 ); input += 16; @@ -248,6 +226,8 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, } } + esp_aes_release_hardware(); + return 0; } @@ -265,10 +245,12 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, int c; size_t n = *iv_off; + esp_aes_acquire_hardware(); + if ( mode == AES_DECRYPT ) { while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, iv, iv ); } c = *input++; @@ -280,7 +262,7 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, } else { while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, iv, iv ); } iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); @@ -291,6 +273,8 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, *iv_off = n; + esp_aes_release_hardware(); + return 0; } @@ -307,9 +291,11 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, unsigned char c; unsigned char ov[17]; + esp_aes_acquire_hardware(); + while ( length-- ) { memcpy( ov, iv, 16 ); - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, iv, iv ); if ( mode == AES_DECRYPT ) { ov[16] = *input; @@ -324,6 +310,8 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, memcpy( iv, ov + 1, 16 ); } + esp_aes_release_hardware(); + return 0; } @@ -341,9 +329,11 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, int c, i; size_t n = *nc_off; + esp_aes_acquire_hardware(); + while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb( ctx, AES_ENCRYPT, nonce_counter, stream_block ); + esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, nonce_counter, stream_block ); for ( i = 16; i > 0; i-- ) if ( ++nonce_counter[i - 1] != 0 ) { @@ -358,6 +348,7 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, *nc_off = n; + esp_aes_release_hardware(); + return 0; } - diff --git a/components/esp32/hwcrypto/bignum.c b/components/esp32/hwcrypto/bignum.c index dbfa418ec..93b31e6f6 100644 --- a/components/esp32/hwcrypto/bignum.c +++ b/components/esp32/hwcrypto/bignum.c @@ -1,7 +1,9 @@ /* - * Multi-precision integer library + * ESP32 hardware accelerated multi-precision integer functions + * based on mbedTLS implementation * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -36,8 +38,10 @@ #include #include -#include "bignum.h" -#include "esp_crypto.h" +#include +#include "hwcrypto/bignum.h" +#include "rom/ets_sys.h" +#include "rom/bigint.h" /* Implementation that should never be optimized out by the compiler */ //static void bzero( void *v, size_t n ) { @@ -57,6 +61,22 @@ #define BITS_TO_LIMBS(i) ( (i) / biL + ( (i) % biL != 0 ) ) #define CHARS_TO_LIMBS(i) ( (i) / ciL + ( (i) % ciL != 0 ) ) +static _lock_t mpi_lock; + +void esp_mpi_acquire_hardware( void ) +{ + /* newlib locks lazy initialize on ESP-IDF */ + _lock_acquire(&mpi_lock); + ets_bigint_enable(); +} + +void esp_mpi_release_hardware( void ) +{ + ets_bigint_disable(); + _lock_release(&mpi_lock); +} + + /* * Initialize one MPI */ @@ -68,10 +88,6 @@ void esp_mpi_init( mpi *X ) X->s = 1; X->n = 0; X->p = NULL; - BIGNUM_LOCK(); - BIGNUM_TAKE(); - ets_bigint_enable(); - BIGNUM_UNLOCK(); } /* @@ -91,11 +107,6 @@ void esp_mpi_free( mpi *X ) X->s = 1; X->n = 0; X->p = NULL; - BIGNUM_LOCK(); - BIGNUM_GIVE(); - if (false == BIGNUM_IS_USED()) - ets_bigint_disable(); - BIGNUM_UNLOCK(); } /* @@ -1107,7 +1118,7 @@ int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) goto cleanup; } - BIGNUM_LOCK(); + esp_mpi_acquire_hardware(); if (ets_bigint_mult_prepare((uint32_t *)s1, (uint32_t *)s2, bites)){ ets_bigint_wait_finish(); if (ets_bigint_mult_getz((uint32_t *)dest, bites) == true) { @@ -1119,7 +1130,7 @@ int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) } else{ esp_mpi_printf("Baseline multiplication failed\n"); } - BIGNUM_UNLOCK(); + esp_mpi_release_hardware(); X->s = A->s * B->s; @@ -1487,7 +1498,7 @@ static void esp_mpi_montmul( mpi *A, const mpi *B, const mpi *N, esp_mpi_uint mm n = N->n; m = ( B->n < n ) ? B->n : n; - BIGNUM_LOCK(); + esp_mpi_acquire_hardware(); if (ets_bigint_montgomery_mult_prepare(N->p, B->p, d, m, n, false)) { ets_bigint_wait_finish(); @@ -1495,7 +1506,7 @@ static void esp_mpi_montmul( mpi *A, const mpi *B, const mpi *N, esp_mpi_uint mm } else{ esp_mpi_printf("Montgomery multiplication failed\n"); } - BIGNUM_UNLOCK(); + esp_mpi_release_hardware(); } diff --git a/components/esp32/hwcrypto/esp_crypto.c b/components/esp32/hwcrypto/esp_crypto.c deleted file mode 100644 index 0a5cd2f47..000000000 --- a/components/esp32/hwcrypto/esp_crypto.c +++ /dev/null @@ -1,66 +0,0 @@ -#include "esp_crypto.h" -#include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" - -static SemaphoreHandle_t esp_crypto_mutex[MUTEX_MAX_NUM]; -static int esp_crypto_sig[MUTEX_MAX_NUM]; - -#if 0 -#define ESP_DEBUG ets_printf -#else -#define ESP_DEBUG(...) -#endif - -int esp_crypto_init(void) -{ - int i; - - for (i = 0; i < MUTEX_MAX_NUM; i++) { - esp_crypto_mutex[i] = xSemaphoreCreateMutex(); - ESP_DEBUG("init num %d mutex %p\n", i, esp_crypto_mutex[i]); - if (!esp_crypto_mutex[i]) { - goto failed1; - } - esp_crypto_sig[i] = 0; - } - - return 0; - -failed1: - ESP_DEBUG("esp_crypto_init failed\n"); - for (i--; i >= 0; i--) { - vQueueDelete(esp_crypto_mutex[i]); - } - - return -1; -} - -void esp_crypto_lock(unsigned int num) -{ - ESP_DEBUG("1num %d, mutex %p\n", num, esp_crypto_mutex[num]); - xSemaphoreTake(esp_crypto_mutex[num], portMAX_DELAY); -} - -void esp_crypto_unlock(unsigned int num) -{ - ESP_DEBUG("2num %d, mutex %p\n", num, esp_crypto_mutex[num]); - xSemaphoreGive(esp_crypto_mutex[num]); -} - -void esp_crypto_take(unsigned int num) -{ - esp_crypto_sig[num]++; -} - -void esp_crypto_give(unsigned int num) -{ - if (esp_crypto_sig[num]) { - esp_crypto_sig[num]--; - } -} - -bool esp_crypto_is_used(unsigned int num) -{ - return (esp_crypto_sig[num] != 0) ? true : false; -} - diff --git a/components/esp32/hwcrypto/sha.c b/components/esp32/hwcrypto/sha.c index cc850f084..e54ef45a8 100644 --- a/components/esp32/hwcrypto/sha.c +++ b/components/esp32/hwcrypto/sha.c @@ -1,7 +1,9 @@ /* - * FIPS-180-1 compliant SHA-1 implementation + * ESP32 hardware accelerated SHA1/256/512 implementation + * based on mbedTLS FIPS-197 compliant version. * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -24,22 +26,33 @@ */ #include -#include "sha.h" -#include "esp_crypto.h" +#include +#include "hwcrypto/sha.h" +#include "rom/ets_sys.h" -/* Implementation that should never be optimized out by the compiler */ -//static void bzero( void *v, size_t n ) { -// volatile unsigned char *p = v; while( n-- ) *p++ = 0; -//} + +static _lock_t sha_lock; + +void esp_sha_acquire_hardware( void ) +{ + /* newlib locks lazy initialize on ESP-IDF */ + _lock_acquire(&sha_lock); + ets_sha_enable(); +} + +void esp_sha_release_hardware( void ) +{ + /* Want to empty internal SHA buffers where possible, + need to check if this is sufficient for this. */ + SHA_CTX zero = { 0 }; + ets_sha_init(&zero); + ets_sha_disable(); + _lock_release(&sha_lock); +} void esp_sha1_init( SHA1_CTX *ctx ) { - memset( ctx, 0, sizeof( SHA1_CTX ) ); - - SHA_LOCK(); - SHA_TAKE(); - ets_sha_enable(); - SHA_UNLOCK(); + bzero( ctx, sizeof( SHA1_CTX ) ); } void esp_sha1_free( SHA1_CTX *ctx ) @@ -49,15 +62,6 @@ void esp_sha1_free( SHA1_CTX *ctx ) } bzero( ctx, sizeof( SHA1_CTX ) ); - - SHA_LOCK(); - SHA_GIVE(); - - if (false == SHA_IS_USED()) { - ets_sha_disable(); - } - - SHA_UNLOCK(); } void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) @@ -65,19 +69,12 @@ void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) *dst = *src; } -void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]) -{ - -} - /* * SHA-1 context setup */ void esp_sha1_start( SHA1_CTX *ctx ) { - SHA_LOCK(); - ets_sha_init(&ctx->context); - + esp_sha_acquire_hardware(); ctx->context_type = SHA1; } @@ -95,7 +92,7 @@ void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA_UNLOCK(); + esp_sha_release_hardware(); } /* @@ -112,21 +109,9 @@ void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char out esp_sha1_free( &ctx ); } -///// -/* Implementation that should never be optimized out by the compiler */ void esp_sha256_init( SHA256_CTX *ctx ) { - memset( ctx, 0, sizeof( SHA256_CTX ) ); - - SHA_LOCK(); - SHA_TAKE(); - ets_sha_enable(); - SHA_UNLOCK(); -} - -void esp_sha256_process(SHA256_CTX *ctx, const unsigned char data[64]) -{ - + bzero( ctx, sizeof( SHA256_CTX ) ); } void esp_sha256_free( SHA256_CTX *ctx ) @@ -136,15 +121,6 @@ void esp_sha256_free( SHA256_CTX *ctx ) } bzero( ctx, sizeof( SHA256_CTX ) ); - - SHA_LOCK(); - SHA_GIVE(); - - if (false == SHA_IS_USED()) { - ets_sha_disable(); - } - - SHA_UNLOCK(); } void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) @@ -157,7 +133,7 @@ void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) */ void esp_sha256_start( SHA256_CTX *ctx, int is224 ) { - SHA_LOCK(); + esp_sha_acquire_hardware(); ets_sha_init(&ctx->context); if ( is224 == 0 ) { @@ -183,7 +159,7 @@ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA_UNLOCK(); + esp_sha_release_hardware(); } /* @@ -205,16 +181,6 @@ void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char o void esp_sha512_init( SHA512_CTX *ctx ) { memset( ctx, 0, sizeof( SHA512_CTX ) ); - - SHA_LOCK(); - SHA_TAKE(); - ets_sha_enable(); - SHA_UNLOCK(); -} - -void esp_sha512_process( SHA512_CTX *ctx, const unsigned char data[128] ) -{ - } void esp_sha512_free( SHA512_CTX *ctx ) @@ -224,15 +190,6 @@ void esp_sha512_free( SHA512_CTX *ctx ) } bzero( ctx, sizeof( SHA512_CTX ) ); - - SHA_LOCK(); - SHA_GIVE(); - - if (false == SHA_IS_USED()) { - ets_sha_disable(); - } - - SHA_UNLOCK(); } void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) @@ -245,7 +202,7 @@ void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) */ void esp_sha512_start( SHA512_CTX *ctx, int is384 ) { - SHA_LOCK(); + esp_sha_acquire_hardware(); ets_sha_init(&ctx->context); if ( is384 == 0 ) { @@ -271,7 +228,7 @@ void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen void esp_sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); - SHA_UNLOCK(); + esp_sha_release_hardware(); } /* diff --git a/components/esp32/include/hwcrypto/aes.h b/components/esp32/include/hwcrypto/aes.h index 76ea47c55..9c149a935 100644 --- a/components/esp32/include/hwcrypto/aes.h +++ b/components/esp32/include/hwcrypto/aes.h @@ -1,9 +1,11 @@ /** * \file esp_aes.h * - * \brief AES block cipher + * \brief AES block cipher, ESP32 hardware accelerated version + * Based on mbedTLS version. * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -25,7 +27,6 @@ #define ESP_AES_H #include "esp_types.h" -#include "rom/ets_sys.h" #include "rom/aes.h" #ifdef __cplusplus @@ -40,8 +41,7 @@ extern "C" { #define ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ typedef struct { - bool keyflag; - uint16_t keybits; + enum AES_BITS aesbits; uint8_t key[32]; } key_context, KEY_CTX; @@ -60,6 +60,27 @@ typedef struct { KEY_CTX dec; } aes_context, AES_CTX; +/** + * \brief Lock access to AES hardware unit + * + * AES hardware unit can only be used by one + * consumer at a time. + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_acquire_hardware( void ); + +/** + * \brief Unlock access to AES hardware unit + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_release_hardware( void ); + /** * \brief Initialize AES context * diff --git a/components/esp32/include/hwcrypto/bignum.h b/components/esp32/include/hwcrypto/bignum.h index e077fe2ed..dbcef43de 100644 --- a/components/esp32/include/hwcrypto/bignum.h +++ b/components/esp32/include/hwcrypto/bignum.h @@ -1,9 +1,11 @@ /** * \file bignum_alt.h * - * \brief Multi-precision integer library + * \brief Multi-precision integer library, ESP32 hardware accelerated version + * Based on mbedTLS version. * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -19,13 +21,11 @@ * limitations under the License. * */ - + #ifndef _ESP_BIGNUM_H #define _ESP_BIGNUM_H #include "esp_types.h" -#include "rom/ets_sys.h" -#include "rom/bigint.h" #define MPI_DEBUG_ALT @@ -147,6 +147,27 @@ typedef struct esp_mpi_uint *p; /*!< pointer to limbs */ }mpi, MPI_CTX; +/** + * \brief Lock access to MPI hardware unit + * + * MPI hardware unit can only be used by one + * consumer at a time. + * + * esp_mpi_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_bigint_xxx functions directly. + */ +void esp_mpi_acquire_hardware( void ); + +/** + * \brief Unlock access to MPI hardware unit + * + * esp_mpi_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_bigint_xxx functions directly. + */ +void esp_mpi_release_hardware( void ); + /** * \brief Initialize one MPI (make internal references valid) * This just makes it ready to be set or freed, diff --git a/components/esp32/include/hwcrypto/esp_crypto.h b/components/esp32/include/hwcrypto/esp_crypto.h deleted file mode 100644 index bac07ceac..000000000 --- a/components/esp32/include/hwcrypto/esp_crypto.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef _MULTI_CRYPTO_H_ -#define _MULTI_CRYPTO_H_ - -#include "esp_types.h" -#include "rom/ets_sys.h" - -#ifdef __cplusplus -extern "C" { -#endif - -enum { - AES_MUTEX = 0, - BIGNUM_MUTEX, - SHA_MUTEX, - - MUTEX_MAX_NUM, -}; - -int esp_crypto_init(void); - -void esp_crypto_lock(unsigned int num); -void esp_crypto_unlock(unsigned int num); - -void esp_crypto_take(unsigned int num); -void esp_crypto_give(unsigned int num); -bool esp_crypto_is_used(unsigned int num); - -#define MUTEX_LOCK(num) esp_crypto_lock(num) -#define MUTEX_UNLOCK(num) esp_crypto_unlock(num) - -#define SIG_TAKE(num) esp_crypto_take(num) -#define SIG_GIVE(num) esp_crypto_give(num) -#define SIG_IS_USED(num) esp_crypto_is_used(num) - -#define AES_LOCK() MUTEX_LOCK(AES_MUTEX) -#define AES_UNLOCK() MUTEX_UNLOCK(AES_MUTEX) -#define BIGNUM_LOCK() MUTEX_LOCK(BIGNUM_MUTEX) -#define BIGNUM_UNLOCK() MUTEX_UNLOCK(BIGNUM_MUTEX) -#define SHA_LOCK() MUTEX_LOCK(SHA_MUTEX) -#define SHA_UNLOCK() MUTEX_UNLOCK(SHA_MUTEX) - -#define AES_TAKE() SIG_TAKE(AES_MUTEX) -#define AES_GIVE() SIG_GIVE(AES_MUTEX) -#define AES_IS_USED() SIG_IS_USED(AES_MUTEX) -#define BIGNUM_TAKE() SIG_TAKE(BIGNUM_MUTEX) -#define BIGNUM_GIVE() SIG_GIVE(BIGNUM_MUTEX) -#define BIGNUM_IS_USED() SIG_IS_USED(BIGNUM_MUTEX) -#define SHA_TAKE() SIG_TAKE(SHA_MUTEX) -#define SHA_GIVE() SIG_GIVE(SHA_MUTEX) -#define SHA_IS_USED() SIG_IS_USED(SHA_MUTEX) - -#ifdef __cplusplus -} -#endif - -#endif /* esp_crypto.h */ diff --git a/components/esp32/include/hwcrypto/sha.h b/components/esp32/include/hwcrypto/sha.h index 2ee667cf7..a5de3d402 100644 --- a/components/esp32/include/hwcrypto/sha.h +++ b/components/esp32/include/hwcrypto/sha.h @@ -15,10 +15,10 @@ #ifndef _ESP_SHA_H_ #define _ESP_SHA_H_ -#include "esp_types.h" -#include "rom/ets_sys.h" #include "rom/sha.h" +#include "esp_types.h" + #ifdef __cplusplus extern "C" { #endif @@ -28,11 +28,32 @@ extern "C" { */ typedef struct { SHA_CTX context; - int context_type; + enum SHA_TYPE context_type; /* defined in rom/sha.h */ } sha_context; typedef sha_context SHA1_CTX; +/** + * \brief Lock access to SHA hardware unit + * + * SHA hardware unit can only be used by one + * consumer at a time. + * + * esp_sha_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_sha_xxx functions directly. + */ +void esp_sha_acquire_hardware( void ); + +/** + * \brief Unlock access to SHA hardware unit + * + * esp_sha_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_sha_xxx functions directly. + */ +void esp_sha_release_hardware( void ); + /** * \brief Initialize SHA-1 context * @@ -55,8 +76,6 @@ void esp_sha1_free( SHA1_CTX *ctx ); */ void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ); -void esp_sha1_process(SHA1_CTX *ctx, const unsigned char data[64]); - /** * \brief SHA-1 context setup * @@ -92,7 +111,7 @@ void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char out /// #define SHA256 SHA2_256 -#define SHA224 4 +#define SHA224 4 /* TODO: check this */ /** * \brief SHA-256 context structure @@ -113,7 +132,6 @@ void esp_sha256_init( SHA256_CTX *ctx ); * \param ctx SHA-256 context to be cleared */ void esp_sha256_free( SHA256_CTX *ctx ); -void esp_sha256_process(SHA256_CTX *ctx, const unsigned char data[64]); /** * \brief Clone (the state of) a SHA-256 context @@ -173,8 +191,6 @@ typedef sha_context SHA512_CTX; */ void esp_sha512_init( SHA512_CTX *ctx ); -void esp_sha512_process( SHA512_CTX *ctx, const unsigned char data[128] ); - /** * \brief Clear SHA-512 context * From 2bee84062af96890b9680bfb0420c8ced542930c Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 2 Sep 2016 18:39:57 +1000 Subject: [PATCH 12/57] esp32: Add comment to ROM crypto functions recommending they not be used directly --- components/esp32/include/rom/aes.h | 7 +++++++ components/esp32/include/rom/bigint.h | 7 +++++++ components/esp32/include/rom/sha.h | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/components/esp32/include/rom/aes.h b/components/esp32/include/rom/aes.h index 9fd0e5bae..2f058f1c2 100644 --- a/components/esp32/include/rom/aes.h +++ b/components/esp32/include/rom/aes.h @@ -1,3 +1,10 @@ +/* + ROM functions for hardware AES support. + + It is not recommended to use these functions directly, + use the wrapper functions in hwcrypto/aes.h instead. + + */ // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/components/esp32/include/rom/bigint.h b/components/esp32/include/rom/bigint.h index 461469cac..624336695 100644 --- a/components/esp32/include/rom/bigint.h +++ b/components/esp32/include/rom/bigint.h @@ -1,3 +1,10 @@ +/* + ROM functions for hardware bigint support. + + It is not recommended to use these functions directly, + use the wrapper functions in hwcrypto/mpi.h instead. + + */ // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/components/esp32/include/rom/sha.h b/components/esp32/include/rom/sha.h index a5536bd3b..b35faa9a0 100644 --- a/components/esp32/include/rom/sha.h +++ b/components/esp32/include/rom/sha.h @@ -1,3 +1,10 @@ +/* + ROM functions for hardware SHA support. + + It is not recommended to use these functions directly, + use the wrapper functions in hwcrypto/sha.h instead. + + */ // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); From 2580c07ae671b2432cbaacd3912eb24d70da3b3e Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Mon, 5 Sep 2016 10:36:25 +1000 Subject: [PATCH 13/57] esp32 hwcrypto: Make SHA-224 an obvious no-op for now This is not the long term solution... --- components/esp32/hwcrypto/sha.c | 14 ++++++++++---- components/esp32/include/hwcrypto/sha.h | 4 ---- components/esp32/include/rom/sha.h | 3 ++- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/components/esp32/hwcrypto/sha.c b/components/esp32/hwcrypto/sha.c index e54ef45a8..584383eb1 100644 --- a/components/esp32/hwcrypto/sha.c +++ b/components/esp32/hwcrypto/sha.c @@ -138,10 +138,10 @@ void esp_sha256_start( SHA256_CTX *ctx, int is224 ) if ( is224 == 0 ) { /* SHA-256 */ - ctx->context_type = SHA256; + ctx->context_type = SHA2_256; } else { - /* SHA-224 */ - ctx->context_type = SHA224; + /* SHA-224 is not supported! */ + ctx->context_type = SHA_INVALID; } } @@ -158,7 +158,13 @@ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen */ void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) { - ets_sha_finish(&ctx->context, ctx->context_type, output); + if ( ctx->context_type == SHA2_256 ) { + ets_sha_finish(&ctx->context, ctx->context_type, output); + } else { + /* No hardware SHA-224 support, but mbedTLS API doesn't allow failure. + For now, zero the output to make it clear it's not valid. */ + bzero( output, 28 ); + } esp_sha_release_hardware(); } diff --git a/components/esp32/include/hwcrypto/sha.h b/components/esp32/include/hwcrypto/sha.h index a5de3d402..dbefcef06 100644 --- a/components/esp32/include/hwcrypto/sha.h +++ b/components/esp32/include/hwcrypto/sha.h @@ -109,10 +109,6 @@ void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ); */ void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ); -/// -#define SHA256 SHA2_256 -#define SHA224 4 /* TODO: check this */ - /** * \brief SHA-256 context structure */ diff --git a/components/esp32/include/rom/sha.h b/components/esp32/include/rom/sha.h index b35faa9a0..8082a394c 100644 --- a/components/esp32/include/rom/sha.h +++ b/components/esp32/include/rom/sha.h @@ -37,7 +37,8 @@ enum SHA_TYPE { SHA1 = 0, SHA2_256, SHA2_384, - SHA2_512 + SHA2_512, + SHA_INVALID = -1, }; void ets_sha_init(SHA_CTX *ctx); From 0a970e3a258327db02410c41cb79126fb87ca222 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Tue, 6 Sep 2016 10:38:12 +1000 Subject: [PATCH 14/57] hwcrypto: Match API completely to mbedTLS naming conventions --- components/esp32/hwcrypto/aes.c | 61 ++++++++------- components/esp32/hwcrypto/bignum.c | 5 +- components/esp32/hwcrypto/sha.c | 68 +++++++++-------- components/esp32/include/hwcrypto/aes.h | 36 +++++---- components/esp32/include/hwcrypto/sha.h | 99 +++++++++++++------------ 5 files changed, 135 insertions(+), 134 deletions(-) diff --git a/components/esp32/hwcrypto/aes.c b/components/esp32/hwcrypto/aes.c index e2ee67bec..16ed704ba 100644 --- a/components/esp32/hwcrypto/aes.c +++ b/components/esp32/hwcrypto/aes.c @@ -1,7 +1,6 @@ - -/* - * ESP32 hardware accelerated AES implementation - * based on mbedTLS FIPS-197 compliant version. +/** + * \brief AES block cipher, ESP32 hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd @@ -48,18 +47,18 @@ void esp_aes_release_hardware( void ) _lock_release(&aes_lock); } -void esp_aes_init( AES_CTX *ctx ) +void esp_aes_init( esp_aes_context *ctx ) { - bzero( ctx, sizeof( AES_CTX ) ); + bzero( ctx, sizeof( esp_aes_context ) ); } -void esp_aes_free( AES_CTX *ctx ) +void esp_aes_free( esp_aes_context *ctx ) { if ( ctx == NULL ) { return; } - bzero( ctx, sizeof( AES_CTX ) ); + bzero( ctx, sizeof( esp_aes_context ) ); } /* Translate number of bits to an AES_BITS enum */ @@ -74,7 +73,7 @@ static int keybits_to_aesbits(unsigned int keybits) case 256: return AES256; default: - return ( ERR_AES_INVALID_KEY_LENGTH ); + return ( ERR_ESP_AES_INVALID_KEY_LENGTH ); } } @@ -82,7 +81,7 @@ static int keybits_to_aesbits(unsigned int keybits) * AES key schedule (encryption) * */ -int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, +int esp_aes_setkey_enc( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { uint16_t keybytes = keybits / 8; @@ -100,7 +99,7 @@ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, * AES key schedule (decryption) * */ -int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, +int esp_aes_setkey_dec( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { uint16_t keybytes = keybits / 8; @@ -120,12 +119,12 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, * Optimisation to prevent overhead of locking each time when * encrypting many blocks in sequence. */ -static int esp_aes_crypt_ecb_inner( AES_CTX *ctx, +static int esp_aes_crypt_ecb_inner( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ) { - if ( mode == AES_ENCRYPT ) { + if ( mode == ESP_AES_ENCRYPT ) { ets_aes_setkey_enc(ctx->enc.key, ctx->enc.aesbits); ets_aes_crypt(input, output); } else { @@ -139,12 +138,12 @@ static int esp_aes_crypt_ecb_inner( AES_CTX *ctx, /* * AES-ECB block encryption */ -void esp_aes_encrypt( AES_CTX *ctx, +void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { esp_aes_acquire_hardware(); - esp_aes_crypt_ecb_inner(ctx, AES_ENCRYPT, input, output); + esp_aes_crypt_ecb_inner(ctx, ESP_AES_ENCRYPT, input, output); esp_aes_release_hardware(); } @@ -152,12 +151,12 @@ void esp_aes_encrypt( AES_CTX *ctx, * AES-ECB block decryption */ -void esp_aes_decrypt( AES_CTX *ctx, +void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) { esp_aes_acquire_hardware(); - esp_aes_crypt_ecb_inner(ctx, AES_DECRYPT, input, output); + esp_aes_crypt_ecb_inner(ctx, ESP_AES_DECRYPT, input, output); esp_aes_release_hardware(); } @@ -165,7 +164,7 @@ void esp_aes_decrypt( AES_CTX *ctx, /* * AES-ECB block encryption/decryption */ -int esp_aes_crypt_ecb( AES_CTX *ctx, +int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ) @@ -180,7 +179,7 @@ int esp_aes_crypt_ecb( AES_CTX *ctx, /* * AES-CBC buffer encryption/decryption */ -int esp_aes_crypt_cbc( AES_CTX *ctx, +int esp_aes_crypt_cbc( esp_aes_context *ctx, int mode, size_t length, unsigned char iv[16], @@ -191,12 +190,12 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, unsigned char temp[16]; if ( length % 16 ) { - return ( ERR_AES_INVALID_INPUT_LENGTH ); + return ( ERR_ESP_AES_INVALID_INPUT_LENGTH ); } esp_aes_acquire_hardware(); - if ( mode == AES_DECRYPT ) { + if ( mode == ESP_AES_DECRYPT ) { while ( length > 0 ) { memcpy( temp, input, 16 ); esp_aes_crypt_ecb_inner( ctx, mode, input, output ); @@ -234,7 +233,7 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, /* * AES-CFB128 buffer encryption/decryption */ -int esp_aes_crypt_cfb128( AES_CTX *ctx, +int esp_aes_crypt_cfb128( esp_aes_context *ctx, int mode, size_t length, size_t *iv_off, @@ -247,10 +246,10 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, esp_aes_acquire_hardware(); - if ( mode == AES_DECRYPT ) { + if ( mode == ESP_AES_DECRYPT ) { while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, iv, iv ); } c = *input++; @@ -262,7 +261,7 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, } else { while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, iv, iv ); } iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); @@ -281,7 +280,7 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, /* * AES-CFB8 buffer encryption/decryption */ -int esp_aes_crypt_cfb8( AES_CTX *ctx, +int esp_aes_crypt_cfb8( esp_aes_context *ctx, int mode, size_t length, unsigned char iv[16], @@ -295,15 +294,15 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, while ( length-- ) { memcpy( ov, iv, 16 ); - esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, iv, iv ); + esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, iv, iv ); - if ( mode == AES_DECRYPT ) { + if ( mode == ESP_AES_DECRYPT ) { ov[16] = *input; } c = *output++ = (unsigned char)( iv[0] ^ *input++ ); - if ( mode == AES_ENCRYPT ) { + if ( mode == ESP_AES_ENCRYPT ) { ov[16] = c; } @@ -318,7 +317,7 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, /* * AES-CTR buffer encryption/decryption */ -int esp_aes_crypt_ctr( AES_CTX *ctx, +int esp_aes_crypt_ctr( esp_aes_context *ctx, size_t length, size_t *nc_off, unsigned char nonce_counter[16], @@ -333,7 +332,7 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb_inner( ctx, AES_ENCRYPT, nonce_counter, stream_block ); + esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, nonce_counter, stream_block ); for ( i = 16; i > 0; i-- ) if ( ++nonce_counter[i - 1] != 0 ) { diff --git a/components/esp32/hwcrypto/bignum.c b/components/esp32/hwcrypto/bignum.c index 93b31e6f6..96f12419e 100644 --- a/components/esp32/hwcrypto/bignum.c +++ b/components/esp32/hwcrypto/bignum.c @@ -1,4 +1,7 @@ -/* +/** + * \brief Multi-precision integer library, ESP32 hardware accelerated version + * Based on mbedTLS version. + * * ESP32 hardware accelerated multi-precision integer functions * based on mbedTLS implementation * diff --git a/components/esp32/hwcrypto/sha.c b/components/esp32/hwcrypto/sha.c index 584383eb1..06be8b825 100644 --- a/components/esp32/hwcrypto/sha.c +++ b/components/esp32/hwcrypto/sha.c @@ -50,21 +50,21 @@ void esp_sha_release_hardware( void ) _lock_release(&sha_lock); } -void esp_sha1_init( SHA1_CTX *ctx ) +void esp_sha1_init( esp_sha_context *ctx ) { - bzero( ctx, sizeof( SHA1_CTX ) ); + bzero( ctx, sizeof( esp_sha_context ) ); } -void esp_sha1_free( SHA1_CTX *ctx ) +void esp_sha1_free( esp_sha_context *ctx ) { if ( ctx == NULL ) { return; } - bzero( ctx, sizeof( SHA1_CTX ) ); + bzero( ctx, sizeof( esp_sha_context ) ); } -void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) +void esp_sha1_clone( esp_sha_context *dst, const esp_sha_context *src ) { *dst = *src; } @@ -72,7 +72,7 @@ void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ) /* * SHA-1 context setup */ -void esp_sha1_start( SHA1_CTX *ctx ) +void esp_sha1_start( esp_sha_context *ctx ) { esp_sha_acquire_hardware(); ctx->context_type = SHA1; @@ -81,7 +81,7 @@ void esp_sha1_start( SHA1_CTX *ctx ) /* * SHA-1 process buffer */ -void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) +void esp_sha1_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -89,18 +89,16 @@ void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ) /* * SHA-1 final digest */ -void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ) +void esp_sha1_finish( esp_sha_context *ctx, unsigned char output[20] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); esp_sha_release_hardware(); } -/* - * output = SHA-1( input buffer ) - */ -void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ) +/* Full SHA-1 calculation */ +void esp_sha1( const unsigned char *input, size_t ilen, unsigned char output[20] ) { - SHA1_CTX ctx; + esp_sha_context ctx; esp_sha1_init( &ctx ); esp_sha1_start( &ctx ); @@ -109,21 +107,21 @@ void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char out esp_sha1_free( &ctx ); } -void esp_sha256_init( SHA256_CTX *ctx ) +void esp_sha256_init( esp_sha_context *ctx ) { - bzero( ctx, sizeof( SHA256_CTX ) ); + bzero( ctx, sizeof( esp_sha_context ) ); } -void esp_sha256_free( SHA256_CTX *ctx ) +void esp_sha256_free( esp_sha_context *ctx ) { if ( ctx == NULL ) { return; } - bzero( ctx, sizeof( SHA256_CTX ) ); + bzero( ctx, sizeof( esp_sha_context ) ); } -void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) +void esp_sha256_clone( esp_sha_context *dst, const esp_sha_context *src ) { *dst = *src; } @@ -131,7 +129,7 @@ void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ) /* * SHA-256 context setup */ -void esp_sha256_start( SHA256_CTX *ctx, int is224 ) +void esp_sha256_start( esp_sha_context *ctx, int is224 ) { esp_sha_acquire_hardware(); ets_sha_init(&ctx->context); @@ -148,7 +146,7 @@ void esp_sha256_start( SHA256_CTX *ctx, int is224 ) /* * SHA-256 process buffer */ -void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ) +void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -156,7 +154,7 @@ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen /* * SHA-256 final digest */ -void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) +void esp_sha256_finish( esp_sha_context *ctx, unsigned char output[32] ) { if ( ctx->context_type == SHA2_256 ) { ets_sha_finish(&ctx->context, ctx->context_type, output); @@ -169,11 +167,11 @@ void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ) } /* - * output = SHA-256( input buffer ) + * Full SHA-256 calculation */ -void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ) +void esp_sha256( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ) { - SHA256_CTX ctx; + esp_sha_context ctx; esp_sha256_init( &ctx ); esp_sha256_start( &ctx, is224 ); @@ -184,21 +182,21 @@ void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char o ///// -void esp_sha512_init( SHA512_CTX *ctx ) +void esp_sha512_init( esp_sha_context *ctx ) { - memset( ctx, 0, sizeof( SHA512_CTX ) ); + memset( ctx, 0, sizeof( esp_sha_context ) ); } -void esp_sha512_free( SHA512_CTX *ctx ) +void esp_sha512_free( esp_sha_context *ctx ) { if ( ctx == NULL ) { return; } - bzero( ctx, sizeof( SHA512_CTX ) ); + bzero( ctx, sizeof( esp_sha_context ) ); } -void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) +void esp_sha512_clone( esp_sha_context *dst, const esp_sha_context *src ) { *dst = *src; } @@ -206,7 +204,7 @@ void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ) /* * SHA-512 context setup */ -void esp_sha512_start( SHA512_CTX *ctx, int is384 ) +void esp_sha512_start( esp_sha_context *ctx, int is384 ) { esp_sha_acquire_hardware(); ets_sha_init(&ctx->context); @@ -223,7 +221,7 @@ void esp_sha512_start( SHA512_CTX *ctx, int is384 ) /* * SHA-512 process buffer */ -void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen ) +void esp_sha512_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); } @@ -231,18 +229,18 @@ void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen /* * SHA-512 final digest */ -void esp_sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ) +void esp_sha512_finish( esp_sha_context *ctx, unsigned char output[64] ) { ets_sha_finish(&ctx->context, ctx->context_type, output); esp_sha_release_hardware(); } /* - * output = SHA-512( input buffer ) + * Full SHA-512 calculation */ -void esp_sha512_output( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ) +void esp_sha512( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ) { - SHA512_CTX ctx; + esp_sha_context ctx; esp_sha512_init( &ctx ); esp_sha512_start( &ctx, is384 ); diff --git a/components/esp32/include/hwcrypto/aes.h b/components/esp32/include/hwcrypto/aes.h index 9c149a935..b6a632aff 100644 --- a/components/esp32/include/hwcrypto/aes.h +++ b/components/esp32/include/hwcrypto/aes.h @@ -1,8 +1,6 @@ /** - * \file esp_aes.h - * * \brief AES block cipher, ESP32 hardware accelerated version - * Based on mbedTLS version. + * Based on mbedTLS FIPS-197 compliant version. * * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd @@ -34,11 +32,11 @@ extern "C" { #endif /* padlock.c and aesni.c rely on these values! */ -#define AES_ENCRYPT 1 -#define AES_DECRYPT 0 +#define ESP_AES_ENCRYPT 1 +#define ESP_AES_DECRYPT 0 -#define ERR_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ -#define ERR_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ +#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ typedef struct { enum AES_BITS aesbits; @@ -58,7 +56,7 @@ typedef struct { uint32_t *rk; /*!< AES round keys */ KEY_CTX enc; KEY_CTX dec; -} aes_context, AES_CTX; +} esp_aes_context; /** * \brief Lock access to AES hardware unit @@ -86,14 +84,14 @@ void esp_aes_release_hardware( void ); * * \param ctx AES context to be initialized */ -void esp_aes_init( AES_CTX *ctx ); +void esp_aes_init( esp_aes_context *ctx ); /** * \brief Clear AES context * * \param ctx AES context to be cleared */ -void esp_aes_free( AES_CTX *ctx ); +void esp_aes_free( esp_aes_context *ctx ); /** * \brief AES key schedule (encryption) @@ -104,7 +102,7 @@ void esp_aes_free( AES_CTX *ctx ); * * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH */ -int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ); +int esp_aes_setkey_enc( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); /** * \brief AES key schedule (decryption) @@ -115,7 +113,7 @@ int esp_aes_setkey_enc( AES_CTX *ctx, const unsigned char *key, unsigned int key * * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH */ -int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int keybits ); +int esp_aes_setkey_dec( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); /** * \brief AES-ECB block encryption/decryption @@ -127,7 +125,7 @@ int esp_aes_setkey_dec( AES_CTX *ctx, const unsigned char *key, unsigned int key * * \return 0 if successful */ -int esp_aes_crypt_ecb( AES_CTX *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); +int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); /** * \brief AES-CBC buffer encryption/decryption @@ -151,7 +149,7 @@ int esp_aes_crypt_ecb( AES_CTX *ctx, int mode, const unsigned char input[16], un * * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH */ -int esp_aes_crypt_cbc( AES_CTX *ctx, +int esp_aes_crypt_cbc( esp_aes_context *ctx, int mode, size_t length, unsigned char iv[16], @@ -184,7 +182,7 @@ int esp_aes_crypt_cbc( AES_CTX *ctx, * * \return 0 if successful */ -int esp_aes_crypt_cfb128( AES_CTX *ctx, +int esp_aes_crypt_cfb128( esp_aes_context *ctx, int mode, size_t length, size_t *iv_off, @@ -216,7 +214,7 @@ int esp_aes_crypt_cfb128( AES_CTX *ctx, * * \return 0 if successful */ -int esp_aes_crypt_cfb8( AES_CTX *ctx, +int esp_aes_crypt_cfb8( esp_aes_context *ctx, int mode, size_t length, unsigned char iv[16], @@ -245,7 +243,7 @@ int esp_aes_crypt_cfb8( AES_CTX *ctx, * * \return 0 if successful */ -int esp_aes_crypt_ctr( AES_CTX *ctx, +int esp_aes_crypt_ctr( esp_aes_context *ctx, size_t length, size_t *nc_off, unsigned char nonce_counter[16], @@ -263,7 +261,7 @@ int esp_aes_crypt_ctr( AES_CTX *ctx, * \param input Plaintext block * \param output Output (ciphertext) block */ -void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ); +void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); /** * \brief Internal AES block decryption function @@ -274,7 +272,7 @@ void esp_aes_encrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char * \param input Ciphertext block * \param output Output (plaintext) block */ -void esp_aes_decrypt( AES_CTX *ctx, const unsigned char input[16], unsigned char output[16] ); +void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); #ifdef __cplusplus } diff --git a/components/esp32/include/hwcrypto/sha.h b/components/esp32/include/hwcrypto/sha.h index dbefcef06..a165c46c1 100644 --- a/components/esp32/include/hwcrypto/sha.h +++ b/components/esp32/include/hwcrypto/sha.h @@ -1,16 +1,24 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * ESP32 hardware accelerated SHA1/256/512 implementation + * based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ #ifndef _ESP_SHA_H_ #define _ESP_SHA_H_ @@ -27,11 +35,10 @@ extern "C" { * \brief SHA-1 context structure */ typedef struct { + /* both types defined in rom/sha.h */ SHA_CTX context; - enum SHA_TYPE context_type; /* defined in rom/sha.h */ -} sha_context; - -typedef sha_context SHA1_CTX; + enum SHA_TYPE context_type; +} esp_sha_context; /** * \brief Lock access to SHA hardware unit @@ -59,14 +66,14 @@ void esp_sha_release_hardware( void ); * * \param ctx SHA-1 context to be initialized */ -void esp_sha1_init( SHA1_CTX *ctx ); +void esp_sha1_init( esp_sha_context *ctx ); /** * \brief Clear SHA-1 context * * \param ctx SHA-1 context to be cleared */ -void esp_sha1_free( SHA1_CTX *ctx ); +void esp_sha1_free( esp_sha_context *ctx ); /** * \brief Clone (the state of) a SHA-1 context @@ -74,14 +81,14 @@ void esp_sha1_free( SHA1_CTX *ctx ); * \param dst The destination context * \param src The context to be cloned */ -void esp_sha1_clone( SHA1_CTX *dst, const SHA1_CTX *src ); +void esp_sha1_clone( esp_sha_context *dst, const esp_sha_context *src ); /** * \brief SHA-1 context setup * * \param ctx context to be initialized */ -void esp_sha1_start( SHA1_CTX *ctx ); +void esp_sha1_start( esp_sha_context *ctx ); /** * \brief SHA-1 process buffer @@ -90,7 +97,7 @@ void esp_sha1_start( SHA1_CTX *ctx ); * \param input buffer holding the data * \param ilen length of the input data */ -void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ); +void esp_sha1_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ); /** * \brief SHA-1 final digest @@ -98,36 +105,34 @@ void esp_sha1_update( SHA1_CTX *ctx, const unsigned char *input, size_t ilen ); * \param ctx SHA-1 context * \param output SHA-1 checksum result */ -void esp_sha1_finish( SHA1_CTX *ctx, unsigned char output[20] ); +void esp_sha1_finish( esp_sha_context *ctx, unsigned char output[20] ); /** - * \brief Output = SHA-1( input buffer ) + * \brief Calculate SHA-1 of input buffer * - * \param input buffer holding the data + * \param input buffer holding the data * \param ilen length of the input data * \param output SHA-1 checksum result */ -void esp_sha1_output( const unsigned char *input, size_t ilen, unsigned char output[20] ); +void esp_sha1( const unsigned char *input, size_t ilen, unsigned char output[20] ); /** * \brief SHA-256 context structure */ -typedef sha_context SHA256_CTX; - /** * \brief Initialize SHA-256 context * * \param ctx SHA-256 context to be initialized */ -void esp_sha256_init( SHA256_CTX *ctx ); +void esp_sha256_init( esp_sha_context *ctx ); /** * \brief Clear SHA-256 context * * \param ctx SHA-256 context to be cleared */ -void esp_sha256_free( SHA256_CTX *ctx ); +void esp_sha256_free( esp_sha_context *ctx ); /** * \brief Clone (the state of) a SHA-256 context @@ -135,7 +140,7 @@ void esp_sha256_free( SHA256_CTX *ctx ); * \param dst The destination context * \param src The context to be cloned */ -void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ); +void esp_sha256_clone( esp_sha_context *dst, const esp_sha_context *src ); /** * \brief SHA-256 context setup @@ -143,7 +148,7 @@ void esp_sha256_clone( SHA256_CTX *dst, const SHA256_CTX *src ); * \param ctx context to be initialized * \param is224 0 = use SHA256, 1 = use SHA224 */ -void esp_sha256_start( SHA256_CTX *ctx, int is224 ); +void esp_sha256_start( esp_sha_context *ctx, int is224 ); /** * \brief SHA-256 process buffer @@ -152,7 +157,7 @@ void esp_sha256_start( SHA256_CTX *ctx, int is224 ); * \param input buffer holding the data * \param ilen length of the input data */ -void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen ); +void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ); /** * \brief SHA-256 final digest @@ -160,17 +165,17 @@ void esp_sha256_update( SHA256_CTX *ctx, const unsigned char *input, size_t ilen * \param ctx SHA-256 context * \param output SHA-224/256 checksum result */ -void esp_sha256_finish( SHA256_CTX *ctx, unsigned char output[32] ); +void esp_sha256_finish( esp_sha_context *ctx, unsigned char output[32] ); /** - * \brief Output = SHA-256( input buffer ) + * \brief Calculate SHA-256 of input buffer * - * \param input buffer holding the data + * \param input buffer holding the data * \param ilen length of the input data * \param output SHA-224/256 checksum result * \param is224 0 = use SHA256, 1 = use SHA224 */ -void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ); +void esp_sha256( const unsigned char *input, size_t ilen, unsigned char output[32], int is224 ); // @@ -178,21 +183,19 @@ void esp_sha256_output( const unsigned char *input, size_t ilen, unsigned char o * \brief SHA-512 context structure */ -typedef sha_context SHA512_CTX; - /** * \brief Initialize SHA-512 context * * \param ctx SHA-512 context to be initialized */ -void esp_sha512_init( SHA512_CTX *ctx ); +void esp_sha512_init( esp_sha_context *ctx ); /** * \brief Clear SHA-512 context * * \param ctx SHA-512 context to be cleared */ -void esp_sha512_free( SHA512_CTX *ctx ); +void esp_sha512_free( esp_sha_context *ctx ); /** * \brief Clone (the state of) a SHA-512 context @@ -200,7 +203,7 @@ void esp_sha512_free( SHA512_CTX *ctx ); * \param dst The destination context * \param src The context to be cloned */ -void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ); +void esp_sha512_clone( esp_sha_context *dst, const esp_sha_context *src ); /** * \brief SHA-512 context setup @@ -208,7 +211,7 @@ void esp_sha512_clone( SHA512_CTX *dst, const SHA512_CTX *src ); * \param ctx context to be initialized * \param is384 0 = use SHA512, 1 = use SHA384 */ -void esp_sha512_start( SHA512_CTX *ctx, int is384 ); +void esp_sha512_start( esp_sha_context *ctx, int is384 ); /** * \brief SHA-512 process buffer @@ -217,7 +220,7 @@ void esp_sha512_start( SHA512_CTX *ctx, int is384 ); * \param input buffer holding the data * \param ilen length of the input data */ -void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen ); +void esp_sha512_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ); /** * \brief SHA-512 final digest @@ -225,17 +228,17 @@ void esp_sha512_update( SHA512_CTX *ctx, const unsigned char *input, size_t ilen * \param ctx SHA-512 context * \param output SHA-384/512 checksum result */ -void esp_sha512_finish( SHA512_CTX *ctx, unsigned char output[64] ); +void esp_sha512_finish( esp_sha_context *ctx, unsigned char output[64] ); /** - * \brief Output = SHA-512( input buffer ) + * \brief Calculate SHA-512 of input buffer. * - * \param input buffer holding the data + * \param input buffer holding the data * \param ilen length of the input data * \param output SHA-384/512 checksum result * \param is384 0 = use SHA512, 1 = use SHA384 */ -void esp_sha512_output( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ); +void esp_sha512( const unsigned char *input, size_t ilen, unsigned char output[64], int is384 ); // From a32e954f67bec9e933b6a454f8be89ccf58ae604 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Tue, 6 Sep 2016 11:05:56 +1000 Subject: [PATCH 15/57] hwcrypto sha: Feed one block at a time to hardware SHA implementation Fixes a bug where some longer block sizes produced incorrect results. --- components/esp32/hwcrypto/sha.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/components/esp32/hwcrypto/sha.c b/components/esp32/hwcrypto/sha.c index 06be8b825..78ecbf771 100644 --- a/components/esp32/hwcrypto/sha.c +++ b/components/esp32/hwcrypto/sha.c @@ -50,6 +50,18 @@ void esp_sha_release_hardware( void ) _lock_release(&sha_lock); } +/* Generic esp_shaX_update implementation */ +static void esp_sha_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen, size_t block_size) +{ + /* Feed the SHA engine one block at a time */ + while(ilen > 0) { + size_t chunk_len = (ilen > block_size) ? block_size : ilen; + ets_sha_update(&ctx->context, ctx->context_type, input, chunk_len * 8); + input += chunk_len; + ilen -= chunk_len; + } +} + void esp_sha1_init( esp_sha_context *ctx ) { bzero( ctx, sizeof( esp_sha_context ) ); @@ -83,7 +95,7 @@ void esp_sha1_start( esp_sha_context *ctx ) */ void esp_sha1_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); + esp_sha_update(ctx, input, ilen, 64); } /* @@ -148,7 +160,7 @@ void esp_sha256_start( esp_sha_context *ctx, int is224 ) */ void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); + esp_sha_update(ctx, input, ilen, 64); } /* @@ -223,7 +235,7 @@ void esp_sha512_start( esp_sha_context *ctx, int is384 ) */ void esp_sha512_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { - ets_sha_update(&ctx->context, ctx->context_type, input, ilen * 8); + esp_sha_update(ctx, input, ilen, 128); } /* From d951ab266121fdd3ce8c18170c182e60274eff4a Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 7 Sep 2016 14:48:20 +1000 Subject: [PATCH 16/57] hwcrypto aes: Performance tweak, only write key to hardware once Shaves ~10% off time to compute AES-CBC --- components/esp32/hwcrypto/aes.c | 39 +++++++++++++++++---------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/components/esp32/hwcrypto/aes.c b/components/esp32/hwcrypto/aes.c index 16ed704ba..e08486de2 100644 --- a/components/esp32/hwcrypto/aes.c +++ b/components/esp32/hwcrypto/aes.c @@ -114,23 +114,17 @@ int esp_aes_setkey_dec( esp_aes_context *ctx, const unsigned char *key, } /* - * Inner AES-ECB function. Call only when protected by esp_aes_acquire_hardware(). + * Helper function to copy key from esp_aes_context buffer + * to hardware key registers. * - * Optimisation to prevent overhead of locking each time when - * encrypting many blocks in sequence. + * Only call when protected by esp_aes_acquire_hardware(). */ -static int esp_aes_crypt_ecb_inner( esp_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16] ) +static inline int esp_aes_setkey_hardware( esp_aes_context *ctx, int mode) { if ( mode == ESP_AES_ENCRYPT ) { ets_aes_setkey_enc(ctx->enc.key, ctx->enc.aesbits); - ets_aes_crypt(input, output); } else { ets_aes_setkey_dec(ctx->enc.key, ctx->enc.aesbits); - /* TODO: previous commit esp_aes_decrypt function calls this but this is not correct! */ - ets_aes_crypt(input, output); } return 0; } @@ -143,7 +137,8 @@ void esp_aes_encrypt( esp_aes_context *ctx, unsigned char output[16] ) { esp_aes_acquire_hardware(); - esp_aes_crypt_ecb_inner(ctx, ESP_AES_ENCRYPT, input, output); + esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); + ets_aes_crypt(input, output); esp_aes_release_hardware(); } @@ -156,7 +151,8 @@ void esp_aes_decrypt( esp_aes_context *ctx, unsigned char output[16] ) { esp_aes_acquire_hardware(); - esp_aes_crypt_ecb_inner(ctx, ESP_AES_DECRYPT, input, output); + esp_aes_setkey_hardware(ctx, ESP_AES_DECRYPT); + ets_aes_crypt(input, output); esp_aes_release_hardware(); } @@ -170,7 +166,8 @@ int esp_aes_crypt_ecb( esp_aes_context *ctx, unsigned char output[16] ) { esp_aes_acquire_hardware(); - esp_aes_crypt_ecb_inner(ctx, mode, input, output); + esp_aes_setkey_hardware(ctx, mode); + ets_aes_crypt(input, output); esp_aes_release_hardware(); return 0; } @@ -194,11 +191,12 @@ int esp_aes_crypt_cbc( esp_aes_context *ctx, } esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, mode); if ( mode == ESP_AES_DECRYPT ) { while ( length > 0 ) { memcpy( temp, input, 16 ); - esp_aes_crypt_ecb_inner( ctx, mode, input, output ); + ets_aes_crypt(input, output); for ( i = 0; i < 16; i++ ) { output[i] = (unsigned char)( output[i] ^ iv[i] ); @@ -216,7 +214,7 @@ int esp_aes_crypt_cbc( esp_aes_context *ctx, output[i] = (unsigned char)( input[i] ^ iv[i] ); } - esp_aes_crypt_ecb_inner( ctx, mode, output, output ); + ets_aes_crypt(output, output); memcpy( iv, output, 16 ); input += 16; @@ -245,11 +243,12 @@ int esp_aes_crypt_cfb128( esp_aes_context *ctx, size_t n = *iv_off; esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, mode); if ( mode == ESP_AES_DECRYPT ) { while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, iv, iv ); + ets_aes_crypt(iv, iv ); } c = *input++; @@ -261,7 +260,7 @@ int esp_aes_crypt_cfb128( esp_aes_context *ctx, } else { while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, iv, iv ); + ets_aes_crypt(iv, iv ); } iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); @@ -291,10 +290,11 @@ int esp_aes_crypt_cfb8( esp_aes_context *ctx, unsigned char ov[17]; esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, mode); while ( length-- ) { memcpy( ov, iv, 16 ); - esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, iv, iv ); + ets_aes_crypt(iv, iv); if ( mode == ESP_AES_DECRYPT ) { ov[16] = *input; @@ -329,10 +329,11 @@ int esp_aes_crypt_ctr( esp_aes_context *ctx, size_t n = *nc_off; esp_aes_acquire_hardware(); + esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); while ( length-- ) { if ( n == 0 ) { - esp_aes_crypt_ecb_inner( ctx, ESP_AES_ENCRYPT, nonce_counter, stream_block ); + ets_aes_crypt(nonce_counter, stream_block); for ( i = 16; i > 0; i-- ) if ( ++nonce_counter[i - 1] != 0 ) { From 2211759cc08779ad0bd1fd471db123eab5bc1457 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 8 Sep 2016 17:06:27 +1000 Subject: [PATCH 17/57] hwcrypto aes: Fix bugs w/ ECB decrypt, CFB modes --- components/esp32/hwcrypto/aes.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/esp32/hwcrypto/aes.c b/components/esp32/hwcrypto/aes.c index e08486de2..169465822 100644 --- a/components/esp32/hwcrypto/aes.c +++ b/components/esp32/hwcrypto/aes.c @@ -124,7 +124,7 @@ static inline int esp_aes_setkey_hardware( esp_aes_context *ctx, int mode) if ( mode == ESP_AES_ENCRYPT ) { ets_aes_setkey_enc(ctx->enc.key, ctx->enc.aesbits); } else { - ets_aes_setkey_dec(ctx->enc.key, ctx->enc.aesbits); + ets_aes_setkey_dec(ctx->dec.key, ctx->dec.aesbits); } return 0; } @@ -243,7 +243,7 @@ int esp_aes_crypt_cfb128( esp_aes_context *ctx, size_t n = *iv_off; esp_aes_acquire_hardware(); - esp_aes_setkey_hardware(ctx, mode); + esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); if ( mode == ESP_AES_DECRYPT ) { while ( length-- ) { @@ -290,7 +290,7 @@ int esp_aes_crypt_cfb8( esp_aes_context *ctx, unsigned char ov[17]; esp_aes_acquire_hardware(); - esp_aes_setkey_hardware(ctx, mode); + esp_aes_setkey_hardware(ctx, ESP_AES_ENCRYPT); while ( length-- ) { memcpy( ov, iv, 16 ); From 95defc7d32fcc085e2470f790785352a0ec2a6d8 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Thu, 8 Sep 2016 17:41:43 +0800 Subject: [PATCH 18/57] mbedtls: Use hardware accelerated AES, SHA, bignum --- components/esp32/Makefile | 2 + components/esp32/hwcrypto/bignum.c | 2194 ----------------- components/esp32/include/hwcrypto/bignum.h | 727 ------ components/mbedtls/Makefile | 3 + .../mbedtls/include/mbedtls/esp_config.h | 20 +- components/mbedtls/library/bignum.c | 4 + components/mbedtls/port/esp_bignum.c | 536 ++++ components/mbedtls/port/esp_hardware.c | 28 +- components/mbedtls/port/include/aes_alt.h | 4 +- components/mbedtls/port/include/bignum_alt.h | 77 - components/mbedtls/port/include/sha1_alt.h | 7 +- components/mbedtls/port/include/sha256_alt.h | 7 +- components/mbedtls/port/include/sha512_alt.h | 6 +- 13 files changed, 572 insertions(+), 3043 deletions(-) delete mode 100644 components/esp32/hwcrypto/bignum.c delete mode 100644 components/esp32/include/hwcrypto/bignum.h create mode 100644 components/mbedtls/port/esp_bignum.c delete mode 100644 components/mbedtls/port/include/bignum_alt.h diff --git a/components/esp32/Makefile b/components/esp32/Makefile index 1d55d0ff6..95647c2eb 100644 --- a/components/esp32/Makefile +++ b/components/esp32/Makefile @@ -8,6 +8,8 @@ # -include $(PROJECT_PATH)/build/include/config/auto.conf +COMPONENT_SRCDIRS := . hwcrypto + LIBS := crypto core net80211 phy rtc pp wpa wps ifeq ($(CONFIG_MEMMAP_BT),y) diff --git a/components/esp32/hwcrypto/bignum.c b/components/esp32/hwcrypto/bignum.c deleted file mode 100644 index 96f12419e..000000000 --- a/components/esp32/hwcrypto/bignum.c +++ /dev/null @@ -1,2194 +0,0 @@ -/** - * \brief Multi-precision integer library, ESP32 hardware accelerated version - * Based on mbedTLS version. - * - * ESP32 hardware accelerated multi-precision integer functions - * based on mbedTLS implementation - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -/* - * The following sources were referenced in the design of this Multi-precision - * Integer library: - * - * [1] Handbook of Applied Cryptography - 1997 - * Menezes, van Oorschot and Vanstone - * - * [2] Multi-Precision Math - * Tom St Denis - * https://github.com/libtom/libtommath/blob/develop/tommath.pdf - * - * [3] GNU Multi-Precision Arithmetic Library - * https://gmplib.org/manual/index.html - * - */ - -#include -#include -#include -#include "hwcrypto/bignum.h" -#include "rom/ets_sys.h" -#include "rom/bigint.h" - -/* Implementation that should never be optimized out by the compiler */ -//static void bzero( void *v, size_t n ) { -// volatile unsigned char *p = v; while( n-- ) *p++ = 0; -//} - -#define ciL (sizeof(esp_mpi_uint)) /* chars in limb */ -#define biL (ciL << 3) /* bits in limb */ -#define biH (ciL << 2) /* half limb size */ - -#define MPI_SIZE_T_MAX ( (size_t) -1 ) /* SIZE_T_MAX is not standard */ - -/* - * Convert between bits/chars and number of limbs - * Divide first in order to avoid potential overflows - */ -#define BITS_TO_LIMBS(i) ( (i) / biL + ( (i) % biL != 0 ) ) -#define CHARS_TO_LIMBS(i) ( (i) / ciL + ( (i) % ciL != 0 ) ) - -static _lock_t mpi_lock; - -void esp_mpi_acquire_hardware( void ) -{ - /* newlib locks lazy initialize on ESP-IDF */ - _lock_acquire(&mpi_lock); - ets_bigint_enable(); -} - -void esp_mpi_release_hardware( void ) -{ - ets_bigint_disable(); - _lock_release(&mpi_lock); -} - - -/* - * Initialize one MPI - */ -void esp_mpi_init( mpi *X ) -{ - if( X == NULL ) - return; - - X->s = 1; - X->n = 0; - X->p = NULL; -} - -/* - * Unallocate one MPI - */ -void esp_mpi_free( mpi *X ) -{ - if( X == NULL ) - return; - - if( X->p != NULL ) - { - bzero( X->p, X->n * ciL ); - free( X->p ); - } - - X->s = 1; - X->n = 0; - X->p = NULL; -} - -/* - * Enlarge to the specified number of limbs - */ -int esp_mpi_grow( mpi *X, size_t nblimbs ) -{ - esp_mpi_uint *p; - - if( nblimbs > MPI_MAX_LIMBS ) - return( ERR_MPI_ALLOC_FAILED ); - - if( X->n < nblimbs ) - { - if( ( p = calloc( nblimbs, ciL ) ) == NULL ) - return( ERR_MPI_ALLOC_FAILED ); - - if( X->p != NULL ) - { - memcpy( p, X->p, X->n * ciL ); - bzero( X->p, X->n * ciL ); - free( X->p ); - } - - X->n = nblimbs; - X->p = p; - } - - return( 0 ); -} - -/* - * Resize down as much as possible, - * while keeping at least the specified number of limbs - */ -int esp_mpi_shrink( mpi *X, size_t nblimbs ) -{ - esp_mpi_uint *p; - size_t i; - - /* Actually resize up in this case */ - if( X->n <= nblimbs ) - return( esp_mpi_grow( X, nblimbs ) ); - - for( i = X->n - 1; i > 0; i-- ) - if( X->p[i] != 0 ) - break; - i++; - - if( i < nblimbs ) - i = nblimbs; - - if( ( p = calloc( i, ciL ) ) == NULL ) - return( ERR_MPI_ALLOC_FAILED ); - - if( X->p != NULL ) - { - memcpy( p, X->p, i * ciL ); - bzero( X->p, X->n * ciL ); - free( X->p ); - } - - X->n = i; - X->p = p; - - return( 0 ); -} - -/* - * Copy the contents of Y into X - */ -int esp_mpi_copy( mpi *X, const mpi *Y ) -{ - int ret; - size_t i; - - if( X == Y ) - return( 0 ); - - if( Y->p == NULL ) - { - esp_mpi_free( X ); - return( 0 ); - } - - for( i = Y->n - 1; i > 0; i-- ) - if( Y->p[i] != 0 ) - break; - i++; - - X->s = Y->s; - - MPI_CHK( esp_mpi_grow( X, i ) ); - - memset( X->p, 0, X->n * ciL ); - memcpy( X->p, Y->p, i * ciL ); - -cleanup: - - return( ret ); -} - -/* - * Swap the contents of X and Y - */ -void esp_mpi_swap( mpi *X, mpi *Y ) -{ - mpi T; - - memcpy( &T, X, sizeof( mpi ) ); - memcpy( X, Y, sizeof( mpi ) ); - memcpy( Y, &T, sizeof( mpi ) ); -} - -/* - * Conditionally assign X = Y, without leaking information - * about whether the assignment was made or not. - * (Leaking information about the respective sizes of X and Y is ok however.) - */ -int esp_mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ) -{ - int ret = 0; - size_t i; - - /* make sure assign is 0 or 1 in a time-constant manner */ - assign = (assign | (unsigned char)-assign) >> 7; - - MPI_CHK( esp_mpi_grow( X, Y->n ) ); - - X->s = X->s * ( 1 - assign ) + Y->s * assign; - - for( i = 0; i < Y->n; i++ ) - X->p[i] = X->p[i] * ( 1 - assign ) + Y->p[i] * assign; - - for( ; i < X->n; i++ ) - X->p[i] *= ( 1 - assign ); - -cleanup: - return( ret ); -} - -/* - * Conditionally swap X and Y, without leaking information - * about whether the swap was made or not. - * Here it is not ok to simply swap the pointers, which whould lead to - * different memory access patterns when X and Y are used afterwards. - */ -int esp_mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char swap ) -{ - int ret, s; - size_t i; - esp_mpi_uint tmp; - - if( X == Y ) - return( 0 ); - - /* make sure swap is 0 or 1 in a time-constant manner */ - swap = (swap | (unsigned char)-swap) >> 7; - - MPI_CHK( esp_mpi_grow( X, Y->n ) ); - MPI_CHK( esp_mpi_grow( Y, X->n ) ); - - s = X->s; - X->s = X->s * ( 1 - swap ) + Y->s * swap; - Y->s = Y->s * ( 1 - swap ) + s * swap; - - - for( i = 0; i < X->n; i++ ) - { - tmp = X->p[i]; - X->p[i] = X->p[i] * ( 1 - swap ) + Y->p[i] * swap; - Y->p[i] = Y->p[i] * ( 1 - swap ) + tmp * swap; - } - -cleanup: - return( ret ); -} - -/* - * Set value from integer - */ -int esp_mpi_lset( mpi *X, esp_mpi_sint z ) -{ - int ret; - - MPI_CHK( esp_mpi_grow( X, 1 ) ); - memset( X->p, 0, X->n * ciL ); - - X->p[0] = ( z < 0 ) ? -z : z; - X->s = ( z < 0 ) ? -1 : 1; - -cleanup: - - return( ret ); -} - -/* - * Get a specific bit - */ -int esp_mpi_get_bit( const mpi *X, size_t pos ) -{ - if( X->n * biL <= pos ) - return( 0 ); - - return( ( X->p[pos / biL] >> ( pos % biL ) ) & 0x01 ); -} - -/* - * Set a bit to a specific value of 0 or 1 - */ -int esp_mpi_set_bit( mpi *X, size_t pos, unsigned char val ) -{ - int ret = 0; - size_t off = pos / biL; - size_t idx = pos % biL; - - if( val != 0 && val != 1 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - if( X->n * biL <= pos ) - { - if( val == 0 ) - return( 0 ); - - MPI_CHK( esp_mpi_grow( X, off + 1 ) ); - } - - X->p[off] &= ~( (esp_mpi_uint) 0x01 << idx ); - X->p[off] |= (esp_mpi_uint) val << idx; - -cleanup: - - return( ret ); -} - -/* - * Return the number of less significant zero-bits - */ -size_t esp_mpi_lsb( const mpi *X ) -{ - size_t i, j, count = 0; - - for( i = 0; i < X->n; i++ ) - for( j = 0; j < biL; j++, count++ ) - if( ( ( X->p[i] >> j ) & 1 ) != 0 ) - return( count ); - - return( 0 ); -} - -/* - * Count leading zero bits in a given integer - */ -static size_t clz( const esp_mpi_uint x ) -{ - size_t j; - esp_mpi_uint mask = (esp_mpi_uint) 1 << (biL - 1); - - for( j = 0; j < biL; j++ ) - { - if( x & mask ) break; - - mask >>= 1; - } - - return j; -} - -/* - * Return the number of bits - */ -size_t esp_mpi_bitlen( const mpi *X ) -{ - size_t i, j; - - if( X->n == 0 ) - return( 0 ); - - for( i = X->n - 1; i > 0; i-- ) - if( X->p[i] != 0 ) - break; - - j = biL - clz( X->p[i] ); - - return( ( i * biL ) + j ); -} - -/* - * Return the total size in bytes - */ -size_t esp_mpi_size( const mpi *X ) -{ - return( ( esp_mpi_bitlen( X ) + 7 ) >> 3 ); -} - -/* - * Convert an ASCII character to digit value - */ -static int esp_mpi_get_digit( esp_mpi_uint *d, int radix, char c ) -{ - *d = 255; - - if( c >= 0x30 && c <= 0x39 ) *d = c - 0x30; - if( c >= 0x41 && c <= 0x46 ) *d = c - 0x37; - if( c >= 0x61 && c <= 0x66 ) *d = c - 0x57; - - if( *d >= (esp_mpi_uint) radix ) - return( ERR_MPI_INVALID_CHARACTER ); - - return( 0 ); -} - -/* - * Import from an ASCII string - */ -int esp_mpi_read_string( mpi *X, int radix, const char *s ) -{ - int ret; - size_t i, j, slen, n; - esp_mpi_uint d; - mpi T; - - if( radix < 2 || radix > 16 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - esp_mpi_init( &T ); - - slen = strlen( s ); - - if( radix == 16 ) - { - if( slen > MPI_SIZE_T_MAX >> 2 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - n = BITS_TO_LIMBS( slen << 2 ); - - MPI_CHK( esp_mpi_grow( X, n ) ); - MPI_CHK( esp_mpi_lset( X, 0 ) ); - - for( i = slen, j = 0; i > 0; i--, j++ ) - { - if( i == 1 && s[i - 1] == '-' ) - { - X->s = -1; - break; - } - - MPI_CHK( esp_mpi_get_digit( &d, radix, s[i - 1] ) ); - X->p[j / ( 2 * ciL )] |= d << ( ( j % ( 2 * ciL ) ) << 2 ); - } - } - else - { - MPI_CHK( esp_mpi_lset( X, 0 ) ); - - for( i = 0; i < slen; i++ ) - { - if( i == 0 && s[i] == '-' ) - { - X->s = -1; - continue; - } - - MPI_CHK( esp_mpi_get_digit( &d, radix, s[i] ) ); - MPI_CHK( esp_mpi_mul_int( &T, X, radix ) ); - - if( X->s == 1 ) - { - MPI_CHK( esp_mpi_add_int( X, &T, d ) ); - } - else - { - MPI_CHK( esp_mpi_sub_int( X, &T, d ) ); - } - } - } - -cleanup: - - esp_mpi_free( &T ); - - return( ret ); -} - -/* - * Helper to write the digits high-order first - */ -static int esp_mpi_write_hlp( mpi *X, int radix, char **p ) -{ - int ret; - esp_mpi_uint r; - - if( radix < 2 || radix > 16 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - MPI_CHK( esp_mpi_mod_int( &r, X, radix ) ); - MPI_CHK( esp_mpi_div_int( X, NULL, X, radix ) ); - - if( esp_mpi_cmp_int( X, 0 ) != 0 ) - MPI_CHK( esp_mpi_write_hlp( X, radix, p ) ); - - if( r < 10 ) - *(*p)++ = (char)( r + 0x30 ); - else - *(*p)++ = (char)( r + 0x37 ); - -cleanup: - - return( ret ); -} - -/* - * Export into an ASCII string - */ -int esp_mpi_write_string( const mpi *X, int radix, - char *buf, size_t buflen, size_t *olen ) -{ - int ret = 0; - size_t n; - char *p; - mpi T; - - if( radix < 2 || radix > 16 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - n = esp_mpi_bitlen( X ); - if( radix >= 4 ) n >>= 1; - if( radix >= 16 ) n >>= 1; - n += 3; - - if( buflen < n ) - { - *olen = n; - return( ERR_MPI_BUFFER_TOO_SMALL ); - } - - p = buf; - esp_mpi_init( &T ); - - if( X->s == -1 ) - *p++ = '-'; - - if( radix == 16 ) - { - int c; - size_t i, j, k; - - for( i = X->n, k = 0; i > 0; i-- ) - { - for( j = ciL; j > 0; j-- ) - { - c = ( X->p[i - 1] >> ( ( j - 1 ) << 3) ) & 0xFF; - - if( c == 0 && k == 0 && ( i + j ) != 2 ) - continue; - - *(p++) = "0123456789ABCDEF" [c / 16]; - *(p++) = "0123456789ABCDEF" [c % 16]; - k = 1; - } - } - } - else - { - MPI_CHK( esp_mpi_copy( &T, X ) ); - - if( T.s == -1 ) - T.s = 1; - - MPI_CHK( esp_mpi_write_hlp( &T, radix, &p ) ); - } - - *p++ = '\0'; - *olen = p - buf; - -cleanup: - - esp_mpi_free( &T ); - - return( ret ); -} - -/* - * Import X from unsigned binary data, big endian - */ -int esp_mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ) -{ - int ret; - size_t i, j, n; - - for( n = 0; n < buflen; n++ ) - if( buf[n] != 0 ) - break; - - MPI_CHK( esp_mpi_grow( X, CHARS_TO_LIMBS( buflen - n ) ) ); - MPI_CHK( esp_mpi_lset( X, 0 ) ); - - for( i = buflen, j = 0; i > n; i--, j++ ) - X->p[j / ciL] |= ((esp_mpi_uint) buf[i - 1]) << ((j % ciL) << 3); - -cleanup: - - return( ret ); -} - -/* - * Export X into unsigned binary data, big endian - */ -int esp_mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ) -{ - size_t i, j, n; - - n = esp_mpi_size( X ); - - if( buflen < n ) - return( ERR_MPI_BUFFER_TOO_SMALL ); - - memset( buf, 0, buflen ); - - for( i = buflen - 1, j = 0; n > 0; i--, j++, n-- ) - buf[i] = (unsigned char)( X->p[j / ciL] >> ((j % ciL) << 3) ); - - return( 0 ); -} - -/* - * Left-shift: X <<= count - */ -int esp_mpi_shift_l( mpi *X, size_t count ) -{ - int ret; - size_t i, v0, t1; - esp_mpi_uint r0 = 0, r1; - - v0 = count / (biL ); - t1 = count & (biL - 1); - - i = esp_mpi_bitlen( X ) + count; - - if( X->n * biL < i ) - MPI_CHK( esp_mpi_grow( X, BITS_TO_LIMBS( i ) ) ); - - ret = 0; - - /* - * shift by count / limb_size - */ - if( v0 > 0 ) - { - for( i = X->n; i > v0; i-- ) - X->p[i - 1] = X->p[i - v0 - 1]; - - for( ; i > 0; i-- ) - X->p[i - 1] = 0; - } - - /* - * shift by count % limb_size - */ - if( t1 > 0 ) - { - for( i = v0; i < X->n; i++ ) - { - r1 = X->p[i] >> (biL - t1); - X->p[i] <<= t1; - X->p[i] |= r0; - r0 = r1; - } - } - -cleanup: - - return( ret ); -} - -/* - * Right-shift: X >>= count - */ -int esp_mpi_shift_r( mpi *X, size_t count ) -{ - size_t i, v0, v1; - esp_mpi_uint r0 = 0, r1; - - v0 = count / biL; - v1 = count & (biL - 1); - - if( v0 > X->n || ( v0 == X->n && v1 > 0 ) ) - return esp_mpi_lset( X, 0 ); - - /* - * shift by count / limb_size - */ - if( v0 > 0 ) - { - for( i = 0; i < X->n - v0; i++ ) - X->p[i] = X->p[i + v0]; - - for( ; i < X->n; i++ ) - X->p[i] = 0; - } - - /* - * shift by count % limb_size - */ - if( v1 > 0 ) - { - for( i = X->n; i > 0; i-- ) - { - r1 = X->p[i - 1] << (biL - v1); - X->p[i - 1] >>= v1; - X->p[i - 1] |= r0; - r0 = r1; - } - } - - return( 0 ); -} - -/* - * Compare unsigned values - */ -int esp_mpi_cmp_abs( const mpi *X, const mpi *Y ) -{ - size_t i, j; - - for( i = X->n; i > 0; i-- ) - if( X->p[i - 1] != 0 ) - break; - - for( j = Y->n; j > 0; j-- ) - if( Y->p[j - 1] != 0 ) - break; - - if( i == 0 && j == 0 ) - return( 0 ); - - if( i > j ) return( 1 ); - if( j > i ) return( -1 ); - - for( ; i > 0; i-- ) - { - if( X->p[i - 1] > Y->p[i - 1] ) return( 1 ); - if( X->p[i - 1] < Y->p[i - 1] ) return( -1 ); - } - - return( 0 ); -} - -/* - * Compare signed values - */ -int esp_mpi_cmp_mpi( const mpi *X, const mpi *Y ) -{ - size_t i, j; - - for( i = X->n; i > 0; i-- ) - if( X->p[i - 1] != 0 ) - break; - - for( j = Y->n; j > 0; j-- ) - if( Y->p[j - 1] != 0 ) - break; - - if( i == 0 && j == 0 ) - return( 0 ); - - if( i > j ) return( X->s ); - if( j > i ) return( -Y->s ); - - if( X->s > 0 && Y->s < 0 ) return( 1 ); - if( Y->s > 0 && X->s < 0 ) return( -1 ); - - for( ; i > 0; i-- ) - { - if( X->p[i - 1] > Y->p[i - 1] ) return( X->s ); - if( X->p[i - 1] < Y->p[i - 1] ) return( -X->s ); - } - - return( 0 ); -} - -/* - * Compare signed values - */ -int esp_mpi_cmp_int( const mpi *X, esp_mpi_sint z ) -{ - mpi Y; - esp_mpi_uint p[1]; - - *p = ( z < 0 ) ? -z : z; - Y.s = ( z < 0 ) ? -1 : 1; - Y.n = 1; - Y.p = p; - - return( esp_mpi_cmp_mpi( X, &Y ) ); -} - -/* - * Unsigned addition: X = |A| + |B| (HAC 14.7) - */ -int esp_mpi_add_abs( mpi *X, const mpi *A, const mpi *B ) -{ - int ret; - size_t i, j; - esp_mpi_uint *o, *p, c; - - if( X == B ) - { - const mpi *T = A; A = X; B = T; - } - - if( X != A ) - MPI_CHK( esp_mpi_copy( X, A ) ); - - /* - * X should always be positive as a result of unsigned additions. - */ - X->s = 1; - - for( j = B->n; j > 0; j-- ) - if( B->p[j - 1] != 0 ) - break; - - MPI_CHK( esp_mpi_grow( X, j ) ); - - o = B->p; p = X->p; c = 0; - - for( i = 0; i < j; i++, o++, p++ ) - { - *p += c; c = ( *p < c ); - *p += *o; c += ( *p < *o ); - } - - while( c != 0 ) - { - if( i >= X->n ) - { - MPI_CHK( esp_mpi_grow( X, i + 1 ) ); - p = X->p + i; - } - - *p += c; c = ( *p < c ); i++; p++; - } - -cleanup: - - return( ret ); -} - -/* - * Helper for mpi subtraction - */ -static void esp_mpi_sub_hlp( size_t n, esp_mpi_uint *s, esp_mpi_uint *d ) -{ - size_t i; - esp_mpi_uint c, z; - - for( i = c = 0; i < n; i++, s++, d++ ) - { - z = ( *d < c ); *d -= c; - c = ( *d < *s ) + z; *d -= *s; - } - - while( c != 0 ) - { - z = ( *d < c ); *d -= c; - c = z; i++; d++; - } -} - -/* - * Unsigned subtraction: X = |A| - |B| (HAC 14.9) - */ -int esp_mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ) -{ - mpi TB; - int ret; - size_t n; - - if( esp_mpi_cmp_abs( A, B ) < 0 ) - return( ERR_MPI_NEGATIVE_VALUE ); - - esp_mpi_init( &TB ); - - if( X == B ) - { - MPI_CHK( esp_mpi_copy( &TB, B ) ); - B = &TB; - } - - if( X != A ) - MPI_CHK( esp_mpi_copy( X, A ) ); - - /* - * X should always be positive as a result of unsigned subtractions. - */ - X->s = 1; - - ret = 0; - - for( n = B->n; n > 0; n-- ) - if( B->p[n - 1] != 0 ) - break; - - esp_mpi_sub_hlp( n, B->p, X->p ); - -cleanup: - - esp_mpi_free( &TB ); - - return( ret ); -} - -/* - * Signed addition: X = A + B - */ -int esp_mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ) -{ - int ret, s = A->s; - - if( A->s * B->s < 0 ) - { - if( esp_mpi_cmp_abs( A, B ) >= 0 ) - { - MPI_CHK( esp_mpi_sub_abs( X, A, B ) ); - X->s = s; - } - else - { - MPI_CHK( esp_mpi_sub_abs( X, B, A ) ); - X->s = -s; - } - } - else - { - MPI_CHK( esp_mpi_add_abs( X, A, B ) ); - X->s = s; - } - -cleanup: - - return( ret ); -} - -/* - * Signed subtraction: X = A - B - */ -int esp_mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ) -{ - int ret, s = A->s; - - if( A->s * B->s > 0 ) - { - if( esp_mpi_cmp_abs( A, B ) >= 0 ) - { - MPI_CHK( esp_mpi_sub_abs( X, A, B ) ); - X->s = s; - } - else - { - MPI_CHK( esp_mpi_sub_abs( X, B, A ) ); - X->s = -s; - } - } - else - { - MPI_CHK( esp_mpi_add_abs( X, A, B ) ); - X->s = s; - } - -cleanup: - - return( ret ); -} - -/* - * Signed addition: X = A + b - */ -int esp_mpi_add_int( mpi *X, const mpi *A, esp_mpi_sint b ) -{ - mpi _B; - esp_mpi_uint p[1]; - - p[0] = ( b < 0 ) ? -b : b; - _B.s = ( b < 0 ) ? -1 : 1; - _B.n = 1; - _B.p = p; - - return( esp_mpi_add_mpi( X, A, &_B ) ); -} - -/* - * Signed subtraction: X = A - b - */ -int esp_mpi_sub_int( mpi *X, const mpi *A, esp_mpi_sint b ) -{ - mpi _B; - esp_mpi_uint p[1]; - - p[0] = ( b < 0 ) ? -b : b; - _B.s = ( b < 0 ) ? -1 : 1; - _B.n = 1; - _B.p = p; - - return( esp_mpi_sub_mpi( X, A, &_B ) ); -} - -/* - * Helper for mpi multiplication - */ -static void esp_mpi_mul_hlp( size_t i, esp_mpi_uint *s, esp_mpi_uint *d, esp_mpi_uint b ) -{ - -} - -/* - * Baseline multiplication: X = A * B (HAC 14.12) - */ - -static int mul_pram_alloc( mpi *X, const mpi *A, const mpi *B, char **pA, char **pB, char **pX, size_t *bites) -{ - char *sa, *sb, *sx; -// int algn; - int words, bytes; - int abytes, bbytes; - - if (A->n > B->n) - words = A->n; - else - words = B->n; - - bytes = (words / 16 + ((words % 16) ? 1 : 0 )) * 16 * 4 * 2; - - abytes = A->n * 4; - bbytes = B->n * 4; - - sa = malloc(bytes); - if (!sa) { - return -1; - } - - sb = malloc(bytes); - if (!sb) { - free(sa); - return -1; - } - - sx = malloc(bytes); - if (!sx) { - free(sa); - free(sb); - return -1; - } - - memcpy(sa, A->p, abytes); - memset(sa + abytes, 0, bytes - abytes); - - memcpy(sb, B->p, bbytes); - memset(sb + bbytes, 0, bytes - bbytes); - - *pA = sa; - *pB = sb; - - *pX = sx; - - *bites = bytes * 4; - - return 0; -} - -void mul_pram_free(char **pA, char **pB, char **pX) -{ - free(*pA); - *pA = NULL; - - free(*pB); - *pB = NULL; - - free(*pX); - *pX = NULL; -} - -int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ) -{ - int ret = -1; - size_t i, j; - char *s1 = NULL, *s2 = NULL, *dest = NULL; - size_t bites; - - mpi TA, TB; - - esp_mpi_init( &TA ); esp_mpi_init( &TB ); - - if( X == A ) { MPI_CHK( esp_mpi_copy( &TA, A ) ); A = &TA; } - if( X == B ) { MPI_CHK( esp_mpi_copy( &TB, B ) ); B = &TB; } - - for( i = A->n; i > 0; i-- ) - if( A->p[i - 1] != 0 ) - break; - - for( j = B->n; j > 0; j-- ) - if( B->p[j - 1] != 0 ) - break; - - MPI_CHK( esp_mpi_grow( X, i + j ) ); - MPI_CHK( esp_mpi_lset( X, 0 ) ); - - if (mul_pram_alloc(X, A, B, &s1, &s2, &dest, &bites)) { - goto cleanup; - } - - esp_mpi_acquire_hardware(); - if (ets_bigint_mult_prepare((uint32_t *)s1, (uint32_t *)s2, bites)){ - ets_bigint_wait_finish(); - if (ets_bigint_mult_getz((uint32_t *)dest, bites) == true) { - memcpy(X->p, dest, (i + j) * 4); - ret = 0; - } else { - esp_mpi_printf("ets_bigint_mult_getz failed\n"); - } - } else{ - esp_mpi_printf("Baseline multiplication failed\n"); - } - esp_mpi_release_hardware(); - - X->s = A->s * B->s; - - mul_pram_free(&s1, &s2, &dest); - -cleanup: - - esp_mpi_free( &TB ); esp_mpi_free( &TA ); - - return( ret ); -} - -/* - * Baseline multiplication: X = A * b - */ -int esp_mpi_mul_int( mpi *X, const mpi *A, esp_mpi_uint b ) -{ - mpi _B; - esp_mpi_uint p[1]; - - _B.s = 1; - _B.n = 1; - _B.p = p; - p[0] = b; - - return( esp_mpi_mul_mpi( X, A, &_B ) ); -} - -/* - * Unsigned integer divide - double esp_mpi_uint dividend, u1/u0, and - * esp_mpi_uint divisor, d - */ -static esp_mpi_uint int_div_int( esp_mpi_uint u1, - esp_mpi_uint u0, esp_mpi_uint d, esp_mpi_uint *r ) -{ -#if defined(HAVE_UDBL) - t_udbl dividend, quotient; -#else - const esp_mpi_uint radix = (esp_mpi_uint) 1 << biH; - const esp_mpi_uint uint_halfword_mask = ( (esp_mpi_uint) 1 << biH ) - 1; - esp_mpi_uint d0, d1, q0, q1, rAX, r0, quotient; - esp_mpi_uint u0_msw, u0_lsw; - size_t s; -#endif - - /* - * Check for overflow - */ - if( 0 == d || u1 >= d ) - { - if (r != NULL) *r = ~0; - - return ( ~0 ); - } - -#if defined(HAVE_UDBL) - dividend = (t_udbl) u1 << biL; - dividend |= (t_udbl) u0; - quotient = dividend / d; - if( quotient > ( (t_udbl) 1 << biL ) - 1 ) - quotient = ( (t_udbl) 1 << biL ) - 1; - - if( r != NULL ) - *r = (esp_mpi_uint)( dividend - (quotient * d ) ); - - return (esp_mpi_uint) quotient; -#else - - /* - * Algorithm D, Section 4.3.1 - The Art of Computer Programming - * Vol. 2 - Seminumerical Algorithms, Knuth - */ - - /* - * Normalize the divisor, d, and dividend, u0, u1 - */ - s = clz( d ); - d = d << s; - - u1 = u1 << s; - u1 |= ( u0 >> ( biL - s ) ) & ( -(esp_mpi_sint)s >> ( biL - 1 ) ); - u0 = u0 << s; - - d1 = d >> biH; - d0 = d & uint_halfword_mask; - - u0_msw = u0 >> biH; - u0_lsw = u0 & uint_halfword_mask; - - /* - * Find the first quotient and remainder - */ - q1 = u1 / d1; - r0 = u1 - d1 * q1; - - while( q1 >= radix || ( q1 * d0 > radix * r0 + u0_msw ) ) - { - q1 -= 1; - r0 += d1; - - if ( r0 >= radix ) break; - } - - rAX = ( u1 * radix ) + ( u0_msw - q1 * d ); - q0 = rAX / d1; - r0 = rAX - q0 * d1; - - while( q0 >= radix || ( q0 * d0 > radix * r0 + u0_lsw ) ) - { - q0 -= 1; - r0 += d1; - - if ( r0 >= radix ) break; - } - - if (r != NULL) - *r = ( rAX * radix + u0_lsw - q0 * d ) >> s; - - quotient = q1 * radix + q0; - - return quotient; -#endif -} - -/* - * Division by mpi: A = Q * B + R (HAC 14.20) - */ -int esp_mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ) -{ - int ret; - size_t i, n, t, k; - mpi X, Y, Z, T1, T2; - - if( esp_mpi_cmp_int( B, 0 ) == 0 ) - return( ERR_MPI_DIVISION_BY_ZERO ); - - esp_mpi_init( &X ); esp_mpi_init( &Y ); esp_mpi_init( &Z ); - esp_mpi_init( &T1 ); esp_mpi_init( &T2 ); - - if( esp_mpi_cmp_abs( A, B ) < 0 ) - { - if( Q != NULL ) MPI_CHK( esp_mpi_lset( Q, 0 ) ); - if( R != NULL ) MPI_CHK( esp_mpi_copy( R, A ) ); - return( 0 ); - } - - MPI_CHK( esp_mpi_copy( &X, A ) ); - MPI_CHK( esp_mpi_copy( &Y, B ) ); - X.s = Y.s = 1; - - MPI_CHK( esp_mpi_grow( &Z, A->n + 2 ) ); - MPI_CHK( esp_mpi_lset( &Z, 0 ) ); - MPI_CHK( esp_mpi_grow( &T1, 2 ) ); - MPI_CHK( esp_mpi_grow( &T2, 3 ) ); - - k = esp_mpi_bitlen( &Y ) % biL; - if( k < biL - 1 ) - { - k = biL - 1 - k; - MPI_CHK( esp_mpi_shift_l( &X, k ) ); - MPI_CHK( esp_mpi_shift_l( &Y, k ) ); - } - else k = 0; - - n = X.n - 1; - t = Y.n - 1; - MPI_CHK( esp_mpi_shift_l( &Y, biL * ( n - t ) ) ); - - while( esp_mpi_cmp_mpi( &X, &Y ) >= 0 ) - { - Z.p[n - t]++; - MPI_CHK( esp_mpi_sub_mpi( &X, &X, &Y ) ); - } - MPI_CHK( esp_mpi_shift_r( &Y, biL * ( n - t ) ) ); - - for( i = n; i > t ; i-- ) - { - if( X.p[i] >= Y.p[t] ) - Z.p[i - t - 1] = ~0; - else - { - Z.p[i - t - 1] = int_div_int( X.p[i], X.p[i - 1], - Y.p[t], NULL); - } - - Z.p[i - t - 1]++; - do - { - Z.p[i - t - 1]--; - - MPI_CHK( esp_mpi_lset( &T1, 0 ) ); - T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1]; - T1.p[1] = Y.p[t]; - MPI_CHK( esp_mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) ); - - MPI_CHK( esp_mpi_lset( &T2, 0 ) ); - T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2]; - T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1]; - T2.p[2] = X.p[i]; - } - while( esp_mpi_cmp_mpi( &T1, &T2 ) > 0 ); - - MPI_CHK( esp_mpi_mul_int( &T1, &Y, Z.p[i - t - 1] ) ); - MPI_CHK( esp_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); - MPI_CHK( esp_mpi_sub_mpi( &X, &X, &T1 ) ); - - if( esp_mpi_cmp_int( &X, 0 ) < 0 ) - { - MPI_CHK( esp_mpi_copy( &T1, &Y ) ); - MPI_CHK( esp_mpi_shift_l( &T1, biL * ( i - t - 1 ) ) ); - MPI_CHK( esp_mpi_add_mpi( &X, &X, &T1 ) ); - Z.p[i - t - 1]--; - } - } - - if( Q != NULL ) - { - MPI_CHK( esp_mpi_copy( Q, &Z ) ); - Q->s = A->s * B->s; - } - - if( R != NULL ) - { - MPI_CHK( esp_mpi_shift_r( &X, k ) ); - X.s = A->s; - MPI_CHK( esp_mpi_copy( R, &X ) ); - - if( esp_mpi_cmp_int( R, 0 ) == 0 ) - R->s = 1; - } - -cleanup: - - esp_mpi_free( &X ); esp_mpi_free( &Y ); esp_mpi_free( &Z ); - esp_mpi_free( &T1 ); esp_mpi_free( &T2 ); - - return( ret ); -} - -/* - * Division by int: A = Q * b + R - */ -int esp_mpi_div_int( mpi *Q, mpi *R, const mpi *A, esp_mpi_sint b ) -{ - mpi _B; - esp_mpi_uint p[1]; - - p[0] = ( b < 0 ) ? -b : b; - _B.s = ( b < 0 ) ? -1 : 1; - _B.n = 1; - _B.p = p; - - return( esp_mpi_div_mpi( Q, R, A, &_B ) ); -} - -/* - * Modulo: R = A mod B - */ -int esp_mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ) -{ - int ret; - - if( esp_mpi_cmp_int( B, 0 ) < 0 ) - return( ERR_MPI_NEGATIVE_VALUE ); - - MPI_CHK( esp_mpi_div_mpi( NULL, R, A, B ) ); - - while( esp_mpi_cmp_int( R, 0 ) < 0 ) - MPI_CHK( esp_mpi_add_mpi( R, R, B ) ); - - while( esp_mpi_cmp_mpi( R, B ) >= 0 ) - MPI_CHK( esp_mpi_sub_mpi( R, R, B ) ); - -cleanup: - - return( ret ); -} - -/* - * Modulo: r = A mod b - */ -int esp_mpi_mod_int( esp_mpi_uint *r, const mpi *A, esp_mpi_sint b ) -{ - size_t i; - esp_mpi_uint x, y, z; - - if( b == 0 ) - return( ERR_MPI_DIVISION_BY_ZERO ); - - if( b < 0 ) - return( ERR_MPI_NEGATIVE_VALUE ); - - /* - * handle trivial cases - */ - if( b == 1 ) - { - *r = 0; - return( 0 ); - } - - if( b == 2 ) - { - *r = A->p[0] & 1; - return( 0 ); - } - - /* - * general case - */ - for( i = A->n, y = 0; i > 0; i-- ) - { - x = A->p[i - 1]; - y = ( y << biH ) | ( x >> biH ); - z = y / b; - y -= z * b; - - x <<= biH; - y = ( y << biH ) | ( x >> biH ); - z = y / b; - y -= z * b; - } - - /* - * If A is negative, then the current y represents a negative value. - * Flipping it to the positive side. - */ - if( A->s < 0 && y != 0 ) - y = b - y; - - *r = y; - - return( 0 ); -} - -/* - * Fast Montgomery initialization (thanks to Tom St Denis) - */ -static void esp_mpi_montg_init( esp_mpi_uint *mm, const mpi *N ) -{ - esp_mpi_uint x, m0 = N->p[0]; - unsigned int i; - - x = m0; - x += ( ( m0 + 2 ) & 4 ) << 1; - - for( i = biL; i >= 8; i /= 2 ) - x *= ( 2 - ( m0 * x ) ); - - *mm = ~x + 1; -} - -/* - * Montgomery multiplication: A = A * B * R^-1 mod N (HAC 14.36) - */ -static void esp_mpi_montmul( mpi *A, const mpi *B, const mpi *N, esp_mpi_uint mm, - const mpi *T ) -{ - size_t n, m; - esp_mpi_uint *d = NULL; - - memset( T->p, 0, T->n * ciL ); - - d = T->p; - n = N->n; - m = ( B->n < n ) ? B->n : n; - - esp_mpi_acquire_hardware(); - if (ets_bigint_montgomery_mult_prepare(N->p, B->p, d, m, n, false)) { - ets_bigint_wait_finish(); - - ets_bigint_montgomery_mult_getz(A->p, n); - } else{ - esp_mpi_printf("Montgomery multiplication failed\n"); - } - esp_mpi_release_hardware(); - -} - -/* - * Montgomery reduction: A = A * R^-1 mod N - */ -static void esp_mpi_montred( mpi *A, const mpi *N, esp_mpi_uint mm, const mpi *T ) -{ - esp_mpi_uint z = 1; - mpi U; - - U.n = U.s = (int) z; - U.p = &z; - - esp_mpi_montmul( A, &U, N, mm, T ); -} - -/* - * Sliding-window exponentiation: X = A^E mod N (HAC 14.85) - */ -int esp_mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ) -{ - int ret; - size_t wbits, wsize, one = 1; - size_t i, j, nblimbs; - size_t bufsize, nbits; - esp_mpi_uint ei, mm, state; - mpi RR, T, W[ 2 << MPI_WINDOW_SIZE ], Apos; - int neg; - - if( esp_mpi_cmp_int( N, 0 ) < 0 || ( N->p[0] & 1 ) == 0 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - if( esp_mpi_cmp_int( E, 0 ) < 0 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - /* - * Init temps and window size - */ - esp_mpi_montg_init( &mm, N ); - esp_mpi_init( &RR ); esp_mpi_init( &T ); - esp_mpi_init( &Apos ); - memset( W, 0, sizeof( W ) ); - - i = esp_mpi_bitlen( E ); - - wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 : - ( i > 79 ) ? 4 : ( i > 23 ) ? 3 : 1; - - if( wsize > MPI_WINDOW_SIZE ) - wsize = MPI_WINDOW_SIZE; - - j = N->n + 1; - MPI_CHK( esp_mpi_grow( X, j ) ); - MPI_CHK( esp_mpi_grow( &W[1], j ) ); - MPI_CHK( esp_mpi_grow( &T, j * 2 ) ); - - /* - * Compensate for negative A (and correct at the end) - */ - neg = ( A->s == -1 ); - if( neg ) - { - MPI_CHK( esp_mpi_copy( &Apos, A ) ); - Apos.s = 1; - A = &Apos; - } - - /* - * If 1st call, pre-compute R^2 mod N - */ - if( _RR == NULL || _RR->p == NULL ) - { - MPI_CHK( esp_mpi_lset( &RR, 1 ) ); - MPI_CHK( esp_mpi_shift_l( &RR, N->n * 2 * biL ) ); - MPI_CHK( esp_mpi_mod_mpi( &RR, &RR, N ) ); - - if( _RR != NULL ) - memcpy( _RR, &RR, sizeof( mpi ) ); - } - else - memcpy( &RR, _RR, sizeof( mpi ) ); - - /* - * W[1] = A * R^2 * R^-1 mod N = A * R mod N - */ - if( esp_mpi_cmp_mpi( A, N ) >= 0 ) - MPI_CHK( esp_mpi_mod_mpi( &W[1], A, N ) ); - else - MPI_CHK( esp_mpi_copy( &W[1], A ) ); - - esp_mpi_montmul( &W[1], &RR, N, mm, &T ); - - /* - * X = R^2 * R^-1 mod N = R mod N - */ - MPI_CHK( esp_mpi_copy( X, &RR ) ); - esp_mpi_montred( X, N, mm, &T ); - - if( wsize > 1 ) - { - /* - * W[1 << (wsize - 1)] = W[1] ^ (wsize - 1) - */ - j = one << ( wsize - 1 ); - - MPI_CHK( esp_mpi_grow( &W[j], N->n + 1 ) ); - MPI_CHK( esp_mpi_copy( &W[j], &W[1] ) ); - - for( i = 0; i < wsize - 1; i++ ) - esp_mpi_montmul( &W[j], &W[j], N, mm, &T ); - - /* - * W[i] = W[i - 1] * W[1] - */ - for( i = j + 1; i < ( one << wsize ); i++ ) - { - MPI_CHK( esp_mpi_grow( &W[i], N->n + 1 ) ); - MPI_CHK( esp_mpi_copy( &W[i], &W[i - 1] ) ); - - esp_mpi_montmul( &W[i], &W[1], N, mm, &T ); - } - } - - nblimbs = E->n; - bufsize = 0; - nbits = 0; - wbits = 0; - state = 0; - - while( 1 ) - { - if( bufsize == 0 ) - { - if( nblimbs == 0 ) - break; - - nblimbs--; - - bufsize = sizeof( esp_mpi_uint ) << 3; - } - - bufsize--; - - ei = (E->p[nblimbs] >> bufsize) & 1; - - /* - * skip leading 0s - */ - if( ei == 0 && state == 0 ) - continue; - - if( ei == 0 && state == 1 ) - { - /* - * out of window, square X - */ - esp_mpi_montmul( X, X, N, mm, &T ); - continue; - } - - /* - * add ei to current window - */ - state = 2; - - nbits++; - wbits |= ( ei << ( wsize - nbits ) ); - - if( nbits == wsize ) - { - /* - * X = X^wsize R^-1 mod N - */ - for( i = 0; i < wsize; i++ ) - esp_mpi_montmul( X, X, N, mm, &T ); - - /* - * X = X * W[wbits] R^-1 mod N - */ - esp_mpi_montmul( X, &W[wbits], N, mm, &T ); - - state--; - nbits = 0; - wbits = 0; - } - } - - /* - * process the remaining bits - */ - for( i = 0; i < nbits; i++ ) - { - esp_mpi_montmul( X, X, N, mm, &T ); - - wbits <<= 1; - - if( ( wbits & ( one << wsize ) ) != 0 ) - esp_mpi_montmul( X, &W[1], N, mm, &T ); - } - - /* - * X = A^E * R * R^-1 mod N = A^E mod N - */ - esp_mpi_montred( X, N, mm, &T ); - - if( neg ) - { - X->s = -1; - MPI_CHK( esp_mpi_add_mpi( X, N, X ) ); - } - -cleanup: - - for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ ) - esp_mpi_free( &W[i] ); - - esp_mpi_free( &W[1] ); esp_mpi_free( &T ); esp_mpi_free( &Apos ); - - if( _RR == NULL || _RR->p == NULL ) - esp_mpi_free( &RR ); - - return( ret ); -} - -/* - * Greatest common divisor: G = gcd(A, B) (HAC 14.54) - */ -int esp_mpi_gcd( mpi *G, const mpi *A, const mpi *B ) -{ - int ret; - size_t lz, lzt; - mpi TG, TA, TB; - - esp_mpi_init( &TG ); esp_mpi_init( &TA ); esp_mpi_init( &TB ); - - MPI_CHK( esp_mpi_copy( &TA, A ) ); - MPI_CHK( esp_mpi_copy( &TB, B ) ); - - lz = esp_mpi_lsb( &TA ); - lzt = esp_mpi_lsb( &TB ); - - if( lzt < lz ) - lz = lzt; - - MPI_CHK( esp_mpi_shift_r( &TA, lz ) ); - MPI_CHK( esp_mpi_shift_r( &TB, lz ) ); - - TA.s = TB.s = 1; - - while( esp_mpi_cmp_int( &TA, 0 ) != 0 ) - { - MPI_CHK( esp_mpi_shift_r( &TA, esp_mpi_lsb( &TA ) ) ); - MPI_CHK( esp_mpi_shift_r( &TB, esp_mpi_lsb( &TB ) ) ); - - if( esp_mpi_cmp_mpi( &TA, &TB ) >= 0 ) - { - MPI_CHK( esp_mpi_sub_abs( &TA, &TA, &TB ) ); - MPI_CHK( esp_mpi_shift_r( &TA, 1 ) ); - } - else - { - MPI_CHK( esp_mpi_sub_abs( &TB, &TB, &TA ) ); - MPI_CHK( esp_mpi_shift_r( &TB, 1 ) ); - } - } - - MPI_CHK( esp_mpi_shift_l( &TB, lz ) ); - MPI_CHK( esp_mpi_copy( G, &TB ) ); - -cleanup: - - esp_mpi_free( &TG ); esp_mpi_free( &TA ); esp_mpi_free( &TB ); - - return( ret ); -} - -/* - * Fill X with size bytes of random. - * - * Use a temporary bytes representation to make sure the result is the same - * regardless of the platform endianness (useful when f_rng is actually - * deterministic, eg for tests). - */ -int esp_mpi_fill_random( mpi *X, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ) -{ - int ret; - unsigned char buf[MPI_MAX_SIZE]; - - if( size > MPI_MAX_SIZE ) - return( ERR_MPI_BAD_INPUT_DATA ); - - MPI_CHK( f_rng( p_rng, buf, size ) ); - MPI_CHK( esp_mpi_read_binary( X, buf, size ) ); - -cleanup: - return( ret ); -} - -/* - * Modular inverse: X = A^-1 mod N (HAC 14.61 / 14.64) - */ -int esp_mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ) -{ - int ret; - mpi G, TA, TU, U1, U2, TB, TV, V1, V2; - - if( esp_mpi_cmp_int( N, 0 ) <= 0 ) - return( ERR_MPI_BAD_INPUT_DATA ); - - esp_mpi_init( &TA ); esp_mpi_init( &TU ); esp_mpi_init( &U1 ); esp_mpi_init( &U2 ); - esp_mpi_init( &G ); esp_mpi_init( &TB ); esp_mpi_init( &TV ); - esp_mpi_init( &V1 ); esp_mpi_init( &V2 ); - - MPI_CHK( esp_mpi_gcd( &G, A, N ) ); - - if( esp_mpi_cmp_int( &G, 1 ) != 0 ) - { - ret = ERR_MPI_NOT_ACCEPTABLE; - goto cleanup; - } - - MPI_CHK( esp_mpi_mod_mpi( &TA, A, N ) ); - MPI_CHK( esp_mpi_copy( &TU, &TA ) ); - MPI_CHK( esp_mpi_copy( &TB, N ) ); - MPI_CHK( esp_mpi_copy( &TV, N ) ); - - MPI_CHK( esp_mpi_lset( &U1, 1 ) ); - MPI_CHK( esp_mpi_lset( &U2, 0 ) ); - MPI_CHK( esp_mpi_lset( &V1, 0 ) ); - MPI_CHK( esp_mpi_lset( &V2, 1 ) ); - - do - { - while( ( TU.p[0] & 1 ) == 0 ) - { - MPI_CHK( esp_mpi_shift_r( &TU, 1 ) ); - - if( ( U1.p[0] & 1 ) != 0 || ( U2.p[0] & 1 ) != 0 ) - { - MPI_CHK( esp_mpi_add_mpi( &U1, &U1, &TB ) ); - MPI_CHK( esp_mpi_sub_mpi( &U2, &U2, &TA ) ); - } - - MPI_CHK( esp_mpi_shift_r( &U1, 1 ) ); - MPI_CHK( esp_mpi_shift_r( &U2, 1 ) ); - } - - while( ( TV.p[0] & 1 ) == 0 ) - { - MPI_CHK( esp_mpi_shift_r( &TV, 1 ) ); - - if( ( V1.p[0] & 1 ) != 0 || ( V2.p[0] & 1 ) != 0 ) - { - MPI_CHK( esp_mpi_add_mpi( &V1, &V1, &TB ) ); - MPI_CHK( esp_mpi_sub_mpi( &V2, &V2, &TA ) ); - } - - MPI_CHK( esp_mpi_shift_r( &V1, 1 ) ); - MPI_CHK( esp_mpi_shift_r( &V2, 1 ) ); - } - - if( esp_mpi_cmp_mpi( &TU, &TV ) >= 0 ) - { - MPI_CHK( esp_mpi_sub_mpi( &TU, &TU, &TV ) ); - MPI_CHK( esp_mpi_sub_mpi( &U1, &U1, &V1 ) ); - MPI_CHK( esp_mpi_sub_mpi( &U2, &U2, &V2 ) ); - } - else - { - MPI_CHK( esp_mpi_sub_mpi( &TV, &TV, &TU ) ); - MPI_CHK( esp_mpi_sub_mpi( &V1, &V1, &U1 ) ); - MPI_CHK( esp_mpi_sub_mpi( &V2, &V2, &U2 ) ); - } - } - while( esp_mpi_cmp_int( &TU, 0 ) != 0 ); - - while( esp_mpi_cmp_int( &V1, 0 ) < 0 ) - MPI_CHK( esp_mpi_add_mpi( &V1, &V1, N ) ); - - while( esp_mpi_cmp_mpi( &V1, N ) >= 0 ) - MPI_CHK( esp_mpi_sub_mpi( &V1, &V1, N ) ); - - MPI_CHK( esp_mpi_copy( X, &V1 ) ); - -cleanup: - - esp_mpi_free( &TA ); esp_mpi_free( &TU ); esp_mpi_free( &U1 ); esp_mpi_free( &U2 ); - esp_mpi_free( &G ); esp_mpi_free( &TB ); esp_mpi_free( &TV ); - esp_mpi_free( &V1 ); esp_mpi_free( &V2 ); - - return( ret ); -} - -static const int small_prime[] = -{ - 3, 5, 7, 11, 13, 17, 19, 23, - 29, 31, 37, 41, 43, 47, 53, 59, - 61, 67, 71, 73, 79, 83, 89, 97, - 101, 103, 107, 109, 113, 127, 131, 137, - 139, 149, 151, 157, 163, 167, 173, 179, - 181, 191, 193, 197, 199, 211, 223, 227, - 229, 233, 239, 241, 251, 257, 263, 269, - 271, 277, 281, 283, 293, 307, 311, 313, - 317, 331, 337, 347, 349, 353, 359, 367, - 373, 379, 383, 389, 397, 401, 409, 419, - 421, 431, 433, 439, 443, 449, 457, 461, - 463, 467, 479, 487, 491, 499, 503, 509, - 521, 523, 541, 547, 557, 563, 569, 571, - 577, 587, 593, 599, 601, 607, 613, 617, - 619, 631, 641, 643, 647, 653, 659, 661, - 673, 677, 683, 691, 701, 709, 719, 727, - 733, 739, 743, 751, 757, 761, 769, 773, - 787, 797, 809, 811, 821, 823, 827, 829, - 839, 853, 857, 859, 863, 877, 881, 883, - 887, 907, 911, 919, 929, 937, 941, 947, - 953, 967, 971, 977, 983, 991, 997, -103 -}; - -/* - * Small divisors test (X must be positive) - * - * Return values: - * 0: no small factor (possible prime, more tests needed) - * 1: certain prime - * ERR_MPI_NOT_ACCEPTABLE: certain non-prime - * other negative: error - */ -static int esp_mpi_check_small_factors( const mpi *X ) -{ - int ret = 0; - size_t i; - esp_mpi_uint r; - - if( ( X->p[0] & 1 ) == 0 ) - return( ERR_MPI_NOT_ACCEPTABLE ); - - for( i = 0; small_prime[i] > 0; i++ ) - { - if( esp_mpi_cmp_int( X, small_prime[i] ) <= 0 ) - return( 1 ); - - MPI_CHK( esp_mpi_mod_int( &r, X, small_prime[i] ) ); - - if( r == 0 ) - return( ERR_MPI_NOT_ACCEPTABLE ); - } - -cleanup: - return( ret ); -} - -/* - * Miller-Rabin pseudo-primality test (HAC 4.24) - */ -static int esp_mpi_miller_rabin( const mpi *X, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ) -{ - int ret, count; - size_t i, j, k, n, s; - mpi W, R, T, A, RR; - - esp_mpi_init( &W ); esp_mpi_init( &R ); esp_mpi_init( &T ); esp_mpi_init( &A ); - esp_mpi_init( &RR ); - - /* - * W = |X| - 1 - * R = W >> lsb( W ) - */ - MPI_CHK( esp_mpi_sub_int( &W, X, 1 ) ); - s = esp_mpi_lsb( &W ); - MPI_CHK( esp_mpi_copy( &R, &W ) ); - MPI_CHK( esp_mpi_shift_r( &R, s ) ); - - i = esp_mpi_bitlen( X ); - /* - * HAC, table 4.4 - */ - n = ( ( i >= 1300 ) ? 2 : ( i >= 850 ) ? 3 : - ( i >= 650 ) ? 4 : ( i >= 350 ) ? 8 : - ( i >= 250 ) ? 12 : ( i >= 150 ) ? 18 : 27 ); - - for( i = 0; i < n; i++ ) - { - /* - * pick a random A, 1 < A < |X| - 1 - */ - MPI_CHK( esp_mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); - - if( esp_mpi_cmp_mpi( &A, &W ) >= 0 ) - { - j = esp_mpi_bitlen( &A ) - esp_mpi_bitlen( &W ); - MPI_CHK( esp_mpi_shift_r( &A, j + 1 ) ); - } - A.p[0] |= 3; - - count = 0; - do { - MPI_CHK( esp_mpi_fill_random( &A, X->n * ciL, f_rng, p_rng ) ); - - j = esp_mpi_bitlen( &A ); - k = esp_mpi_bitlen( &W ); - if (j > k) { - MPI_CHK( esp_mpi_shift_r( &A, j - k ) ); - } - - if (count++ > 30) { - return ERR_MPI_NOT_ACCEPTABLE; - } - - } while ( esp_mpi_cmp_mpi( &A, &W ) >= 0 || - esp_mpi_cmp_int( &A, 1 ) <= 0 ); - - /* - * A = A^R mod |X| - */ - MPI_CHK( esp_mpi_exp_mod( &A, &A, &R, X, &RR ) ); - - if( esp_mpi_cmp_mpi( &A, &W ) == 0 || - esp_mpi_cmp_int( &A, 1 ) == 0 ) - continue; - - j = 1; - while( j < s && esp_mpi_cmp_mpi( &A, &W ) != 0 ) - { - /* - * A = A * A mod |X| - */ - MPI_CHK( esp_mpi_mul_mpi( &T, &A, &A ) ); - MPI_CHK( esp_mpi_mod_mpi( &A, &T, X ) ); - - if( esp_mpi_cmp_int( &A, 1 ) == 0 ) - break; - - j++; - } - - /* - * not prime if A != |X| - 1 or A == 1 - */ - if( esp_mpi_cmp_mpi( &A, &W ) != 0 || - esp_mpi_cmp_int( &A, 1 ) == 0 ) - { - ret = ERR_MPI_NOT_ACCEPTABLE; - break; - } - } - -cleanup: - esp_mpi_free( &W ); esp_mpi_free( &R ); esp_mpi_free( &T ); esp_mpi_free( &A ); - esp_mpi_free( &RR ); - - return( ret ); -} - -/* - * Pseudo-primality test: small factors, then Miller-Rabin - */ -int esp_mpi_is_prime( const mpi *X, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ) -{ - int ret; - mpi XX; - - XX.s = 1; - XX.n = X->n; - XX.p = X->p; - - if( esp_mpi_cmp_int( &XX, 0 ) == 0 || - esp_mpi_cmp_int( &XX, 1 ) == 0 ) - return( ERR_MPI_NOT_ACCEPTABLE ); - - if( esp_mpi_cmp_int( &XX, 2 ) == 0 ) - return( 0 ); - - if( ( ret = esp_mpi_check_small_factors( &XX ) ) != 0 ) - { - if( ret == 1 ) - return( 0 ); - - return( ret ); - } - - return( esp_mpi_miller_rabin( &XX, f_rng, p_rng ) ); -} - -/* - * Prime number generation - */ -int esp_mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ) -{ - int ret; - size_t k, n; - esp_mpi_uint r; - mpi Y; - - if( nbits < 3 || nbits > MPI_MAX_BITS ) - return( ERR_MPI_BAD_INPUT_DATA ); - - esp_mpi_init( &Y ); - - n = BITS_TO_LIMBS( nbits ); - - MPI_CHK( esp_mpi_fill_random( X, n * ciL, f_rng, p_rng ) ); - - k = esp_mpi_bitlen( X ); - if( k > nbits ) MPI_CHK( esp_mpi_shift_r( X, k - nbits + 1 ) ); - - esp_mpi_set_bit( X, nbits-1, 1 ); - - X->p[0] |= 1; - - if( dh_flag == 0 ) - { - while( ( ret = esp_mpi_is_prime( X, f_rng, p_rng ) ) != 0 ) - { - if( ret != ERR_MPI_NOT_ACCEPTABLE ) - goto cleanup; - - MPI_CHK( esp_mpi_add_int( X, X, 2 ) ); - } - } - else - { - /* - * An necessary condition for Y and X = 2Y + 1 to be prime - * is X = 2 mod 3 (which is equivalent to Y = 2 mod 3). - * Make sure it is satisfied, while keeping X = 3 mod 4 - */ - - X->p[0] |= 2; - - MPI_CHK( esp_mpi_mod_int( &r, X, 3 ) ); - if( r == 0 ) - MPI_CHK( esp_mpi_add_int( X, X, 8 ) ); - else if( r == 1 ) - MPI_CHK( esp_mpi_add_int( X, X, 4 ) ); - - /* Set Y = (X-1) / 2, which is X / 2 because X is odd */ - MPI_CHK( esp_mpi_copy( &Y, X ) ); - MPI_CHK( esp_mpi_shift_r( &Y, 1 ) ); - - while( 1 ) - { - /* - * First, check small factors for X and Y - * before doing Miller-Rabin on any of them - */ - if( ( ret = esp_mpi_check_small_factors( X ) ) == 0 && - ( ret = esp_mpi_check_small_factors( &Y ) ) == 0 && - ( ret = esp_mpi_miller_rabin( X, f_rng, p_rng ) ) == 0 && - ( ret = esp_mpi_miller_rabin( &Y, f_rng, p_rng ) ) == 0 ) - { - break; - } - - if( ret != ERR_MPI_NOT_ACCEPTABLE ) - goto cleanup; - - /* - * Next candidates. We want to preserve Y = (X-1) / 2 and - * Y = 1 mod 2 and Y = 2 mod 3 (eq X = 3 mod 4 and X = 2 mod 3) - * so up Y by 6 and X by 12. - */ - MPI_CHK( esp_mpi_add_int( X, X, 12 ) ); - MPI_CHK( esp_mpi_add_int( &Y, &Y, 6 ) ); - } - } - -cleanup: - - esp_mpi_free( &Y ); - - return( ret ); -} - diff --git a/components/esp32/include/hwcrypto/bignum.h b/components/esp32/include/hwcrypto/bignum.h deleted file mode 100644 index dbcef43de..000000000 --- a/components/esp32/include/hwcrypto/bignum.h +++ /dev/null @@ -1,727 +0,0 @@ -/** - * \file bignum_alt.h - * - * \brief Multi-precision integer library, ESP32 hardware accelerated version - * Based on mbedTLS version. - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#ifndef _ESP_BIGNUM_H -#define _ESP_BIGNUM_H - -#include "esp_types.h" - - -#define MPI_DEBUG_ALT - - -#define ERR_MPI_FILE_IO_ERROR -0x0002 /**< An error occurred while reading from or writing to a file. */ -#define ERR_MPI_BAD_INPUT_DATA -0x0004 /**< Bad input parameters to function. */ -#define ERR_MPI_INVALID_CHARACTER -0x0006 /**< There is an invalid character in the digit string. */ -#define ERR_MPI_BUFFER_TOO_SMALL -0x0008 /**< The buffer is too small to write to. */ -#define ERR_MPI_NEGATIVE_VALUE -0x000A /**< The input arguments are negative or result in illegal output. */ -#define ERR_MPI_DIVISION_BY_ZERO -0x000C /**< The input argument for division is zero, which is not allowed. */ -#define ERR_MPI_NOT_ACCEPTABLE -0x000E /**< The input arguments are not acceptable. */ -#define ERR_MPI_ALLOC_FAILED -0x0010 /**< Memory allocation failed. */ - -#define MPI_CHK(f) do { if( ( ret = f ) != 0 ) goto cleanup; } while( 0 ) -#if defined(MPI_DEBUG_ALT) -#define esp_mpi_printf ets_printf -#else -#define esp_mpi_printf -#endif -/* - * Maximum size MPIs are allowed to grow to in number of limbs. - */ -#define MPI_MAX_LIMBS 10000 - -#if !defined(MPI_WINDOW_SIZE) -/* - * Maximum window size used for modular exponentiation. Default: 6 - * Minimum value: 1. Maximum value: 6. - * - * Result is an array of ( 2 << MPI_WINDOW_SIZE ) MPIs used - * for the sliding window calculation. (So 64 by default) - * - * Reduction in size, reduces speed. - */ -#define MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ -#endif /* !MPI_WINDOW_SIZE */ - -#if !defined(MPI_MAX_SIZE) -/* - * Maximum size of MPIs allowed in bits and bytes for user-MPIs. - * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits ) - * - * Note: Calculations can results temporarily in larger MPIs. So the number - * of limbs required (MPI_MAX_LIMBS) is higher. - */ -#define MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ -#endif /* !MPI_MAX_SIZE */ - -#define MPI_MAX_BITS ( 8 * MPI_MAX_SIZE ) /**< Maximum number of bits for usable MPIs. */ - -/* - * When reading from files with esp_mpi_read_file() and writing to files with - * esp_mpi_write_file() the buffer should have space - * for a (short) label, the MPI (in the provided radix), the newline - * characters and the '\0'. - * - * By default we assume at least a 10 char label, a minimum radix of 10 - * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars). - * Autosized at compile time for at least a 10 char label, a minimum radix - * of 10 (decimal) for a number of MPI_MAX_BITS size. - * - * This used to be statically sized to 1250 for a maximum of 4096 bit - * numbers (1234 decimal chars). - * - * Calculate using the formula: - * MPI_RW_BUFFER_SIZE = ceil(MPI_MAX_BITS / ln(10) * ln(2)) + - * LabelSize + 6 - */ -#define MPI_MAX_BITS_SCALE100 ( 100 * MPI_MAX_BITS ) -#define LN_2_DIV_LN_10_SCALE100 332 -#define MPI_RW_BUFFER_SIZE ( ((MPI_MAX_BITS_SCALE100 + LN_2_DIV_LN_10_SCALE100 - 1) / LN_2_DIV_LN_10_SCALE100) + 10 + 6 ) - -/* - * Define the base integer type, architecture-wise. - * - * 32-bit integers can be forced on 64-bit arches (eg. for testing purposes) - * by defining HAVE_INT32 and undefining HAVE_ASM - */ -#if ( ! defined(HAVE_INT32) && \ - defined(_MSC_VER) && defined(_M_AMD64) ) - #define HAVE_INT64 - typedef int64_t esp_mpi_sint; - typedef uint64_t esp_mpi_uint; -#else - #if ( ! defined(HAVE_INT32) && \ - defined(__GNUC__) && ( \ - defined(__amd64__) || defined(__x86_64__) || \ - defined(__ppc64__) || defined(__powerpc64__) || \ - defined(__ia64__) || defined(__alpha__) || \ - (defined(__sparc__) && defined(__arch64__)) || \ - defined(__s390x__) || defined(__mips64) ) ) - #define HAVE_INT64 - typedef int64_t esp_mpi_sint; - typedef uint64_t esp_mpi_uint; - /* t_udbl defined as 128-bit unsigned int */ - typedef unsigned int t_udbl __attribute__((mode(TI))); - #define HAVE_UDBL - #else - #define HAVE_INT32 - typedef int32_t esp_mpi_sint; - typedef uint32_t esp_mpi_uint; - typedef uint64_t t_udbl; - #define HAVE_UDBL - #endif /* !HAVE_INT32 && __GNUC__ && 64-bit platform */ -#endif /* !HAVE_INT32 && _MSC_VER && _M_AMD64 */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief MPI structure - */ -typedef struct -{ - int s; /*!< integer sign */ - size_t n; /*!< total # of limbs */ - esp_mpi_uint *p; /*!< pointer to limbs */ -}mpi, MPI_CTX; - -/** - * \brief Lock access to MPI hardware unit - * - * MPI hardware unit can only be used by one - * consumer at a time. - * - * esp_mpi_xxx API calls automatically manage locking & unlocking of - * hardware, this function is only needed if you want to call - * ets_bigint_xxx functions directly. - */ -void esp_mpi_acquire_hardware( void ); - -/** - * \brief Unlock access to MPI hardware unit - * - * esp_mpi_xxx API calls automatically manage locking & unlocking of - * hardware, this function is only needed if you want to call - * ets_bigint_xxx functions directly. - */ -void esp_mpi_release_hardware( void ); - -/** - * \brief Initialize one MPI (make internal references valid) - * This just makes it ready to be set or freed, - * but does not define a value for the MPI. - * - * \param X One MPI to initialize. - */ -void esp_mpi_init( mpi *X ); - -/** - * \brief Unallocate one MPI - * - * \param X One MPI to unallocate. - */ -void esp_mpi_free( mpi *X ); - -/** - * \brief Enlarge to the specified number of limbs - * - * \param X MPI to grow - * \param nblimbs The target number of limbs - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_grow( mpi *X, size_t nblimbs ); - -/** - * \brief Resize down, keeping at least the specified number of limbs - * - * \param X MPI to shrink - * \param nblimbs The minimum number of limbs to keep - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_shrink( mpi *X, size_t nblimbs ); - -/** - * \brief Copy the contents of Y into X - * - * \param X Destination MPI - * \param Y Source MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_copy( mpi *X, const mpi *Y ); - -/** - * \brief Swap the contents of X and Y - * - * \param X First MPI value - * \param Y Second MPI value - */ -void esp_mpi_swap( mpi *X, mpi *Y ); - -/** - * \brief Safe conditional assignement X = Y if assign is 1 - * - * \param X MPI to conditionally assign to - * \param Y Value to be assigned - * \param assign 1: perform the assignment, 0: keep X's original value - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * - * \note This function is equivalent to - * if( assign ) esp_mpi_copy( X, Y ); - * except that it avoids leaking any information about whether - * the assignment was done or not (the above code may leak - * information through branch prediction and/or memory access - * patterns analysis). - */ -int esp_mpi_safe_cond_assign( mpi *X, const mpi *Y, unsigned char assign ); - -/** - * \brief Safe conditional swap X <-> Y if swap is 1 - * - * \param X First mpi value - * \param Y Second mpi value - * \param assign 1: perform the swap, 0: keep X and Y's original values - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * - * \note This function is equivalent to - * if( assign ) esp_mpi_swap( X, Y ); - * except that it avoids leaking any information about whether - * the assignment was done or not (the above code may leak - * information through branch prediction and/or memory access - * patterns analysis). - */ -int esp_mpi_safe_cond_swap( mpi *X, mpi *Y, unsigned char assign ); - -/** - * \brief Set value from integer - * - * \param X MPI to set - * \param z Value to use - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_lset( mpi *X, esp_mpi_sint z ); - -/** - * \brief Get a specific bit from X - * - * \param X MPI to use - * \param pos Zero-based index of the bit in X - * - * \return Either a 0 or a 1 - */ -int esp_mpi_get_bit( const mpi *X, size_t pos ); - -/** - * \brief Set a bit of X to a specific value of 0 or 1 - * - * \note Will grow X if necessary to set a bit to 1 in a not yet - * existing limb. Will not grow if bit should be set to 0 - * - * \param X MPI to use - * \param pos Zero-based index of the bit in X - * \param val The value to set the bit to (0 or 1) - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_BAD_INPUT_DATA if val is not 0 or 1 - */ -int esp_mpi_set_bit( mpi *X, size_t pos, unsigned char val ); - -/** - * \brief Return the number of zero-bits before the least significant - * '1' bit - * - * Note: Thus also the zero-based index of the least significant '1' bit - * - * \param X MPI to use - */ -size_t esp_mpi_lsb( const mpi *X ); - -/** - * \brief Return the number of bits up to and including the most - * significant '1' bit' - * - * Note: Thus also the one-based index of the most significant '1' bit - * - * \param X MPI to use - */ -size_t esp_mpi_bitlen( const mpi *X ); - -/** - * \brief Return the total size in bytes - * - * \param X MPI to use - */ -size_t esp_mpi_size( const mpi *X ); - -/** - * \brief Import from an ASCII string - * - * \param X Destination MPI - * \param radix Input numeric base - * \param s Null-terminated string buffer - * - * \return 0 if successful, or a ERR_MPI_XXX error code - */ -int esp_mpi_read_string( mpi *X, int radix, const char *s ); - -/** - * \brief Export into an ASCII string - * - * \param X Source MPI - * \param radix Output numeric base - * \param buf Buffer to write the string to - * \param buflen Length of buf - * \param olen Length of the string written, including final NUL byte - * - * \return 0 if successful, or a ERR_MPI_XXX error code. - * *olen is always updated to reflect the amount - * of data that has (or would have) been written. - * - * \note Call this function with buflen = 0 to obtain the - * minimum required buffer size in *olen. - */ -int esp_mpi_write_string( const mpi *X, int radix, - char *buf, size_t buflen, size_t *olen ); - -#if defined(FS_IO) -/** - * \brief Read X from an opened file - * - * \param X Destination MPI - * \param radix Input numeric base - * \param fin Input file handle - * - * \return 0 if successful, ERR_MPI_BUFFER_TOO_SMALL if - * the file read buffer is too small or a - * ERR_MPI_XXX error code - */ -int esp_mpi_read_file( mpi *X, int radix, FILE *fin ); - -/** - * \brief Write X into an opened file, or stdout if fout is NULL - * - * \param p Prefix, can be NULL - * \param X Source MPI - * \param radix Output numeric base - * \param fout Output file handle (can be NULL) - * - * \return 0 if successful, or a ERR_MPI_XXX error code - * - * \note Set fout == NULL to print X on the console. - */ -int esp_mpi_write_file( const char *p, const mpi *X, int radix, FILE *fout ); -#endif /* FS_IO */ - -/** - * \brief Import X from unsigned binary data, big endian - * - * \param X Destination MPI - * \param buf Input buffer - * \param buflen Input buffer size - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen ); - -/** - * \brief Export X into unsigned binary data, big endian. - * Always fills the whole buffer, which will start with zeros - * if the number is smaller. - * - * \param X Source MPI - * \param buf Output buffer - * \param buflen Output buffer size - * - * \return 0 if successful, - * ERR_MPI_BUFFER_TOO_SMALL if buf isn't large enough - */ -int esp_mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen ); - -/** - * \brief Left-shift: X <<= count - * - * \param X MPI to shift - * \param count Amount to shift - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_shift_l( mpi *X, size_t count ); - -/** - * \brief Right-shift: X >>= count - * - * \param X MPI to shift - * \param count Amount to shift - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_shift_r( mpi *X, size_t count ); - -/** - * \brief Compare unsigned values - * - * \param X Left-hand MPI - * \param Y Right-hand MPI - * - * \return 1 if |X| is greater than |Y|, - * -1 if |X| is lesser than |Y| or - * 0 if |X| is equal to |Y| - */ -int esp_mpi_cmp_abs( const mpi *X, const mpi *Y ); - -/** - * \brief Compare signed values - * - * \param X Left-hand MPI - * \param Y Right-hand MPI - * - * \return 1 if X is greater than Y, - * -1 if X is lesser than Y or - * 0 if X is equal to Y - */ -int esp_mpi_cmp_mpi( const mpi *X, const mpi *Y ); - -/** - * \brief Compare signed values - * - * \param X Left-hand MPI - * \param z The integer value to compare to - * - * \return 1 if X is greater than z, - * -1 if X is lesser than z or - * 0 if X is equal to z - */ -int esp_mpi_cmp_int( const mpi *X, esp_mpi_sint z ); - -/** - * \brief Unsigned addition: X = |A| + |B| - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_add_abs( mpi *X, const mpi *A, const mpi *B ); - -/** - * \brief Unsigned subtraction: X = |A| - |B| - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_NEGATIVE_VALUE if B is greater than A - */ -int esp_mpi_sub_abs( mpi *X, const mpi *A, const mpi *B ); - -/** - * \brief Signed addition: X = A + B - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_add_mpi( mpi *X, const mpi *A, const mpi *B ); - -/** - * \brief Signed subtraction: X = A - B - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B ); - -/** - * \brief Signed addition: X = A + b - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param b The integer value to add - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_add_int( mpi *X, const mpi *A, esp_mpi_sint b ); - -/** - * \brief Signed subtraction: X = A - b - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param b The integer value to subtract - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_sub_int( mpi *X, const mpi *A, esp_mpi_sint b ); - -/** - * \brief Baseline multiplication: X = A * B - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B ); - -/** - * \brief Baseline multiplication: X = A * b - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param b The unsigned integer value to multiply with - * - * \note b is unsigned - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_mul_int( mpi *X, const mpi *A, esp_mpi_uint b ); - -/** - * \brief Division by mpi: A = Q * B + R - * - * \param Q Destination MPI for the quotient - * \param R Destination MPI for the rest value - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_DIVISION_BY_ZERO if B == 0 - * - * \note Either Q or R can be NULL. - */ -int esp_mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B ); - -/** - * \brief Division by int: A = Q * b + R - * - * \param Q Destination MPI for the quotient - * \param R Destination MPI for the rest value - * \param A Left-hand MPI - * \param b Integer to divide by - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_DIVISION_BY_ZERO if b == 0 - * - * \note Either Q or R can be NULL. - */ -int esp_mpi_div_int( mpi *Q, mpi *R, const mpi *A, esp_mpi_sint b ); - -/** - * \brief Modulo: R = A mod B - * - * \param R Destination MPI for the rest value - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_DIVISION_BY_ZERO if B == 0, - * ERR_MPI_NEGATIVE_VALUE if B < 0 - */ -int esp_mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B ); - -/** - * \brief Modulo: r = A mod b - * - * \param r Destination esp_mpi_uint - * \param A Left-hand MPI - * \param b Integer to divide by - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_DIVISION_BY_ZERO if b == 0, - * ERR_MPI_NEGATIVE_VALUE if b < 0 - */ -int esp_mpi_mod_int( esp_mpi_uint *r, const mpi *A, esp_mpi_sint b ); - -/** - * \brief Sliding-window exponentiation: X = A^E mod N - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param E Exponent MPI - * \param N Modular MPI - * \param _RR Speed-up MPI used for recalculations - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_BAD_INPUT_DATA if N is negative or even or - * if E is negative - * - * \note _RR is used to avoid re-computing R*R mod N across - * multiple calls, which speeds up things a bit. It can - * be set to NULL if the extra performance is unneeded. - */ -int esp_mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR ); - -/** - * \brief Fill an MPI X with size bytes of random - * - * \param X Destination MPI - * \param size Size in bytes - * \param f_rng RNG function - * \param p_rng RNG parameter - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_fill_random( mpi *X, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ); - -/** - * \brief Greatest common divisor: G = gcd(A, B) - * - * \param G Destination MPI - * \param A Left-hand MPI - * \param B Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed - */ -int esp_mpi_gcd( mpi *G, const mpi *A, const mpi *B ); - -/** - * \brief Modular inverse: X = A^-1 mod N - * - * \param X Destination MPI - * \param A Left-hand MPI - * \param N Right-hand MPI - * - * \return 0 if successful, - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_BAD_INPUT_DATA if N is negative or nil - ERR_MPI_NOT_ACCEPTABLE if A has no inverse mod N - */ -int esp_mpi_inv_mod( mpi *X, const mpi *A, const mpi *N ); - -/** - * \brief Miller-Rabin primality test - * - * \param X MPI to check - * \param f_rng RNG function - * \param p_rng RNG parameter - * - * \return 0 if successful (probably prime), - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_NOT_ACCEPTABLE if X is not prime - */ -int esp_mpi_is_prime( const mpi *X, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ); - -/** - * \brief Prime number generation - * - * \param X Destination MPI - * \param nbits Required size of X in bits - * ( 3 <= nbits <= MPI_MAX_BITS ) - * \param dh_flag If 1, then (X-1)/2 will be prime too - * \param f_rng RNG function - * \param p_rng RNG parameter - * - * \return 0 if successful (probably prime), - * ERR_MPI_ALLOC_FAILED if memory allocation failed, - * ERR_MPI_BAD_INPUT_DATA if nbits is < 3 - */ -int esp_mpi_gen_prime( mpi *X, size_t nbits, int dh_flag, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ); - - -#endif - diff --git a/components/mbedtls/Makefile b/components/mbedtls/Makefile index e44ce2b53..cb3ee2c56 100644 --- a/components/mbedtls/Makefile +++ b/components/mbedtls/Makefile @@ -1,5 +1,8 @@ # # Component Makefile +# + +COMPONENT_ADD_INCLUDEDIRS := port/include include COMPONENT_SRCDIRS := library port diff --git a/components/mbedtls/include/mbedtls/esp_config.h b/components/mbedtls/include/mbedtls/esp_config.h index 0bf7e14d1..6d52294b7 100644 --- a/components/mbedtls/include/mbedtls/esp_config.h +++ b/components/mbedtls/include/mbedtls/esp_config.h @@ -225,7 +225,6 @@ * Uncomment a macro to enable alternate implementation of the corresponding * module. */ -//#define MBEDTLS_AES_ALT //#define MBEDTLS_ARC4_ALT //#define MBEDTLS_BLOWFISH_ALT //#define MBEDTLS_CAMELLIA_ALT @@ -235,11 +234,22 @@ //#define MBEDTLS_MD4_ALT //#define MBEDTLS_MD5_ALT //#define MBEDTLS_RIPEMD160_ALT -//#define MBEDTLS_SHA1_ALT -//#define MBEDTLS_SHA256_ALT -//#define MBEDTLS_SHA512_ALT -//#define MBEDTLS_BIGNUM_ALT +/* The following units have ESP32 hardware support, + uncommenting each _ALT macro will use the + hardware-accelerated implementation. */ +#define MBEDTLS_AES_ALT +#define MBEDTLS_SHA1_ALT +#define MBEDTLS_SHA256_ALT +#define MBEDTLS_SHA512_ALT + +/* The following MPI (bignum) functions have ESP32 hardware support, + Uncommenting these macros will use the hardware-accelerated + implementations. +*/ +#define MBEDTLS_MPI_EXP_MOD_ALT +#define MBEDTLS_MPI_MUL_MPI_ALT + /** * \def MBEDTLS_MD2_PROCESS_ALT * diff --git a/components/mbedtls/library/bignum.c b/components/mbedtls/library/bignum.c index e438fdddb..e739bc1d3 100644 --- a/components/mbedtls/library/bignum.c +++ b/components/mbedtls/library/bignum.c @@ -1164,6 +1164,7 @@ void mpi_mul_hlp( size_t i, mbedtls_mpi_uint *s, mbedtls_mpi_uint *d, mbedtls_mp while( c != 0 ); } +#if !defined(MBEDTLS_MPI_MUL_MPI_ALT) /* * Baseline multiplication: X = A * B (HAC 14.12) */ @@ -1200,6 +1201,7 @@ cleanup: return( ret ); } +#endif /* * Baseline multiplication: X = A * b @@ -1598,6 +1600,7 @@ static int mpi_montred( mbedtls_mpi *A, const mbedtls_mpi *N, mbedtls_mpi_uint m return( mpi_montmul( A, &U, N, mm, T ) ); } +#if !defined(MBEDTLS_MPI_EXP_MOD_ALT) /* * Sliding-window exponentiation: X = A^E mod N (HAC 14.85) */ @@ -1805,6 +1808,7 @@ cleanup: return( ret ); } +#endif /* * Greatest common divisor: G = gcd(A, B) (HAC 14.54) diff --git a/components/mbedtls/port/esp_bignum.c b/components/mbedtls/port/esp_bignum.c new file mode 100644 index 000000000..59bdc8726 --- /dev/null +++ b/components/mbedtls/port/esp_bignum.c @@ -0,0 +1,536 @@ +/** + * \brief Multi-precision integer library, ESP32 hardware accelerated parts + * + * based on mbedTLS implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#include +#include +#include +#include "mbedtls/bignum.h" +#include "mbedtls/bn_mul.h" +#include "rom/bigint.h" + +#if defined(MBEDTLS_MPI_MUL_MPI_ALT) || defined(MBEDTLS_MPI_EXP_MOD_ALT) + +/* Constants from mbedTLS bignum.c */ +#define ciL (sizeof(mbedtls_mpi_uint)) /* chars in limb */ +#define biL (ciL << 3) /* bits in limb */ + +static _lock_t mpi_lock; + +/* At the moment these hardware locking functions aren't exposed publically + for MPI. If you want to use the ROM bigint functions and co-exist with mbedTLS, + please raise a feature request. +*/ +static void esp_mpi_acquire_hardware( void ) +{ + /* newlib locks lazy initialize on ESP-IDF */ + _lock_acquire(&mpi_lock); + ets_bigint_enable(); +} + +static void esp_mpi_release_hardware( void ) +{ + ets_bigint_disable(); + _lock_release(&mpi_lock); +} + +/* + * Helper for mbedtls_mpi multiplication + * copied/trimmed from mbedtls bignum.c + */ +static void mpi_mul_hlp( size_t i, mbedtls_mpi_uint *s, mbedtls_mpi_uint *d, mbedtls_mpi_uint b ) +{ + mbedtls_mpi_uint c = 0, t = 0; + + for( ; i >= 16; i -= 16 ) + { + MULADDC_INIT + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_STOP + } + + for( ; i >= 8; i -= 8 ) + { + MULADDC_INIT + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + + MULADDC_CORE MULADDC_CORE + MULADDC_CORE MULADDC_CORE + MULADDC_STOP + } + + + for( ; i > 0; i-- ) + { + MULADDC_INIT + MULADDC_CORE + MULADDC_STOP + } + + t++; + + do { + *d += c; c = ( *d < c ); d++; + } + while( c != 0 ); +} + + +/* + * Helper for mbedtls_mpi subtraction + * Copied/adapter from mbedTLS bignum.c + */ +static void mpi_sub_hlp( size_t n, mbedtls_mpi_uint *s, mbedtls_mpi_uint *d ) +{ + size_t i; + mbedtls_mpi_uint c, z; + + for( i = c = 0; i < n; i++, s++, d++ ) + { + z = ( *d < c ); *d -= c; + c = ( *d < *s ) + z; *d -= *s; + } + + while( c != 0 ) + { + z = ( *d < c ); *d -= c; + c = z; i++; d++; + } +} + + +/* The following 3 Montgomery arithmetic function are + copied from mbedTLS bigint.c verbatim as they are static. + + TODO: find a way to support making the versions in mbedtls + non-static. +*/ + +/* + * Fast Montgomery initialization (thanks to Tom St Denis) + */ +static void mpi_montg_init( mbedtls_mpi_uint *mm, const mbedtls_mpi *N ) +{ + mbedtls_mpi_uint x, m0 = N->p[0]; + unsigned int i; + + x = m0; + x += ( ( m0 + 2 ) & 4 ) << 1; + + for( i = biL; i >= 8; i /= 2 ) + x *= ( 2 - ( m0 * x ) ); + + *mm = ~x + 1; +} + +/* + * Montgomery multiplication: A = A * B * R^-1 mod N (HAC 14.36) + */ +static int mpi_montmul( mbedtls_mpi *A, const mbedtls_mpi *B, const mbedtls_mpi *N, mbedtls_mpi_uint mm, + const mbedtls_mpi *T ) +{ + size_t i, n, m; + mbedtls_mpi_uint u0, u1, *d; + + if( T->n < N->n + 1 || T->p == NULL ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + memset( T->p, 0, T->n * ciL ); + + d = T->p; + n = N->n; + m = ( B->n < n ) ? B->n : n; + + for( i = 0; i < n; i++ ) + { + /* + * T = (T + u0*B + u1*N) / 2^biL + */ + u0 = A->p[i]; + u1 = ( d[0] + u0 * B->p[0] ) * mm; + + mpi_mul_hlp( m, B->p, d, u0 ); + mpi_mul_hlp( n, N->p, d, u1 ); + + *d++ = u0; d[n + 1] = 0; + } + + memcpy( A->p, d, ( n + 1 ) * ciL ); + + if( mbedtls_mpi_cmp_abs( A, N ) >= 0 ) + mpi_sub_hlp( n, N->p, A->p ); + else + /* prevent timing attacks */ + mpi_sub_hlp( n, A->p, T->p ); + + return( 0 ); +} + +/* + * Montgomery reduction: A = A * R^-1 mod N + */ +static int mpi_montred( mbedtls_mpi *A, const mbedtls_mpi *N, mbedtls_mpi_uint mm, const mbedtls_mpi *T ) +{ + mbedtls_mpi_uint z = 1; + mbedtls_mpi U; + + U.n = U.s = (int) z; + U.p = &z; + + return( mpi_montmul( A, &U, N, mm, T ) ); +} + + +/* Allocate parameters used by hardware MPI multiply, + and copy mbedtls_mpi structures into them */ +static int mul_pram_alloc(const mbedtls_mpi *A, const mbedtls_mpi *B, char **pA, char **pB, char **pX, size_t *bites) +{ + char *sa, *sb, *sx; +// int algn; + int words, bytes; + int abytes, bbytes; + + if (A->n > B->n) + words = A->n; + else + words = B->n; + + bytes = (words / 16 + ((words % 16) ? 1 : 0 )) * 16 * 4 * 2; + + abytes = A->n * 4; + bbytes = B->n * 4; + + sa = malloc(bytes); + if (!sa) { + return -1; + } + + sb = malloc(bytes); + if (!sb) { + free(sa); + return -1; + } + + sx = malloc(bytes); + if (!sx) { + free(sa); + free(sb); + return -1; + } + + memcpy(sa, A->p, abytes); + memset(sa + abytes, 0, bytes - abytes); + + memcpy(sb, B->p, bbytes); + memset(sb + bbytes, 0, bytes - bbytes); + + *pA = sa; + *pB = sb; + + *pX = sx; + + *bites = bytes * 4; + + return 0; +} + +#if defined(MBEDTLS_MPI_MUL_MPI_ALT) + +int mbedtls_mpi_mul_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) +{ + int ret = -1; + size_t i, j; + char *s1 = NULL, *s2 = NULL, *dest = NULL; + size_t bites; + + mbedtls_mpi TA, TB; + + mbedtls_mpi_init( &TA ); mbedtls_mpi_init( &TB ); + + if( X == A ) { MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TA, A ) ); A = &TA; } + if( X == B ) { MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &TB, B ) ); B = &TB; } + + for( i = A->n; i > 0; i-- ) + if( A->p[i - 1] != 0 ) + break; + + for( j = B->n; j > 0; j-- ) + if( B->p[j - 1] != 0 ) + break; + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, i + j ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); + + if (mul_pram_alloc(A, B, &s1, &s2, &dest, &bites)) { + goto cleanup; + } + + esp_mpi_acquire_hardware(); + if (ets_bigint_mult_prepare((uint32_t *)s1, (uint32_t *)s2, bites)){ + ets_bigint_wait_finish(); + if (ets_bigint_mult_getz((uint32_t *)dest, bites) == true) { + memcpy(X->p, dest, (i + j) * 4); + ret = 0; + } else { + printf("ets_bigint_mult_getz failed\n"); + } + } else{ + printf("Baseline multiplication failed\n"); + } + esp_mpi_release_hardware(); + + X->s = A->s * B->s; + + free(s1); + free(s2); + free(dest); + +cleanup: + + mbedtls_mpi_free( &TB ); mbedtls_mpi_free( &TA ); + + return( ret ); +} + +#endif /* MBEDTLS_MPI_MUL_MPI_ALT */ + +#if defined(MBEDTLS_MPI_EXP_MOD_ALT) +/* + * Sliding-window exponentiation: X = A^E mod N (HAC 14.85) + */ +int mbedtls_mpi_exp_mod( mbedtls_mpi* X, const mbedtls_mpi* A, const mbedtls_mpi* E, const mbedtls_mpi* N, mbedtls_mpi* _RR ) +{ + int ret; + size_t wbits, wsize, one = 1; + size_t i, j, nblimbs; + size_t bufsize, nbits; + mbedtls_mpi_uint ei, mm, state; + mbedtls_mpi RR, T, W[ 2 << MBEDTLS_MPI_WINDOW_SIZE ], Apos; + int neg; + + if( mbedtls_mpi_cmp_int( N, 0 ) < 0 || ( N->p[0] & 1 ) == 0 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + if( mbedtls_mpi_cmp_int( E, 0 ) < 0 ) + return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + + /* + * Init temps and window size + */ + mpi_montg_init( &mm, N ); + mbedtls_mpi_init( &RR ); mbedtls_mpi_init( &T ); + mbedtls_mpi_init( &Apos ); + memset( W, 0, sizeof( W ) ); + + i = mbedtls_mpi_bitlen( E ); + + wsize = ( i > 671 ) ? 6 : ( i > 239 ) ? 5 : + ( i > 79 ) ? 4 : ( i > 23 ) ? 3 : 1; + + if( wsize > MBEDTLS_MPI_WINDOW_SIZE ) + wsize = MBEDTLS_MPI_WINDOW_SIZE; + + j = N->n + 1; + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, j ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[1], j ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T, j * 2 ) ); + + /* + * Compensate for negative A (and correct at the end) + */ + neg = ( A->s == -1 ); + if( neg ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Apos, A ) ); + Apos.s = 1; + A = &Apos; + } + + /* + * If 1st call, pre-compute R^2 mod N + */ + if( _RR == NULL || _RR->p == NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &RR, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &RR, N->n * 2 * biL ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &RR, &RR, N ) ); + + if( _RR != NULL ) + memcpy( _RR, &RR, sizeof( mbedtls_mpi) ); + } + else + memcpy( &RR, _RR, sizeof( mbedtls_mpi) ); + + /* + * W[1] = A * R^2 * R^-1 mod N = A * R mod N + */ + if( mbedtls_mpi_cmp_mpi( A, N ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &W[1], A, N ) ); + else + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[1], A ) ); + + mpi_montmul( &W[1], &RR, N, mm, &T ); + + /* + * X = R^2 * R^-1 mod N = R mod N + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( X, &RR ) ); + mpi_montred( X, N, mm, &T ); + + if( wsize > 1 ) + { + /* + * W[1 << (wsize - 1)] = W[1] ^ (wsize - 1) + */ + j = one << ( wsize - 1 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[j], N->n + 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[j], &W[1] ) ); + + for( i = 0; i < wsize - 1; i++ ) + mpi_montmul( &W[j], &W[j], N, mm, &T ); + + /* + * W[i] = W[i - 1] * W[1] + */ + for( i = j + 1; i < ( one << wsize ); i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &W[i], N->n + 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &W[i], &W[i - 1] ) ); + + mpi_montmul( &W[i], &W[1], N, mm, &T ); + } + } + + nblimbs = E->n; + bufsize = 0; + nbits = 0; + wbits = 0; + state = 0; + + while( 1 ) + { + if( bufsize == 0 ) + { + if( nblimbs == 0 ) + break; + + nblimbs--; + + bufsize = sizeof( mbedtls_mpi_uint ) << 3; + } + + bufsize--; + + ei = (E->p[nblimbs] >> bufsize) & 1; + + /* + * skip leading 0s + */ + if( ei == 0 && state == 0 ) + continue; + + if( ei == 0 && state == 1 ) + { + /* + * out of window, square X + */ + mpi_montmul( X, X, N, mm, &T ); + continue; + } + + /* + * add ei to current window + */ + state = 2; + + nbits++; + wbits |= ( ei << ( wsize - nbits ) ); + + if( nbits == wsize ) + { + /* + * X = X^wsize R^-1 mod N + */ + for( i = 0; i < wsize; i++ ) + mpi_montmul( X, X, N, mm, &T ); + + /* + * X = X * W[wbits] R^-1 mod N + */ + mpi_montmul( X, &W[wbits], N, mm, &T ); + + state--; + nbits = 0; + wbits = 0; + } + } + + /* + * process the remaining bits + */ + for( i = 0; i < nbits; i++ ) + { + mpi_montmul( X, X, N, mm, &T ); + + wbits <<= 1; + + if( ( wbits & ( one << wsize ) ) != 0 ) + mpi_montmul( X, &W[1], N, mm, &T ); + } + + /* + * X = A^E * R * R^-1 mod N = A^E mod N + */ + mpi_montred( X, N, mm, &T ); + + if( neg ) + { + X->s = -1; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( X, N, X ) ); + } + +cleanup: + + for( i = ( one << ( wsize - 1 ) ); i < ( one << wsize ); i++ ) + mbedtls_mpi_free( &W[i] ); + + mbedtls_mpi_free( &W[1] ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &Apos ); + + if( _RR == NULL || _RR->p == NULL ) + mbedtls_mpi_free( &RR ); + + return( ret ); +} + +#endif /* MBEDTLS_MPI_EXP_MOD_ALT */ + +#endif /* MBEDTLS_MPI_MUL_MPI_ALT || MBEDTLS_MPI_EXP_MOD_ALT */ + diff --git a/components/mbedtls/port/esp_hardware.c b/components/mbedtls/port/esp_hardware.c index b83c4d7aa..915766249 100644 --- a/components/mbedtls/port/esp_hardware.c +++ b/components/mbedtls/port/esp_hardware.c @@ -9,34 +9,8 @@ #include #if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) -/** - * \brief Entropy poll callback for a hardware source - * - * \warning This is not provided by mbed TLS! - * See \c MBEDTLS_ENTROPY_HARDWARE_ALT in config.h. - * - * \note This must accept NULL as its first argument. - */ -static int os_get_random(unsigned char *buf, size_t len) -{ - int i, j; - unsigned long tmp; - - for (i = 0; i < ((len + 3) & ~3) / 4; i ++) { - tmp = rand(); - for (j = 0; j < 4; j ++) { - if ((i * 4 + j) < len) { - buf[i * 4 + j] = (unsigned char)(tmp >> (j * 8)); - } else { - break; - } - } - - } - - return 0; -} +extern int os_get_random(unsigned char *buf, size_t len); int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen ) { diff --git a/components/mbedtls/port/include/aes_alt.h b/components/mbedtls/port/include/aes_alt.h index daf30d72b..7161b282c 100644 --- a/components/mbedtls/port/include/aes_alt.h +++ b/components/mbedtls/port/include/aes_alt.h @@ -29,9 +29,9 @@ extern "C" { #endif #if defined(MBEDTLS_AES_ALT) -#include "aes.h" +#include "hwcrypto/aes.h" -typedef AES_CTX mbedtls_aes_context; +typedef esp_aes_context mbedtls_aes_context; #define mbedtls_aes_init esp_aes_init #define mbedtls_aes_free esp_aes_free diff --git a/components/mbedtls/port/include/bignum_alt.h b/components/mbedtls/port/include/bignum_alt.h deleted file mode 100644 index f30d7d25c..000000000 --- a/components/mbedtls/port/include/bignum_alt.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * \file bignum_alt.h - * - * \brief Multi-precision integer library - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#ifndef BIGNUM_ALT_H -#define BIGNUM_ALT_H - -#include "bignum.h" - -#if defined(MBEDTLS_BIGNUM_ALT) - -typedef MPI_CTX mbedtls_mpi; - -#define mbedtls_mpi_init esp_mpi_init -#define mbedtls_mpi_free esp_mpi_free -#define mbedtls_mpi_grow esp_mpi_grow -#define mbedtls_mpi_shrink esp_mpi_shrink -#define mbedtls_mpi_copy esp_mpi_copy -#define mbedtls_mpi_swap esp_mpi_swap -#define mbedtls_mpi_safe_cond_assign esp_mpi_safe_cond_assign -#define mbedtls_mpi_safe_cond_swap esp_mpi_safe_cond_swap -#define mbedtls_mpi_lset esp_mpi_lset -#define mbedtls_mpi_get_bit esp_mpi_get_bit -#define mbedtls_mpi_set_bit esp_mpi_set_bit -#define mbedtls_mpi_lsb esp_mpi_lsb -#define mbedtls_mpi_bitlen esp_mpi_bitlen -#define mbedtls_mpi_size esp_mpi_size -#define mbedtls_mpi_read_string esp_mpi_read_string -#define mbedtls_mpi_write_string esp_mpi_write_string -#define mbedtls_mpi_read_binary esp_mpi_read_binary -#define mbedtls_mpi_write_binary esp_mpi_write_binary -#define mbedtls_mpi_shift_l esp_mpi_shift_l -#define mbedtls_mpi_shift_r esp_mpi_shift_r -#define mbedtls_mpi_cmp_abs esp_mpi_cmp_abs -#define mbedtls_mpi_cmp_mpi esp_mpi_cmp_mpi -#define mbedtls_mpi_cmp_int esp_mpi_cmp_int -#define mbedtls_mpi_add_abs esp_mpi_add_abs -#define mbedtls_mpi_sub_abs esp_mpi_sub_abs -#define mbedtls_mpi_add_mpi esp_mpi_add_mpi -#define mbedtls_mpi_sub_mpi esp_mpi_sub_mpi -#define mbedtls_mpi_add_int esp_mpi_add_int -#define mbedtls_mpi_sub_int esp_mpi_sub_int -#define mbedtls_mpi_mul_mpi esp_mpi_mul_mpi -#define mbedtls_mpi_mul_int esp_mpi_mul_int -#define mbedtls_mpi_div_mpi esp_mpi_div_mpi -#define mbedtls_mpi_div_int esp_mpi_div_int -#define mbedtls_mpi_mod_mpi esp_mpi_mod_mpi -#define mbedtls_mpi_mod_int esp_mpi_mod_int -#define mbedtls_mpi_exp_mod esp_mpi_exp_mod -#define mbedtls_mpi_fill_random esp_mpi_fill_random -#define mbedtls_mpi_gcd esp_mpi_gcd -#define mbedtls_mpi_inv_mod esp_mpi_inv_mod -#define mbedtls_mpi_is_prime esp_mpi_is_prime -#define mbedtls_mpi_gen_prime esp_mpi_gen_prime - -#endif - -#endif - diff --git a/components/mbedtls/port/include/sha1_alt.h b/components/mbedtls/port/include/sha1_alt.h index 3cf39d2ff..60297b9fb 100644 --- a/components/mbedtls/port/include/sha1_alt.h +++ b/components/mbedtls/port/include/sha1_alt.h @@ -1,7 +1,6 @@ /* * copyright (c) 2010 - 2012 Espressif System * - * esf Link List Descriptor */ #ifndef _SHA1_ALT_H_ #define _SHA1_ALT_H_ @@ -12,9 +11,9 @@ extern "C" { #if defined(MBEDTLS_SHA1_ALT) -#include "sha.h" +#include "hwcrypto/sha.h" -typedef SHA1_CTX mbedtls_sha1_context; +typedef esp_sha_context mbedtls_sha1_context; #define mbedtls_sha1_init esp_sha1_init #define mbedtls_sha1_starts esp_sha1_start @@ -22,7 +21,7 @@ typedef SHA1_CTX mbedtls_sha1_context; #define mbedtls_sha1_update esp_sha1_update #define mbedtls_sha1_finish esp_sha1_finish #define mbedtls_sha1_free esp_sha1_free -#define mbedtls_sha1_process esp_sha1_process +#define mbedtls_sha1_process(...) #endif diff --git a/components/mbedtls/port/include/sha256_alt.h b/components/mbedtls/port/include/sha256_alt.h index 15ea356ac..6d9986b3a 100644 --- a/components/mbedtls/port/include/sha256_alt.h +++ b/components/mbedtls/port/include/sha256_alt.h @@ -1,7 +1,6 @@ /* * copyright (c) 2010 - 2012 Espressif System * - * esf Link List Descriptor */ #ifndef _SHA256_ALT_H_ @@ -13,9 +12,9 @@ extern "C" { #if defined(MBEDTLS_SHA256_ALT) -#include "sha.h" +#include "hwcrypto/sha.h" -typedef SHA256_CTX mbedtls_sha256_context; +typedef esp_sha_context mbedtls_sha256_context; #define mbedtls_sha256_init esp_sha256_init #define mbedtls_sha256_clone esp_sha256_clone @@ -23,7 +22,7 @@ typedef SHA256_CTX mbedtls_sha256_context; #define mbedtls_sha256_update esp_sha256_update #define mbedtls_sha256_finish esp_sha256_finish #define mbedtls_sha256_free esp_sha256_free -#define mbedtls_sha256_process esp_sha256_process +#define mbedtls_sha256_process(...) #endif diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h index 9e337c1b6..c9f6bdc85 100644 --- a/components/mbedtls/port/include/sha512_alt.h +++ b/components/mbedtls/port/include/sha512_alt.h @@ -12,9 +12,9 @@ extern "C" { #endif #if defined(MBEDTLS_SHA512_ALT) -#include "sha.h" +#include "hwcrypto/sha.h" -typedef SHA512_CTX mbedtls_sha512_context; +typedef esp_sha_context mbedtls_sha512_context; #define mbedtls_sha512_init esp_sha512_init #define mbedtls_sha512_process esp_sha512_process @@ -22,7 +22,7 @@ typedef SHA512_CTX mbedtls_sha512_context; #define mbedtls_sha512_starts esp_sha512_start #define mbedtls_sha512_update esp_sha512_update #define mbedtls_sha512_finish esp_sha512_finish -#define mbedtls_sha512_free esp_sha512_free +#define mbedtls_sha512_free(...) #endif From 7268f0a60a8d1c019ab8999401ba6ae66a477b0d Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 8 Sep 2016 20:02:26 +0800 Subject: [PATCH 19/57] components/log: add API header for logging library TW6703 --- components/log/include/esp_log.h | 120 +++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 components/log/include/esp_log.h diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h new file mode 100644 index 000000000..e8ecf875b --- /dev/null +++ b/components/log/include/esp_log.h @@ -0,0 +1,120 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_LOG_H__ +#define __ESP_LOG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Logging library + * + * In each C file which uses logging functionality, define TAG variable like this: + * + * static const char* TAG = "MyModule"; + * + * then use one of logging macros to produce output, e.g: + * + * ESP_LOGW(TAG, "Baud rate error %.1f%%. Requested: %d baud, actual: %d baud", error * 100, baud_req, baud_real); + * + * Log filtering happens both at compile time and at runtime. + * + * At compile time, filtering is done using CONFIG_ESP_LOG_LEVEL macro, set via menuconfig. + * All logging statments for levels higher than CONFIG_ESP_LOG_LEVEL will be removed by the preprocessor. + * + * At run time, all logs below CONFIG_ESP_LOG_LEVEL are enabled by default. + * esp_log_set function may be used to set logging level per tag. + * + * esp_log_set("*", ESP_LOG_ERROR); // set all components to ERROR level + * esp_log_set("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack + * esp_log_set("dhcpc", ESP_LOG_INFO); // enable INFO logs from DHCP client + * + * + */ + + +typedef enum { + ESP_LOG_NONE, + ESP_LOG_ERROR, + ESP_LOG_WARN, + ESP_LOG_INFO, + ESP_LOG_DEBUG, + ESP_LOG_VERBOSE +} esp_log_level_t; + + +/** + * @brief Set log level for given tag + * + * If logging for given component has already been enabled, changes previous setting. + * + * @param tag Tag of the log entries to enable. Must be a non-NULL zero terminated string. + * Value "*" means that all tags are affected. + * + * @param level Selects log level to enable. Only logs at this and lower levels will be shown. + */ +void esp_log_set(const char* tag, esp_log_level_t level); + +/** + * @brief Write message into the log + * + * This function is not intended to be used directly. Instead, use one of + * ESP_LOGE, ESP_LOGW, ESP_LOGI, ESP_LOGD, ESP_LOGV macros. + */ +void esp_log_write(esp_log_level_t level, const char* tag, const char* format, ...) __attribute__ ((format (printf, 3, 4))); +#ifndef CONFIG_ESP_LOG_LEVEL +#define CONFIG_ESP_LOG_LEVEL ESP_LOG_NONE +#endif + +#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_ERROR) +#define ESP_LOGE( tag, format, ... ) esp_log_write(ESP_LOG_ERROR, tag, format, ##__VA_ARGS__) +#else +#define ESP_LOGE( tag, format, ... ) +#endif + +#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_WARN) +#define ESP_LOGW( tag, format, ... ) esp_log_write(ESP_LOG_WARN, tag, format, ##__VA_ARGS__) +#else +#define ESP_LOGW( tag, format, ... ) +#endif + +#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_INFO) +#define ESP_LOGI( tag, format, ... ) esp_log_write(ESP_LOG_INFO, tag, format, ##__VA_ARGS__) +#else +#define ESP_LOGI( tag, format, ... ) +#endif + + +#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_DEBUG) +#define ESP_LOGD( tag, format, ... ) esp_log_write(ESP_LOG_DEBUG, tag, format, ##__VA_ARGS__) +#else +#define ESP_LOGD( tag, format, ... ) +#endif + +#if (CONFIG_ESP_LOG_VERBOSE < ESP_LOG_ERROR) +#define ESP_LOGV( tag, format, ... ) esp_log_write(ESP_LOG_VERBOSE, tag, format, ##__VA_ARGS__) +#else +#define ESP_LOGV( tag, format, ... ) +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* __ESP_LOG_H__ */ From 7c58c1e06b9704d5c0dfea6248e2f1f1e2d10129 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 10:14:38 +1000 Subject: [PATCH 20/57] Build system: Allow components to add to the global CFLAGS via Makefile.projbuild Used by mbedTLS to set MBEDTLS_CONFIG_FILE in all components. This change sets CFLAGS/etc at the project level and then exports those variables for components, rather than setting them independently each time a component Makefile is invoked. --- components/bootloader/Makefile.projbuild | 4 --- components/expat/Makefile | 2 +- components/lwip/component.mk | 2 +- components/mbedtls/Makefile.projbuild | 4 +++ components/mbedtls/component.mk | 2 -- components/tcpip_adapter/component.mk | 2 +- docs/build_system.rst | 35 ++++++++++++++++-------- make/common.mk | 26 ------------------ make/component_common.mk | 8 ++---- make/project.mk | 35 ++++++++++++++++++++++++ make/project_config.mk | 2 -- tools/kconfig/Makefile | 4 +++ 12 files changed, 73 insertions(+), 53 deletions(-) create mode 100644 components/mbedtls/Makefile.projbuild diff --git a/components/bootloader/Makefile.projbuild b/components/bootloader/Makefile.projbuild index 48c09d481..c8f6e5e62 100644 --- a/components/bootloader/Makefile.projbuild +++ b/components/bootloader/Makefile.projbuild @@ -17,15 +17,11 @@ BOOTLOADER_BIN=$(BOOTLOADER_BUILD_DIR)/bootloader.bin $(BOOTLOADER_BIN): $(COMPONENT_PATH)/src/sdkconfig $(Q) PROJECT_PATH= \ - LDFLAGS= \ - CFLAGS= \ BUILD_DIR_BASE=$(BOOTLOADER_BUILD_DIR) \ $(MAKE) -C $(BOOTLOADER_COMPONENT_PATH)/src MAKEFLAGS= V=$(V) TARGET_BIN_LAYOUT="$(BOOTLOADER_TARGET_BIN_LAYOUT)" $(BOOTLOADER_BIN) bootloader-clean: $(Q) PROJECT_PATH= \ - LDFLAGS= \ - CFLAGS= \ BUILD_DIR_BASE=$(BOOTLOADER_BUILD_DIR) \ $(MAKE) -C $(BOOTLOADER_COMPONENT_PATH)/src app-clean MAKEFLAGS= V=$(V) diff --git a/components/expat/Makefile b/components/expat/Makefile index 96b74ce25..81990aa59 100644 --- a/components/expat/Makefile +++ b/components/expat/Makefile @@ -10,6 +10,6 @@ COMPONENT_ADD_INCLUDEDIRS := port/include include/expat COMPONENT_SRCDIRS := library port -EXTRA_CFLAGS := -Wno-error=address -Waddress -DHAVE_EXPAT_CONFIG_H +CFLAGS += -Wno-error=address -Waddress -DHAVE_EXPAT_CONFIG_H include $(IDF_PATH)/make/component.mk diff --git a/components/lwip/component.mk b/components/lwip/component.mk index a605355d2..750c1cc0c 100644 --- a/components/lwip/component.mk +++ b/components/lwip/component.mk @@ -6,6 +6,6 @@ COMPONENT_ADD_INCLUDEDIRS := include/lwip include/lwip/port include/lwip/posix COMPONENT_SRCDIRS := api apps/sntp apps core/ipv4 core/ipv6 core netif port/freertos port/netif port -EXTRA_CFLAGS := -Wno-error=address -Waddress -DLWIP_ESP8266 +CFLAGS += -Wno-error=address -Waddress -DLWIP_ESP8266 include $(IDF_PATH)/make/component_common.mk diff --git a/components/mbedtls/Makefile.projbuild b/components/mbedtls/Makefile.projbuild new file mode 100644 index 000000000..51300efd1 --- /dev/null +++ b/components/mbedtls/Makefile.projbuild @@ -0,0 +1,4 @@ +# Anyone compiling mbedTLS code needs the name of the +# alternative config file +CFLAGS += -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' + diff --git a/components/mbedtls/component.mk b/components/mbedtls/component.mk index ed8f117ff..98838d4d7 100644 --- a/components/mbedtls/component.mk +++ b/components/mbedtls/component.mk @@ -6,6 +6,4 @@ COMPONENT_ADD_INCLUDEDIRS := port/include include COMPONENT_SRCDIRS := library port -EXTRA_CFLAGS += -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' - include $(IDF_PATH)/make/component_common.mk diff --git a/components/tcpip_adapter/component.mk b/components/tcpip_adapter/component.mk index cb863d1b7..14596443f 100755 --- a/components/tcpip_adapter/component.mk +++ b/components/tcpip_adapter/component.mk @@ -2,6 +2,6 @@ # Component Makefile # -EXTRA_CFLAGS := -DLWIP_ESP8266 +CFLAGS += -DLWIP_ESP8266 include $(IDF_PATH)/make/component_common.mk diff --git a/docs/build_system.rst b/docs/build_system.rst index 24381019b..43055a478 100644 --- a/docs/build_system.rst +++ b/docs/build_system.rst @@ -60,7 +60,7 @@ influencing the build process of the component as well as the project it's used in. Components may also include a Kconfig file defining the compile-time options that are settable by means of the menu system. -Project makefile variables that can be set by the programmer:: +Project Makefile variables that can be set by the programmer:: PROJECT_NAME: Mandatory. Name for the project BUILD_DIR_BASE: Set the directory where all objects/libraries/binaries end up in. @@ -76,17 +76,20 @@ Project makefile variables that can be set by the programmer:: include directories that are passed to the compilation pass of all components and they do not have a Kconfig option. -Component makefile variables that can be set by the programmer:: +Component-specific component.mk variables that can be set by the programmer:: COMPONENT_ADD_INCLUDEDIRS: Relative path to include directories to be added to - the entire project + the entire project. If an include directory is only needed to compile this + specific component, don't add it here. COMPONENT_PRIV_INCLUDEDIRS: Relative path to include directories that are only used - when compiling this specific component + when compiling this specific component. COMPONENT_DEPENDS: Names of any components that need to be compiled before this component. - COMPONENT_ADD_LDFLAGS: Ld flags to add for this project. Defaults to -l$(COMPONENT_NAME). + COMPONENT_ADD_LDFLAGS: LD flags to add for the entire project. Defaults to -l$(COMPONENT_NAME). Add libraries etc in the current directory as $(abspath libwhatever.a) - COMPONENT_EXTRA_INCLUDES: Any extra include paths. These will be prefixed with '-I' and - passed to the compiler; please put absolute paths here. + COMPONENT_EXTRA_INCLUDES: Any extra include paths used when compiling the component's + source files. These will be prefixed with '-I' and passed to the compiler. + Similar to COMPONENT_PRIV_INCLUDEDIRS, but these paths are passed as-is instead of + expanded relative to the component directory. COMPONENT_SRCDIRS: Relative directories to look in for sources. Defaults to '.', the current directory (the root of the component) only. Use this to specify any subdirectories. Note that specifying this overwrites the default action of compiling everything in the @@ -114,6 +117,10 @@ be usable in component or project Makefiles:: COMPONENTS: Name of the components to be included CONFIG_*: All values set by 'make menuconfig' have corresponding Makefile variables. +Inside your component's component.mk makefile, you can override or add to these variables +as necessary. The changes are isolated from other components (see Makefile.projbuild below +if you want to share these changes with all other components.) + For components, there also are these defines:: COMPONENT_PATH: Absolute path to the root of the source tree of the component we're @@ -152,10 +159,16 @@ details to add to "menuconfig" for this component. Makefile.projbuild ------------------ -For components that have parts that need to be run when building of the -project is done, you can create a file called Makefile.projbuild in the -component root directory. This file will be included in the main -Makefile. +For components that have parts that need to be evaluated in the top-level +project context, you can create a file called Makefile.projbuild in the +component root directory. These files is included into the project's +top-level Makefile. + +For example, if your component needs to add to CFLAGS for the entire +project (not just for its own source files) then you can set +``CFLAGS +=`` in Makefile.projbuild. Note that this isn't necessary for +adding include directories to the project, you can set +``COMPONENT_ADD_INCLUDEDIRS`` (see above) in the component.mk. KConfig.projbuild diff --git a/make/common.mk b/make/common.mk index 7f372cc30..4965fa352 100644 --- a/make/common.mk +++ b/make/common.mk @@ -8,32 +8,6 @@ # see project_config.mk for details.) -include $(PROJECT_PATH)/build/include/config/auto.conf -ifeq ("$(LDFLAGS)","") -LDFLAGS = -nostdlib \ - -L$(IDF_PATH)/lib \ - -L$(IDF_PATH)/ld \ - $(addprefix -L$(BUILD_DIR_BASE)/,$(COMPONENTS) $(SRCDIRS)) \ - -u call_user_start_cpu0 \ - -Wl,--gc-sections \ - -Wl,-static \ - -Wl,--start-group \ - $(COMPONENT_LDFLAGS) \ - -lgcc \ - -Wl,--end-group -endif - -ifeq ("$(CFLAGS)","") -CFLAGS = -DESP_PLATFORM -Og -std=gnu99 -g3 \ - -Wpointer-arith -Werror -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable \ - -Wl,-EL -fno-inline-functions -nostdlib -mlongcalls -Wall -ffunction-sections -fdata-sections $(EXTRA_CFLAGS) -endif - -ifeq ("$(CXXFLAGS)","") -CXXFLAGS = -DESP_PLATFORM -Og -std=gnu++11 -g3 \ - -Wpointer-arith -Werror -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable \ - -Wl,-EL -nostdlib -mlongcalls -Wall -ffunction-sections -fdata-sections $(EXTRA_CFLAGS) -fno-exceptions -endif - #Handling of V=1/VERBOSE=1 flag # # if V=1, $(summary) does nothing and $(details) will echo extra details diff --git a/make/component_common.mk b/make/component_common.mk index 1a3d9281c..ebad525a7 100644 --- a/make/component_common.mk +++ b/make/component_common.mk @@ -25,7 +25,7 @@ export COMPONENT_PATH include $(IDF_PATH)/make/common.mk -#Some of these options are overridable by the components Makefile. +#Some of these options are overridable by the component's component.mk Makefile #Name of the component COMPONENT_NAME ?= $(lastword $(subst /, ,$(realpath $(COMPONENT_PATH)))) @@ -58,7 +58,8 @@ COMPONENT_ADD_LDFLAGS ?= -l$(COMPONENT_NAME) OWN_INCLUDES:=$(abspath $(addprefix $(COMPONENT_PATH)/,$(COMPONENT_ADD_INCLUDEDIRS) $(COMPONENT_PRIV_INCLUDEDIRS))) COMPONENT_INCLUDES := $(OWN_INCLUDES) $(filter-out $(OWN_INCLUDES),$(COMPONENT_INCLUDES)) -#This target is used to collect variable values from inside the main makefile +#This target is used to collect variable values from inside project.mk +# see project.mk GetVariable macro for details. get_variable: @echo "$(GET_VARIABLE)=$(call $(GET_VARIABLE)) " @@ -82,9 +83,6 @@ clean: $(Q) rm -f $(COMPONENT_LIBRARY) $(COMPONENT_OBJS) $(COMPONENT_OBJS:.o=.d) $(COMPONENT_EXTRA_CLEAN) endif -#Also generate dependency files -CFLAGS+=-MMD -MP -CXXFLAGS+=-MMD -MP #Include all dependency files already generated -include $(COMPONENT_OBJS:.o=.d) diff --git a/make/project.mk b/make/project.mk index ca80697cb..7526774bd 100644 --- a/make/project.mk +++ b/make/project.mk @@ -133,6 +133,41 @@ export PROJECT_PATH #Include functionality common to both project & component -include $(IDF_PATH)/make/common.mk +# Set default LDFLAGS + +LDFLAGS ?= -nostdlib \ + -L$(IDF_PATH)/lib \ + -L$(IDF_PATH)/ld \ + $(addprefix -L$(BUILD_DIR_BASE)/,$(COMPONENTS) $(SRCDIRS)) \ + -u call_user_start_cpu0 \ + -Wl,--gc-sections \ + -Wl,-static \ + -Wl,--start-group \ + $(COMPONENT_LDFLAGS) \ + -lgcc \ + -Wl,--end-group \ + -Wl,-EL + +# Set default CPPFLAGS, CFLAGS, CXXFLAGS +# +# These are exported so that components can use them when compiling. +# +# If you need your component to add CFLAGS/etc for it's own source compilation only, set CFLAGS += in your component's Makefile. +# +# If you need your component to add CFLAGS/etc globally for all source +# files, set CFLAGS += in your component's Makefile.projbuild + +# CPPFLAGS used by an compile pass that uses the C preprocessor +CPPFLAGS = -DESP_PLATFORM -Og -g3 -Wpointer-arith -Werror -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wall -ffunction-sections -fdata-sections -mlongcalls -nostdlib -MMD -MP + +# C flags use by C only +CFLAGS = $(CPPFLAGS) -std=gnu99 -g3 -fno-inline-functions + +# CXXFLAGS uses by C++ only +CXXFLAGS = $(CPPFLAGS) -Og -std=gnu++11 -g3 -fno-exceptions + +export CFLAGS CPPFLAGS CXXFLAGS + #Set host compiler and binutils HOSTCC := $(CC) HOSTLD := $(LD) diff --git a/make/project_config.mk b/make/project_config.mk index e39fdac3b..d2909bb30 100644 --- a/make/project_config.mk +++ b/make/project_config.mk @@ -10,8 +10,6 @@ KCONFIG_TOOL_DIR=$(IDF_PATH)/tools/kconfig # clear MAKEFLAGS as the menuconfig makefile uses implicit compile rules $(KCONFIG_TOOL_DIR)/mconf $(KCONFIG_TOOL_DIR)/conf: MAKEFLAGS="" \ - CFLAGS="" \ - LDFLAGS="" \ CC=$(HOSTCC) LD=$(HOSTLD) \ $(MAKE) -C $(KCONFIG_TOOL_DIR) diff --git a/tools/kconfig/Makefile b/tools/kconfig/Makefile index b265e9b38..2df04f3f2 100644 --- a/tools/kconfig/Makefile +++ b/tools/kconfig/Makefile @@ -18,6 +18,10 @@ endif # We need this, in case the user has it in its environment unexport CONFIG_ +# Unset some environment variables set in the project environment +CFLAGS := +CPPFLAGS := +LDFLAGS := default: mconf conf From f605e0334490c85f0ea0fd2dbbd8b7cf48122063 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 10:49:35 +1000 Subject: [PATCH 21/57] make debugging: With V=1, output when including each Makefile.projbuild also enable V=1 on CI builds --- .gitlab-ci.yml | 2 +- make/project.mk | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 15a1db2fc..c222ca2fd 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -23,7 +23,7 @@ build_template_app: # branch - git checkout ${CI_BUILD_REF_NAME} || echo "Using esp-idf-template default branch..." - make defconfig - - make all + - make all V=1 test_nvs_on_host: stage: test diff --git a/make/project.mk b/make/project.mk index 7526774bd..b86470bf6 100644 --- a/make/project.mk +++ b/make/project.mk @@ -193,6 +193,7 @@ APP_BIN:=$(APP_ELF:.elf=.bin) # Include any Makefile.projbuild file letting components add # configuration at the project level define includeProjBuildMakefile +$(if $(V),$(if $(wildcard $(1)/Makefile.projbuild),$(info including $(1)/Makefile.projbuild...))) COMPONENT_PATH := $(1) -include $(1)/Makefile.projbuild endef From a939c15723282b84356596822d2fe0196a518812 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 11:24:35 +1000 Subject: [PATCH 22/57] mbedtls networking: Remove WIN32 parts, minor cleanup --- components/mbedtls/port/net.c | 83 +---------------------------------- 1 file changed, 1 insertion(+), 82 deletions(-) diff --git a/components/mbedtls/port/net.c b/components/mbedtls/port/net.c index 390513c17..482a11f97 100644 --- a/components/mbedtls/port/net.c +++ b/components/mbedtls/port/net.c @@ -32,19 +32,13 @@ #include "mbedtls/net.h" #include - #include #include -//#include #include #include -//#include - #include #include - #include - #include /* @@ -52,19 +46,6 @@ */ static int net_prepare( void ) { -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) - WSADATA wsaData; - - if ( wsa_init_done == 0 ) { - if ( WSAStartup( MAKEWORD(2, 0), &wsaData ) != 0 ) { - return ( MBEDTLS_ERR_NET_SOCKET_FAILED ); - } - - wsa_init_done = 1; - } -#else -#endif return ( 0 ); } @@ -137,7 +118,7 @@ int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char */ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto ) { - int n, ret; + int ret; struct addrinfo hints, *addr_list, *cur; if ( ( ret = net_prepare() ) != 0 ) { @@ -204,18 +185,6 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char } -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) -/* - * Check if the requested operation would be blocking on a non-blocking socket - * and thus 'failed' with a negative return value. - */ -static int net_would_block( const mbedtls_net_context *ctx ) -{ - ((void) ctx); - return ( WSAGetLastError() == WSAEWOULDBLOCK ); -} -#else /* * Check if the requested operation would be blocking on a non-blocking socket * and thus 'failed' with a negative return value. @@ -244,7 +213,6 @@ static int net_would_block( const mbedtls_net_context *ctx ) } return ( 0 ); } -#endif /* ( _WIN32 || _WIN32_WCE ) && !EFIX64 && !EFI32 */ /* * Accept a connection from a remote client @@ -279,13 +247,6 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, ret = recvfrom( bind_ctx->fd, buf, sizeof( buf ), MSG_PEEK, (struct sockaddr *) &client_addr, &n ); -#if defined(_WIN32) - if ( ret == SOCKET_ERROR && - WSAGetLastError() == WSAEMSGSIZE ) { - /* We know buf is too small, thanks, just peeking here */ - ret = 0; - } -#endif } if ( ret < 0 ) { @@ -343,24 +304,12 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, */ int mbedtls_net_set_block( mbedtls_net_context *ctx ) { -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) - u_long n = 0; - return ( ioctlsocket( ctx->fd, FIONBIO, &n ) ); -#else return ( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) & ~O_NONBLOCK ) ); -#endif } int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) { -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) - u_long n = 1; - return ( ioctlsocket( ctx->fd, FIONBIO, &n ) ); -#else return ( fcntl( ctx->fd, F_SETFL, fcntl( ctx->fd, F_GETFL, 0 ) | O_NONBLOCK ) ); -#endif } /* @@ -368,19 +317,10 @@ int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) */ void mbedtls_net_usleep( unsigned long usec ) { -#if defined(_WIN32) - Sleep( ( usec + 999 ) / 1000 ); -#else struct timeval tv; tv.tv_sec = usec / 1000000; -#if defined(__unix__) || defined(__unix) || \ - ( defined(__APPLE__) && defined(__MACH__) ) - tv.tv_usec = (suseconds_t) usec % 1000000; -#else tv.tv_usec = usec % 1000000; -#endif select( 0, NULL, NULL, NULL, &tv ); -#endif } /* @@ -404,12 +344,6 @@ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) } error = mbedtls_net_errno(fd); -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) - if ( WSAGetLastError() == WSAECONNRESET ) { - return ( MBEDTLS_ERR_NET_CONN_RESET ); - } -#else if ( error == EPIPE || error == ECONNRESET ) { return ( MBEDTLS_ERR_NET_CONN_RESET ); } @@ -417,7 +351,6 @@ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) if ( error == EINTR ) { return ( MBEDTLS_ERR_SSL_WANT_READ ); } -#endif return ( MBEDTLS_ERR_NET_RECV_FAILED ); } @@ -454,16 +387,9 @@ int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len, } if ( ret < 0 ) { -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) - if ( WSAGetLastError() == WSAEINTR ) { - return ( MBEDTLS_ERR_SSL_WANT_READ ); - } -#else if ( errno == EINTR ) { return ( MBEDTLS_ERR_SSL_WANT_READ ); } -#endif return ( MBEDTLS_ERR_NET_RECV_FAILED ); } @@ -494,12 +420,6 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) } error = mbedtls_net_errno(fd); -#if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ - !defined(EFI32) - if ( WSAGetLastError() == WSAECONNRESET ) { - return ( MBEDTLS_ERR_NET_CONN_RESET ); - } -#else if ( error == EPIPE || error == ECONNRESET ) { return ( MBEDTLS_ERR_NET_CONN_RESET ); } @@ -507,7 +427,6 @@ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) if ( error == EINTR ) { return ( MBEDTLS_ERR_SSL_WANT_WRITE ); } -#endif return ( MBEDTLS_ERR_NET_SEND_FAILED ); } From 264b115eb047dd2a3c06d14f25d3ddbd32408c77 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 14:06:14 +1000 Subject: [PATCH 23/57] mbedtls: Move esp_config.h file to port directory --- components/mbedtls/{ => port}/include/mbedtls/esp_config.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) rename components/mbedtls/{ => port}/include/mbedtls/esp_config.h (99%) diff --git a/components/mbedtls/include/mbedtls/esp_config.h b/components/mbedtls/port/include/mbedtls/esp_config.h similarity index 99% rename from components/mbedtls/include/mbedtls/esp_config.h rename to components/mbedtls/port/include/mbedtls/esp_config.h index 6d52294b7..8ef44c00c 100644 --- a/components/mbedtls/include/mbedtls/esp_config.h +++ b/components/mbedtls/port/include/mbedtls/esp_config.h @@ -1,7 +1,6 @@ /** - * \file config.h * - * \brief Configuration options (set of defines) + * \brief Default mbedTLS configuration options for esp-idf * * This set of compile-time options may be used to enable * or disable features selectively, and reduce the global @@ -2518,6 +2517,6 @@ #include MBEDTLS_USER_CONFIG_FILE #endif -#include "check_config.h" +#include "mbedtls/check_config.h" #endif /* MBEDTLS_CONFIG_H */ From 6f006c25fb5a2b83361c670faf0865aa2d3ee8f2 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 14:07:45 +1000 Subject: [PATCH 24/57] json & expat: Update component.mk after merging from master --- components/expat/{Makefile => component.mk} | 2 +- components/json/{Makefile => component.mk} | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename components/expat/{Makefile => component.mk} (91%) rename components/json/{Makefile => component.mk} (90%) diff --git a/components/expat/Makefile b/components/expat/component.mk similarity index 91% rename from components/expat/Makefile rename to components/expat/component.mk index 81990aa59..69595d7b2 100644 --- a/components/expat/Makefile +++ b/components/expat/component.mk @@ -12,4 +12,4 @@ COMPONENT_SRCDIRS := library port CFLAGS += -Wno-error=address -Waddress -DHAVE_EXPAT_CONFIG_H -include $(IDF_PATH)/make/component.mk +include $(IDF_PATH)/make/component_common.mk diff --git a/components/json/Makefile b/components/json/component.mk similarity index 90% rename from components/json/Makefile rename to components/json/component.mk index ebddafdd1..311a902f9 100644 --- a/components/json/Makefile +++ b/components/json/component.mk @@ -10,4 +10,4 @@ COMPONENT_ADD_INCLUDEDIRS := include port/include COMPONENT_SRCDIRS := library port -include $(IDF_PATH)/make/component.mk +include $(IDF_PATH)/make/component_common.mk From eb47a25012ae66c09cc73f03211ec284dffdbdfc Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 14:10:44 +1000 Subject: [PATCH 25/57] mbedtls: Revert changes to upstream library sources. This reverts part of commit 0f83831c743801960242525bc19ed15383e091e7. --- components/mbedtls/library/aes.c | 24 +++--------------------- components/mbedtls/library/sha1.c | 9 +++------ components/mbedtls/library/sha256.c | 9 +++------ components/mbedtls/library/sha512.c | 10 +++------- 4 files changed, 12 insertions(+), 40 deletions(-) diff --git a/components/mbedtls/library/aes.c b/components/mbedtls/library/aes.c index 690358519..a186dee98 100644 --- a/components/mbedtls/library/aes.c +++ b/components/mbedtls/library/aes.c @@ -1237,8 +1237,9 @@ int mbedtls_aes_self_test( int verbose ) unsigned char stream_block[16]; #endif mbedtls_aes_context ctx; - - memset( key, 0, 32 ); + + memset( key, 0, 32 ); + mbedtls_aes_init( &ctx ); /* * ECB mode @@ -1254,8 +1255,6 @@ int mbedtls_aes_self_test( int verbose ) memset( buf, 0, 16 ); - mbedtls_aes_init( &ctx ); - if( v == MBEDTLS_AES_DECRYPT ) { mbedtls_aes_setkey_dec( &ctx, key, 128 + u * 64 ); @@ -1268,7 +1267,6 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_aes_free( &ctx ); ret = 1; goto exit; } @@ -1285,8 +1283,6 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_aes_free( &ctx ); - ret = 1; goto exit; } @@ -1294,8 +1290,6 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "passed\n" ); - - mbedtls_aes_free( &ctx ); } if( verbose != 0 ) @@ -1318,8 +1312,6 @@ int mbedtls_aes_self_test( int verbose ) memset( prv, 0, 16 ); memset( buf, 0, 16 ); - mbedtls_aes_init( &ctx ); - if( v == MBEDTLS_AES_DECRYPT ) { mbedtls_aes_setkey_dec( &ctx, key, 128 + u * 64 ); @@ -1332,8 +1324,6 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_aes_free( &ctx ); - ret = 1; goto exit; } @@ -1358,8 +1348,6 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_aes_free( &ctx ); - ret = 1; goto exit; } @@ -1367,8 +1355,6 @@ int mbedtls_aes_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "passed\n" ); - - mbedtls_aes_free( &ctx ); } if( verbose != 0 ) @@ -1391,8 +1377,6 @@ int mbedtls_aes_self_test( int verbose ) memcpy( iv, aes_test_cfb128_iv, 16 ); memcpy( key, aes_test_cfb128_key[u], 16 + u * 8 ); - mbedtls_aes_init( &ctx ); - offset = 0; mbedtls_aes_setkey_enc( &ctx, key, 128 + u * 64 ); @@ -1449,8 +1433,6 @@ int mbedtls_aes_self_test( int verbose ) memcpy( nonce_counter, aes_test_ctr_nonce_counter[u], 16 ); memcpy( key, aes_test_ctr_key[u], 16 ); - mbedtls_aes_init( &ctx ); - offset = 0; mbedtls_aes_setkey_enc( &ctx, key, 128 ); diff --git a/components/mbedtls/library/sha1.c b/components/mbedtls/library/sha1.c index 46ed34f94..2ccf2a2f5 100644 --- a/components/mbedtls/library/sha1.c +++ b/components/mbedtls/library/sha1.c @@ -396,13 +396,13 @@ int mbedtls_sha1_self_test( int verbose ) unsigned char sha1sum[20]; mbedtls_sha1_context ctx; + mbedtls_sha1_init( &ctx ); + /* * SHA-1 */ for( i = 0; i < 3; i++ ) { - mbedtls_sha1_init( &ctx ); - if( verbose != 0 ) mbedtls_printf( " SHA-1 test #%d: ", i + 1 ); @@ -426,22 +426,19 @@ int mbedtls_sha1_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_sha1_free( &ctx ); - ret = 1; goto exit; } if( verbose != 0 ) mbedtls_printf( "passed\n" ); - - mbedtls_sha1_free( &ctx ); } if( verbose != 0 ) mbedtls_printf( "\n" ); exit: + mbedtls_sha1_free( &ctx ); return( ret ); } diff --git a/components/mbedtls/library/sha256.c b/components/mbedtls/library/sha256.c index cc6bd335d..4e82c0b79 100644 --- a/components/mbedtls/library/sha256.c +++ b/components/mbedtls/library/sha256.c @@ -393,13 +393,13 @@ int mbedtls_sha256_self_test( int verbose ) unsigned char sha256sum[32]; mbedtls_sha256_context ctx; + mbedtls_sha256_init( &ctx ); + for( i = 0; i < 6; i++ ) { j = i % 3; k = i < 3; - mbedtls_sha256_init( &ctx ); - if( verbose != 0 ) mbedtls_printf( " SHA-%d test #%d: ", 256 - k * 32, j + 1 ); @@ -423,22 +423,19 @@ int mbedtls_sha256_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_sha256_free( &ctx ); - ret = 1; goto exit; } if( verbose != 0 ) mbedtls_printf( "passed\n" ); - - mbedtls_sha256_free( &ctx ); } if( verbose != 0 ) mbedtls_printf( "\n" ); exit: + mbedtls_sha256_free( &ctx ); return( ret ); } diff --git a/components/mbedtls/library/sha512.c b/components/mbedtls/library/sha512.c index 245ede0eb..0f9e1e535 100644 --- a/components/mbedtls/library/sha512.c +++ b/components/mbedtls/library/sha512.c @@ -449,13 +449,13 @@ int mbedtls_sha512_self_test( int verbose ) unsigned char sha512sum[64]; mbedtls_sha512_context ctx; + mbedtls_sha512_init( &ctx ); + for( i = 0; i < 6; i++ ) { j = i % 3; k = i < 3; - mbedtls_sha512_init( &ctx ); - if( verbose != 0 ) mbedtls_printf( " SHA-%d test #%d: ", 512 - k * 128, j + 1 ); @@ -479,23 +479,19 @@ int mbedtls_sha512_self_test( int verbose ) if( verbose != 0 ) mbedtls_printf( "failed\n" ); - mbedtls_sha512_free( &ctx ); - ret = 1; goto exit; } if( verbose != 0 ) mbedtls_printf( "passed\n" ); - - mbedtls_sha512_free( &ctx ); } if( verbose != 0 ) mbedtls_printf( "\n" ); exit: - + mbedtls_sha512_free( &ctx ); return( ret ); } From 46a9754b8ef6756ba2697b2a36910bd6b4d8ba12 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 9 Sep 2016 14:27:34 +1000 Subject: [PATCH 26/57] hwcrypto sha: Fix initialisation of SHA hardware in esp_shaX_start functions Problem exposed by previous commit. --- components/esp32/hwcrypto/sha.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/components/esp32/hwcrypto/sha.c b/components/esp32/hwcrypto/sha.c index 78ecbf771..06b00c54a 100644 --- a/components/esp32/hwcrypto/sha.c +++ b/components/esp32/hwcrypto/sha.c @@ -86,8 +86,9 @@ void esp_sha1_clone( esp_sha_context *dst, const esp_sha_context *src ) */ void esp_sha1_start( esp_sha_context *ctx ) { - esp_sha_acquire_hardware(); ctx->context_type = SHA1; + esp_sha_acquire_hardware(); + ets_sha_init(&ctx->context); } /* @@ -143,12 +144,11 @@ void esp_sha256_clone( esp_sha_context *dst, const esp_sha_context *src ) */ void esp_sha256_start( esp_sha_context *ctx, int is224 ) { - esp_sha_acquire_hardware(); - ets_sha_init(&ctx->context); - if ( is224 == 0 ) { /* SHA-256 */ ctx->context_type = SHA2_256; + esp_sha_acquire_hardware(); + ets_sha_init(&ctx->context); } else { /* SHA-224 is not supported! */ ctx->context_type = SHA_INVALID; @@ -160,7 +160,10 @@ void esp_sha256_start( esp_sha_context *ctx, int is224 ) */ void esp_sha256_update( esp_sha_context *ctx, const unsigned char *input, size_t ilen ) { - esp_sha_update(ctx, input, ilen, 64); + if( ctx->context_type == SHA2_256 ) { + esp_sha_update(ctx, input, ilen, 64); + } + /* SHA-224 is a no-op */ } /* @@ -170,12 +173,12 @@ void esp_sha256_finish( esp_sha_context *ctx, unsigned char output[32] ) { if ( ctx->context_type == SHA2_256 ) { ets_sha_finish(&ctx->context, ctx->context_type, output); + esp_sha_release_hardware(); } else { /* No hardware SHA-224 support, but mbedTLS API doesn't allow failure. For now, zero the output to make it clear it's not valid. */ bzero( output, 28 ); } - esp_sha_release_hardware(); } /* @@ -218,9 +221,6 @@ void esp_sha512_clone( esp_sha_context *dst, const esp_sha_context *src ) */ void esp_sha512_start( esp_sha_context *ctx, int is384 ) { - esp_sha_acquire_hardware(); - ets_sha_init(&ctx->context); - if ( is384 == 0 ) { /* SHA-512 */ ctx->context_type = SHA2_512; @@ -228,6 +228,8 @@ void esp_sha512_start( esp_sha_context *ctx, int is384 ) /* SHA-384 */ ctx->context_type = SHA2_384; } + esp_sha_acquire_hardware(); + ets_sha_init(&ctx->context); } /* From d7f7c36af07e46db03efb312873ee4f3ac1deaac Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 13 Sep 2016 21:24:57 +0800 Subject: [PATCH 27/57] gitlab-ci: fix setting GitHub deploy key - don't run default before_script before push_master_to_github job - replace echo >> with echo > to avoid mistakes in the future --- .gitlab-ci.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 96006f8c8..8ca472d08 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -7,7 +7,7 @@ before_script: # add gitlab ssh key - mkdir -p ~/.ssh - chmod 700 ~/.ssh - - echo -n $GITLAB_KEY >> ~/.ssh/id_rsa_base64 + - echo -n $GITLAB_KEY > ~/.ssh/id_rsa_base64 - base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa - chmod 600 ~/.ssh/id_rsa - echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config @@ -125,8 +125,9 @@ sanity_test: - CONFIG_FILE=sanity_test.yml - push_master_to_github: + before_script: + - echo "Not setting up GitLab key, not fetching submodules" stage: deploy only: - master @@ -139,7 +140,7 @@ push_master_to_github: script: - mkdir -p ~/.ssh - chmod 700 ~/.ssh - - echo -n $GH_PUSH_KEY >> ~/.ssh/id_rsa_base64 + - echo -n $GH_PUSH_KEY > ~/.ssh/id_rsa_base64 - base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa - chmod 600 ~/.ssh/id_rsa - echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config From 126a68ca1ff31f6c3724c4150865aae27f90ee36 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 14 Sep 2016 17:51:27 +1000 Subject: [PATCH 28/57] mbedtls upstream tweak: Move mbedtls_sha512_process in sha512.h Function declaration should only be included if MBEDTLS_SHA512_ALT is not set. This matches sha1.h and sha256.h This change should be contributed back upstream to mbedTLS project. --- components/mbedtls/include/mbedtls/sha512.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/mbedtls/include/mbedtls/sha512.h b/components/mbedtls/include/mbedtls/sha512.h index 627694f42..12f4fab4f 100644 --- a/components/mbedtls/include/mbedtls/sha512.h +++ b/components/mbedtls/include/mbedtls/sha512.h @@ -101,6 +101,9 @@ void mbedtls_sha512_update( mbedtls_sha512_context *ctx, const unsigned char *in */ void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, unsigned char output[64] ); +/* Internal use */ +void mbedtls_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] ); + #ifdef __cplusplus } #endif @@ -131,9 +134,6 @@ void mbedtls_sha512( const unsigned char *input, size_t ilen, */ int mbedtls_sha512_self_test( int verbose ); -/* Internal use */ -void mbedtls_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] ); - #ifdef __cplusplus } #endif From f01cabf71d5f2a26c4bdd8a944e79b181f1761f5 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 14 Sep 2016 17:52:24 +1000 Subject: [PATCH 29/57] mbedtls hwcrypto sha512: Fix redirection of function names --- components/mbedtls/port/include/sha512_alt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/mbedtls/port/include/sha512_alt.h b/components/mbedtls/port/include/sha512_alt.h index c9f6bdc85..241f2be3b 100644 --- a/components/mbedtls/port/include/sha512_alt.h +++ b/components/mbedtls/port/include/sha512_alt.h @@ -17,12 +17,12 @@ extern "C" { typedef esp_sha_context mbedtls_sha512_context; #define mbedtls_sha512_init esp_sha512_init -#define mbedtls_sha512_process esp_sha512_process #define mbedtls_sha512_clone esp_sha512_clone #define mbedtls_sha512_starts esp_sha512_start #define mbedtls_sha512_update esp_sha512_update #define mbedtls_sha512_finish esp_sha512_finish -#define mbedtls_sha512_free(...) +#define mbedtls_sha512_free esp_sha512_free +#define mbedtls_sha512_process(...) #endif From 67a26d52ac05826e0eaf6a69af9966b36c9beb4e Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 14 Sep 2016 17:52:39 +1000 Subject: [PATCH 30/57] mbedtls: Temporarily disable default hardware crypto SHA & bignum Due to limitations referenced in the comments of the changes. --- .../mbedtls/port/include/mbedtls/esp_config.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/components/mbedtls/port/include/mbedtls/esp_config.h b/components/mbedtls/port/include/mbedtls/esp_config.h index 8ef44c00c..68be319c3 100644 --- a/components/mbedtls/port/include/mbedtls/esp_config.h +++ b/components/mbedtls/port/include/mbedtls/esp_config.h @@ -238,16 +238,21 @@ uncommenting each _ALT macro will use the hardware-accelerated implementation. */ #define MBEDTLS_AES_ALT -#define MBEDTLS_SHA1_ALT -#define MBEDTLS_SHA256_ALT -#define MBEDTLS_SHA512_ALT + +/* Currently hardware SHA does not work with TLS handshake, + due to concurrency issue. Internal TW#7111. */ +//#define MBEDTLS_SHA1_ALT +//#define MBEDTLS_SHA256_ALT +//#define MBEDTLS_SHA512_ALT /* The following MPI (bignum) functions have ESP32 hardware support, Uncommenting these macros will use the hardware-accelerated implementations. + + Disabled as number of limbs limited by bug. Internal TW#7112. */ -#define MBEDTLS_MPI_EXP_MOD_ALT -#define MBEDTLS_MPI_MUL_MPI_ALT +//#define MBEDTLS_MPI_EXP_MOD_ALT +//#define MBEDTLS_MPI_MUL_MPI_ALT /** * \def MBEDTLS_MD2_PROCESS_ALT From 716cec5ded2fe561d4c2bf46f8782991c6502b72 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 15 Sep 2016 00:53:33 +0800 Subject: [PATCH 31/57] components/log: add implementation, update a few components to use it This also removes logging implementation from bootloader and replaces it with the one provided by the log component. Some occurrences of printf and ets_printf have been changed to ESP_LOGx APIs. --- components/bootloader/Kconfig.projbuild | 30 -- components/bootloader/src/Makefile | 4 +- .../bootloader/src/main/bootloader_log.h | 114 ------- .../bootloader/src/main/bootloader_start.c | 91 +++--- components/bootloader/src/main/component.mk | 1 - .../bootloader/src/main/flash_encrypt.c | 62 ++-- components/bootloader/src/main/secure_boot.c | 28 +- components/esp32/cpu_start.c | 23 +- components/esp32/heap_alloc_caps.c | 14 +- components/log/Kconfig | 48 +++ components/log/component.mk | 3 + components/log/include/esp_log.h | 171 +++++++++-- components/log/log.c | 283 ++++++++++++++++++ 13 files changed, 590 insertions(+), 282 deletions(-) delete mode 100644 components/bootloader/src/main/bootloader_log.h create mode 100644 components/log/Kconfig create mode 100755 components/log/component.mk create mode 100644 components/log/log.c diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 74028b6e9..8d5f66721 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -1,33 +1,3 @@ menu "Bootloader config" -choice BOOTLOADER_LOG_LEVEL - bool "Bootloader log verbosity" - default BOOTLOADER_LOG_LEVEL_NOTICE - help - Specify how much output to see in the bootloader logs. - - Note that if MTDO is HIGH on reset, all early boot output - (including bootloader logs) are suppressed. -config BOOTLOADER_LOG_LEVEL_NONE - bool "No output" -config BOOTLOADER_LOG_LEVEL_ERROR - bool "Error" -config BOOTLOADER_LOG_LEVEL_WARN - bool "Warning" -config BOOTLOADER_LOG_LEVEL_INFO - bool "Info" -config BOOTLOADER_LOG_LEVEL_NOTICE - bool "Notice" -config BOOTLOADER_LOG_LEVEL_DEBUG - bool "Debug" -endchoice - -config BOOTLOADER_LOG_COLORS - bool "Use ANSI terminal colors in bootloader log output" - default "y" - help - Enable ANSI terminal color codes in bootloader output. - - In order to view these, your terminal program must support ANSI color codes. - endmenu diff --git a/components/bootloader/src/Makefile b/components/bootloader/src/Makefile index b6b0c1af0..065593ccb 100644 --- a/components/bootloader/src/Makefile +++ b/components/bootloader/src/Makefile @@ -4,7 +4,7 @@ # PROJECT_NAME := bootloader -COMPONENTS := esptool_py bootloader +COMPONENTS := esptool_py bootloader log # The bootloader pseudo-component is also included in this build, for its Kconfig.projbuild to be included. # @@ -12,6 +12,6 @@ COMPONENTS := esptool_py bootloader IS_BOOTLOADER_BUILD := 1 #We cannot include the esp32 component directly but we need its includes. This is fixed by -#adding it in the main/Makefile directory. +EXTRA_CFLAGS := -D BOOTLOADER_BUILD=1 -I $(IDF_PATH)/components/esp32/include include $(IDF_PATH)/make/project.mk diff --git a/components/bootloader/src/main/bootloader_log.h b/components/bootloader/src/main/bootloader_log.h deleted file mode 100644 index 1f7ec62ad..000000000 --- a/components/bootloader/src/main/bootloader_log.h +++ /dev/null @@ -1,114 +0,0 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef __BOOT_LOG_H__ -#define __BOOT_LOG_H__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "sdkconfig.h" - -#define BOOT_LOG_LEVEL_NONE (0) -#define BOOT_LOG_LEVEL_ERROR (1) -#define BOOT_LOG_LEVEL_WARN (2) -#define BOOT_LOG_LEVEL_INFO (3) -#define BOOT_LOG_LEVEL_NOTICE (4) -#define BOOT_LOG_LEVEL_DEBUG (5) - -#define Black "30" -#define Red "31" -#define Green "32" -#define Brown "33" -#define Blue "34" -#define Purple "35" -#define Cyan "36" - -#if CONFIG_BOOTLOADER_LOG_COLORS -#define LOG_COLOR(COLOR) "\033[0;"COLOR"m" -#define LOG_BOLD(COLOR) "\033[1;"COLOR"m" -#define LOG_RESET_COLOR "\033[0m" -#else -#define LOG_COLOR(...) -#define LOG_BOLD(...) -#define LOG_RESET_COLOR "" -#endif - -// BOOT_LOG_LEVEL defined by make menuconfig -#if CONFIG_BOOTLOADER_LOG_LEVEL_NONE -#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_NONE -#elif CONFIG_BOOTLOADER_LOG_LEVEL_ERROR -#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_ERROR -#elif CONFIG_BOOTLOADER_LOG_LEVEL_WARN -#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_WARN -#elif CONFIG_BOOTLOADER_LOG_LEVEL_INFO -#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_INFO -#elif CONFIG_BOOTLOADER_LOG_LEVEL_NOTICE -#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_NOTICE -#elif CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG -#define BOOT_LOG_LEVEL BOOT_LOG_LEVEL_DEBUG -#else -#error "No bootloader log level set in menuconfig!" -#endif - -//printf("\033[0;36m[NOTICE][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); -#define log_notice(format, ...) \ - do{\ - if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE){\ - ets_printf(LOG_COLOR(Cyan) format "\r\n", ##__VA_ARGS__); \ - ets_printf(LOG_RESET_COLOR); \ - }\ - }while(0) - -#define log_info(format, ...) \ - do{\ - if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_INFO){\ - ets_printf(LOG_BOLD(Cyan) format "\r\n", ##__VA_ARGS__); \ - ets_printf(LOG_RESET_COLOR); \ - }\ - }while(0) - -//printf("\033[0;31m[ERROR][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); -#define log_error(format, ...) \ - do{\ - if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_ERROR){\ - ets_printf(LOG_COLOR(Red) "[ERROR][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ - ets_printf(LOG_RESET_COLOR); \ - }\ - }while(0) - -//printf("\033[1;33m[WARN][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); -#define log_warn(format, ...) \ - do{\ - if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_WARN){\ - ets_printf(LOG_BOLD(Brown) "[WARN][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ - ets_printf(LOG_RESET_COLOR); \ - }\ - }while(0) - -//printf("\033[1;32m[DEBUG][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); -#define log_debug(format, ...) \ - do{\ - if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_DEBUG){\ - ets_printf(LOG_BOLD(Green) "[DEBUG][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ - ets_printf(LOG_RESET_COLOR); \ - }\ - }while(0) - -#ifdef __cplusplus -} -#endif - -#endif /* __BOOT_LOGGING_H__ */ diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c index 2dbf0e826..f56bc5e6b 100644 --- a/components/bootloader/src/main/bootloader_start.c +++ b/components/bootloader/src/main/bootloader_start.c @@ -16,6 +16,7 @@ #include #include "esp_attr.h" +#include "esp_log.h" #include "rom/cache.h" #include "rom/ets_sys.h" @@ -31,11 +32,12 @@ #include "sdkconfig.h" -#include "bootloader_log.h" #include "bootloader_config.h" extern int _bss_start; extern int _bss_end; + +static const char* TAG = "boot"; /* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized, flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C. @@ -130,7 +132,7 @@ uint32_t get_bin_len(uint32_t pos) { uint32_t len = 8 + 16; uint8_t i; - log_debug("pos %d %x\n",pos,*(uint8_t *)pos); + ESP_LOGD(TAG, "pos %d %x",pos,*(uint8_t *)pos); if(0xE9 != *(uint8_t *)pos) { return 0; } @@ -142,7 +144,7 @@ uint32_t get_bin_len(uint32_t pos) } else { len += 16; } - log_debug("bin length = %d\n", len); + ESP_LOGD(TAG, "bin length = %d", len); return len; } @@ -161,7 +163,7 @@ void boot_cache_redirect( uint32_t pos, size_t size ) uint32_t count = (size + 0xffff) / 0x10000; Cache_Read_Disable( 0 ); Cache_Flush( 0 ); - log_debug( "mmu set paddr=%08x count=%d", pos_aligned, count ); + ESP_LOGD(TAG, "mmu set paddr=%08x count=%d", pos_aligned, count ); cache_flash_mmu_set( 0, 0, 0x3f400000, pos_aligned, 64, count ); Cache_Read_Enable( 0 ); } @@ -183,13 +185,13 @@ bool load_partition_table(bootloader_state_t* bs, uint32_t addr) int index = 0; char *partition_usage; - log_info("Partition Table:"); - log_info("## Label Usage Type ST Offset Length"); + ESP_LOGI(TAG, "Partition Table:"); + ESP_LOGI(TAG, "## Label Usage Type ST Offset Length"); while (addr < end) { - log_debug("load partition table entry from %x(%08x)", addr, MEM_CACHE(addr)); + ESP_LOGD(TAG, "load partition table entry from %x(%08x)", addr, MEM_CACHE(addr)); memcpy(&partition, MEM_CACHE(addr), sizeof(partition)); - log_debug("type=%x subtype=%x", partition.type, partition.subtype); + ESP_LOGD(TAG, "type=%x subtype=%x", partition.type, partition.subtype); partition_usage = "unknown"; if (partition.magic == PARTITION_MAGIC) { /* valid partition definition */ @@ -244,14 +246,14 @@ bool load_partition_table(bootloader_state_t* bs, uint32_t addr) } /* print partition type info */ - log_info("%2d %-16s %-16s %02x %02x %08x %08x", index, partition.label, partition_usage, + ESP_LOGI(TAG, "%2d %-16s %-16s %02x %02x %08x %08x", index, partition.label, partition_usage, partition.type, partition.subtype, partition.pos.offset, partition.pos.size); index++; addr += sizeof(partition); } - log_info("End of partition table"); + ESP_LOGI(TAG,"End of partition table"); return true; } @@ -274,14 +276,7 @@ static bool ota_select_valid(const ota_select *s) void bootloader_main() { - //Run start routine. - /*ESP32 2ND bootload start here*/ - log_info( "\n" ); - log_info( "**************************************" ); - log_info( "* hello espressif ESP32! *" ); - log_info( "* 2nd boot is running! *" ); - log_info( "* version (%s) *", BOOT_VERSION); - log_info( "**************************************"); + ESP_LOGI(TAG, "Espressif ESP32 2nd stage bootloader v. %s", BOOT_VERSION); struct flash_hdr fhdr; bootloader_state_t bs; @@ -289,7 +284,7 @@ void bootloader_main() ota_select sa,sb; memset(&bs, 0, sizeof(bs)); - log_notice( "compile time %s\n", __TIME__ ); + ESP_LOGI(TAG, "compile time " __TIME__ ); /* close watch dog here */ REG_CLR_BIT( RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN ); REG_CLR_BIT( WDTCONFIG0(0), TIMERS_WDT_FLASHBOOT_MOD_EN ); @@ -302,14 +297,14 @@ void bootloader_main() print_flash_info(&fhdr); if (!load_partition_table(&bs, PARTITION_ADD)) { - log_error("load partition table error!"); + ESP_LOGE(TAG, "load partition table error!"); return; } partition_pos_t load_part_pos; if (bs.ota_info.offset != 0) { // check if partition table has OTA info partition - //log_error("OTA info sector handling is not implemented"); + //ESP_LOGE("OTA info sector handling is not implemented"); boot_cache_redirect(bs.ota_info.offset, bs.ota_info.size ); memcpy(&sa,MEM_CACHE(bs.ota_info.offset & 0x0000ffff),sizeof(sa)); memcpy(&sb,MEM_CACHE((bs.ota_info.offset + 0x1000)&0x0000ffff) ,sizeof(sb)); @@ -325,13 +320,13 @@ void bootloader_main() spiRet1 = SPIEraseSector(bs.ota_info.offset/0x1000); spiRet2 = SPIEraseSector(bs.ota_info.offset/0x1000+1); if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) { - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return; } spiRet1 = SPIWrite(bs.ota_info.offset,(uint32_t *)&sa,sizeof(ota_select)); spiRet2 = SPIWrite(bs.ota_info.offset + 0x1000,(uint32_t *)&sb,sizeof(ota_select)); if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) { - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return; } Cache_Read_Enable(0); @@ -344,7 +339,7 @@ void bootloader_main() }else if(ota_select_valid(&sb)) { load_part_pos = bs.ota[(sb.ota_seq - 1) % bs.app_count]; }else { - log_error("ota data partition info error"); + ESP_LOGE(TAG, "ota data partition info error"); return; } } @@ -353,15 +348,15 @@ void bootloader_main() } else if (bs.test.offset != 0) { // otherwise, look for test app parition load_part_pos = bs.test; } else { // nothing to load, bail out - log_error("nothing to load"); + ESP_LOGE(TAG, "nothing to load"); return; } - log_info("Loading app partition at offset %08x", load_part_pos); + ESP_LOGI(TAG, "Loading app partition at offset %08x", load_part_pos); if(fhdr.secury_boot_flag == 0x01) { /* protect the 2nd_boot */ if(false == secure_boot()){ - log_error("secure boot failed"); + ESP_LOGE(TAG, "secure boot failed"); return; } } @@ -369,7 +364,7 @@ void bootloader_main() if(fhdr.encrypt_flag == 0x01) { /* encrypt flash */ if (false == flash_encrypt(&bs)) { - log_error("flash encrypt failed"); + ESP_LOGE(TAG, "flash encrypt failed"); return; } } @@ -395,7 +390,7 @@ void unpack_load_app(const partition_pos_t* partition) uint32_t irom_load_addr = 0; uint32_t irom_size = 0; - log_debug("bin_header: %u %u %u %u %08x\n", image_header.magic, + ESP_LOGD(TAG, "bin_header: %u %u %u %u %08x", image_header.magic, image_header.blocks, image_header.spi_mode, image_header.spi_size, @@ -420,7 +415,7 @@ void unpack_load_app(const partition_pos_t* partition) } if (address >= DROM_LOW && address < DROM_HIGH) { - log_debug("found drom section, map from %08x to %08x\n", pos, + ESP_LOGD(TAG, "found drom section, map from %08x to %08x", pos, section_header.load_addr); drom_addr = partition->offset + pos - sizeof(section_header); drom_load_addr = section_header.load_addr; @@ -430,7 +425,7 @@ void unpack_load_app(const partition_pos_t* partition) } if (address >= IROM_LOW && address < IROM_HIGH) { - log_debug("found irom section, map from %08x to %08x\n", pos, + ESP_LOGD(TAG, "found irom section, map from %08x to %08x", pos, section_header.load_addr); irom_addr = partition->offset + pos - sizeof(section_header); irom_load_addr = section_header.load_addr; @@ -439,7 +434,7 @@ void unpack_load_app(const partition_pos_t* partition) map = true; } - log_notice("section %d: paddr=0x%08x vaddr=0x%08x size=0x%05x (%6d) %s", section_index, pos, section_header.load_addr, section_header.data_len, section_header.data_len, (load)?"load":(map)?"map":""); + ESP_LOGI(TAG, "section %d: paddr=0x%08x vaddr=0x%08x size=0x%05x (%6d) %s", section_index, pos, section_header.load_addr, section_header.data_len, section_header.data_len, (load)?"load":(map)?"map":""); if (!load) { pos += section_header.data_len; @@ -468,29 +463,29 @@ void IRAM_ATTR set_cache_and_start_app( uint32_t irom_size, uint32_t entry_addr) { - log_debug("configure drom and irom and start\n"); + ESP_LOGD(TAG, "configure drom and irom and start"); Cache_Read_Disable( 0 ); Cache_Read_Disable( 1 ); Cache_Flush( 0 ); Cache_Flush( 1 ); uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k - log_debug( "d mmu set paddr=%08x vaddr=%08x size=%d n=%d \n", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count ); + ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count ); int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count ); - log_debug( "rc=%d", rc ); + ESP_LOGV(TAG, "rc=%d", rc ); rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count ); - log_debug( "rc=%d", rc ); + ESP_LOGV(TAG, "rc=%d", rc ); uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k - log_debug( "i mmu set paddr=%08x vaddr=%08x size=%d n=%d\n", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count ); + ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count ); rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); - log_debug( "rc=%d", rc ); + ESP_LOGV(TAG, "rc=%d", rc ); rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); - log_debug( "rc=%d", rc ); + ESP_LOGV(TAG, "rc=%d", rc ); REG_CLR_BIT( PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 ); REG_CLR_BIT( APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 ); Cache_Read_Enable( 0 ); Cache_Read_Enable( 1 ); - log_notice("start: 0x%08x\n", entry_addr); + ESP_LOGD(TAG, "start: 0x%08x", entry_addr); typedef void (*entry_t)(void); entry_t entry = ((entry_t) entry_addr); @@ -506,11 +501,11 @@ void print_flash_info(struct flash_hdr* pfhdr) struct flash_hdr fhdr = *pfhdr; - log_debug( "[D]: magic %02x\n", fhdr.magic ); - log_debug( "[D]: blocks %02x\n", fhdr.blocks ); - log_debug( "[D]: spi_mode %02x\n", fhdr.spi_mode ); - log_debug( "[D]: spi_speed %02x\n", fhdr.spi_speed ); - log_debug( "[D]: spi_size %02x\n", fhdr.spi_size ); + ESP_LOGD(TAG, "magic %02x", fhdr.magic ); + ESP_LOGD(TAG, "blocks %02x", fhdr.blocks ); + ESP_LOGD(TAG, "spi_mode %02x", fhdr.spi_mode ); + ESP_LOGD(TAG, "spi_speed %02x", fhdr.spi_speed ); + ESP_LOGD(TAG, "spi_size %02x", fhdr.spi_size ); const char* str; switch ( fhdr.spi_speed ) { @@ -534,7 +529,7 @@ void print_flash_info(struct flash_hdr* pfhdr) str = "20MHz"; break; } - log_notice( " SPI Speed : %s", str ); + ESP_LOGI(TAG, "SPI Speed : %s", str ); @@ -566,7 +561,7 @@ void print_flash_info(struct flash_hdr* pfhdr) str = "DIO"; break; } - log_notice( " SPI Mode : %s", str ); + ESP_LOGI(TAG, "SPI Mode : %s", str ); @@ -595,6 +590,6 @@ void print_flash_info(struct flash_hdr* pfhdr) str = "1MB"; break; } - log_notice( " SPI Flash Size : %s", str ); + ESP_LOGI(TAG, "SPI Flash Size : %s", str ); #endif } diff --git a/components/bootloader/src/main/component.mk b/components/bootloader/src/main/component.mk index 1671095f1..8c8ea4cb6 100644 --- a/components/bootloader/src/main/component.mk +++ b/components/bootloader/src/main/component.mk @@ -8,6 +8,5 @@ # COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T esp32.bootloader.ld -T $(IDF_PATH)/components/esp32/ld/esp32.rom.ld -COMPONENT_EXTRA_INCLUDES := $(IDF_PATH)/components/esp32/include include $(IDF_PATH)/make/component_common.mk diff --git a/components/bootloader/src/main/flash_encrypt.c b/components/bootloader/src/main/flash_encrypt.c index d5f105f9c..9e774e087 100644 --- a/components/bootloader/src/main/flash_encrypt.c +++ b/components/bootloader/src/main/flash_encrypt.c @@ -16,6 +16,7 @@ #include "esp_types.h" #include "esp_attr.h" +#include "esp_log.h" #include "rom/cache.h" #include "rom/ets_sys.h" @@ -28,13 +29,14 @@ #include "sdkconfig.h" -#include "bootloader_log.h" #include "bootloader_config.h" +static const char* TAG = "flash_encrypt"; + /** * @function : bitcount - * @description: caculate bit 1 in flash_crypt_cnt - * if it's even number ,need encrypt flash data,and burn efuse + * @description: calculate bit 1 in flash_crypt_cnt + * if it's even number, need encrypt flash data, and burn efuse * * @inputs: n flash_crypt_cnt * @return: number of 1 in flash_crypt_cnt @@ -68,19 +70,19 @@ bool flash_encrypt_write(uint32_t pos, uint32_t len) spiRet = SPIRead(pos, buf, SPI_SEC_SIZE); if (spiRet != SPI_FLASH_RESULT_OK) { Cache_Read_Enable(0); - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return false; } spiRet = SPIEraseSector(pos/SPI_SEC_SIZE); if (spiRet != SPI_FLASH_RESULT_OK) { Cache_Read_Enable(0); - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return false; } spiRet = SPI_Encrypt_Write(pos, buf, SPI_SEC_SIZE); if (spiRet != SPI_FLASH_RESULT_OK) { Cache_Read_Enable(0); - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return false; } pos += SPI_SEC_SIZE; @@ -104,53 +106,53 @@ bool flash_encrypt(bootloader_state_t *bs) uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0, EFUSE_FLASH_CRYPT_CNT); uint8_t count = bitcount(flash_crypt_cnt); int i = 0; - log_debug("flash crypt cnt %x, count %d\n", flash_crypt_cnt, count); + ESP_LOGD(TAG, "flash encrypt cnt %x, bitcount %d\n", flash_crypt_cnt, count); if ((count % 2) == 0) { boot_cache_redirect( 0, 64*1024); /* encrypt iv and abstruct */ - if (false == flash_encrypt_write(0,SPI_SEC_SIZE)) { - log_error("encrypt iv and abstruct error"); + if (false == flash_encrypt_write(0, SPI_SEC_SIZE)) { + ESP_LOGE(TAG, "encrypt iv and abstract error"); return false; } /* encrypt write boot bin*/ bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000)); if(bin_len != 0) { - if (false == flash_encrypt_write(0x1000,bin_len)) { - log_error("encrypt 2nd boot error"); + if (false == flash_encrypt_write(0x1000, bin_len)) { + ESP_LOGE(TAG, "encrypt 2nd boot error"); return false; } } else { - log_error("2nd boot len error"); + ESP_LOGE(TAG, "2nd boot len error"); return false; } /* encrypt partition table */ - if (false == flash_encrypt_write(PARTITION_ADD,SPI_SEC_SIZE)) { - log_error("encrypt partition table error"); + if (false == flash_encrypt_write(PARTITION_ADD, SPI_SEC_SIZE)) { + ESP_LOGE(TAG, "encrypt partition table error"); return false; } /* encrypt write factory bin */ if(bs->factory.offset != 0x00) { - log_debug("have factory bin\n"); - boot_cache_redirect(bs->factory.offset,bs->factory.size); + ESP_LOGD(TAG, "have factory bin\n"); + boot_cache_redirect(bs->factory.offset, bs->factory.size); bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->factory.offset&0xffff)); if(bin_len != 0) { - if (false == flash_encrypt_write(bs->factory.offset,bin_len)) { - log_error("encrypt factory bin error"); + if (false == flash_encrypt_write(bs->factory.offset, bin_len)) { + ESP_LOGE(TAG, "encrypt factory bin error"); return false; } } } /* encrypt write test bin */ if(bs->test.offset != 0x00) { - ets_printf("have test bin\n"); - boot_cache_redirect(bs->test.offset,bs->test.size); + ESP_LOGD(TAG, "have test bin\n"); + boot_cache_redirect(bs->test.offset, bs->test.size); bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->test.offset&0xffff)); if(bin_len != 0) { - if (false == flash_encrypt_write(bs->test.offset,bin_len)) { - log_error("encrypt test bin error"); + if (false == flash_encrypt_write(bs->test.offset, bin_len)) { + ESP_LOGE(TAG, "encrypt test bin error"); return false; } } @@ -158,33 +160,33 @@ bool flash_encrypt(bootloader_state_t *bs) /* encrypt write ota bin */ for (i = 0;i<16;i++) { if(bs->ota[i].offset != 0x00) { - log_debug("have ota[%d] bin\n",i); - boot_cache_redirect(bs->ota[i].offset,bs->ota[i].size); + ESP_LOGD(TAG, "have ota[%d] bin\n",i); + boot_cache_redirect(bs->ota[i].offset, bs->ota[i].size); bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->ota[i].offset&0xffff)); if(bin_len != 0) { - if (false == flash_encrypt_write(bs->ota[i].offset,bin_len)) { - log_error("encrypt ota bin error"); + if (false == flash_encrypt_write(bs->ota[i].offset, bin_len)) { + ESP_LOGE(TAG, "encrypt ota bin error"); return false; } } } } /* encrypt write ota info bin */ - if (false == flash_encrypt_write(bs->ota_info.offset,2*SPI_SEC_SIZE)) { - log_error("encrypt ota binfo error"); + if (false == flash_encrypt_write(bs->ota_info.offset, 2*SPI_SEC_SIZE)) { + ESP_LOGE(TAG, "encrypt ota info error"); return false; } REG_SET_FIELD(EFUSE_BLK0_WDATA0, EFUSE_FLASH_CRYPT_CNT, 0x04); REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */ REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */ while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */ - log_warn("burn flash_crypt_cnt\n"); + ESP_LOGW(TAG, "burn flash_crypt_cnt"); REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */ REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */ while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */ return true; } else { - log_info("flash already encrypted.\n"); + ESP_LOGI(TAG, "flash already encrypted."); return true; } } diff --git a/components/bootloader/src/main/secure_boot.c b/components/bootloader/src/main/secure_boot.c index 97ddd1a8d..0e7d581d9 100644 --- a/components/bootloader/src/main/secure_boot.c +++ b/components/bootloader/src/main/secure_boot.c @@ -16,6 +16,7 @@ #include "esp_attr.h" #include "esp_types.h" +#include "esp_log.h" #include "rom/cache.h" #include "rom/ets_sys.h" @@ -29,12 +30,13 @@ #include "sdkconfig.h" -#include "bootloader_log.h" #include "bootloader_config.h" +static const char* TAG = "secure_boot"; + /** * @function : secure_boot_generate - * @description: generate boot abstruct & iv + * @description: generate boot abstract & iv * * @inputs: bool */ @@ -53,17 +55,17 @@ bool secure_boot_generate(uint32_t bin_len){ spiRet = SPIEraseSector(0); if (spiRet != SPI_FLASH_RESULT_OK) { - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return false; } /* write iv to flash, 0x0000, 128 bytes (1024 bits) */ spiRet = SPIWrite(0, buf, 128); if (spiRet != SPI_FLASH_RESULT_OK) { - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return false; } - log_debug("write iv to flash.\n"); + ESP_LOGD(TAG, "write iv to flash."); Cache_Read_Enable(0); /* read 4K code image from flash, for test */ for (i = 0; i < bin_len; i+=128) { @@ -77,10 +79,10 @@ bool secure_boot_generate(uint32_t bin_len){ /* write abstract to flash, 0x0080, 64 bytes (512 bits) */ spiRet = SPIWrite(0x80, buf, 64); if (spiRet != SPI_FLASH_RESULT_OK) { - log_error(SPI_ERROR_LOG); + ESP_LOGE(TAG, SPI_ERROR_LOG); return false; } - log_debug("write abstract to flash.\n"); + ESP_LOGD(TAG, "write abstract to flash."); Cache_Read_Enable(0); return true; } @@ -88,7 +90,7 @@ bool secure_boot_generate(uint32_t bin_len){ /** * @function : secure_boot - * @description: protect boot code inflash + * @description: protect boot code in flash * * @inputs: bool */ @@ -96,17 +98,17 @@ bool secure_boot(void){ uint32_t bin_len = 0; if (REG_READ(EFUSE_BLK0_RDATA6) & EFUSE_RD_ABS_DONE_0) { - log_info("already secure boot !\n"); + ESP_LOGD(TAG, "already secure boot !"); return true; } else { boot_cache_redirect( 0, 64*1024); bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000)); if (bin_len == 0) { - log_error("boot len is error"); + ESP_LOGE(TAG, "boot len is error"); return false; } if (false == secure_boot_generate(bin_len)){ - log_error("secure boot generate failed"); + ESP_LOGE(TAG, "secure boot generate failed"); return false; } } @@ -115,11 +117,11 @@ bool secure_boot(void){ REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */ REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */ while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */ - log_warn("burn abstract_done_0\n"); + ESP_LOGI(TAG, "burn abstract_done_0"); REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */ REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */ while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */ - log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6)); + ESP_LOGD(TAG, "read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6)); return true; } diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index e1a5f027b..cfc628b12 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -39,11 +39,11 @@ #include "esp_event.h" #include "esp_spi_flash.h" #include "esp_ipc.h" +#include "esp_log.h" static void IRAM_ATTR user_start_cpu0(void); static void IRAM_ATTR call_user_start_cpu1(); static void IRAM_ATTR user_start_cpu1(void); -void Cache_Read_Enable(); extern void ets_setup_syscalls(void); @@ -57,6 +57,8 @@ extern int _iram_romjumptable_end; extern int _iram_text_start; extern int _iram_text_end; +static const char* TAG = "cpu_start"; + /* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized, flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C. @@ -110,13 +112,13 @@ void IRAM_ATTR call_user_start_cpu0() { memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); - //Initialize heap allocator + // Initialize heap allocator heap_alloc_caps_init(); - ets_printf("Pro cpu up.\n"); + ESP_EARLY_LOGI(TAG, "Pro cpu up."); #ifndef CONFIG_FREERTOS_UNICORE - ets_printf("Starting app cpu, entry point is %p\n", call_user_start_cpu1); + ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1); SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN); CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL); @@ -128,9 +130,10 @@ void IRAM_ATTR call_user_start_cpu0() { ets_delay_us(100); } #else + ESP_EARLY_LOGI(TAG, "Single core mode"); CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN); #endif - ets_printf("Pro cpu start user code\n"); + ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); user_start_cpu0(); } @@ -173,7 +176,7 @@ void IRAM_ATTR call_user_start_cpu1() { "isync\n" \ :::"a4","a5"); - ets_printf("App cpu up.\n"); + ESP_EARLY_LOGI(TAG, "App cpu up."); app_cpu_started = 1; user_start_cpu1(); } @@ -185,7 +188,7 @@ void IRAM_ATTR user_start_cpu1(void) { while (port_xSchedulerRunning[0] == 0) { ; } - ets_printf("Starting scheduler on APP CPU.\n"); + ESP_LOGI(TAG, "Starting scheduler on APP CPU."); xPortStartScheduler(); } @@ -201,7 +204,7 @@ static void do_global_ctors(void) { extern esp_err_t app_main(void *ctx); void user_start_cpu0(void) { - ets_setup_syscalls(); + ets_setup_syscalls(); do_global_ctors(); esp_ipc_init(); spi_flash_init(); @@ -209,7 +212,7 @@ void user_start_cpu0(void) { #if CONFIG_WIFI_ENABLED esp_err_t ret = nvs_flash_init(5, 3); if (ret != ESP_OK) { - printf("nvs_flash_init failed, ret=%d\n", ret); + ESP_LOGE(TAG, "nvs_flash_init failed, ret=%d", ret); } system_init(); @@ -226,7 +229,7 @@ void user_start_cpu0(void) { app_main(NULL); #endif - ets_printf("Starting scheduler on PRO CPU.\n"); + ESP_LOGI(TAG, "Starting scheduler on PRO CPU."); vTaskStartScheduler(); } diff --git a/components/esp32/heap_alloc_caps.c b/components/esp32/heap_alloc_caps.c index e816175b9..5b3ec33db 100644 --- a/components/esp32/heap_alloc_caps.c +++ b/components/esp32/heap_alloc_caps.c @@ -17,6 +17,9 @@ #include "heap_alloc_caps.h" #include "spiram.h" +#include "esp_log.h" + +static const char* TAG = "heap_alloc_caps"; /* This file, combined with a region allocator that supports tags, solves the problem that the ESP32 has RAM that's @@ -147,7 +150,7 @@ static void disable_mem_region(void *from, void *to) { regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from; } else if (regStartto) { //Range punches a hole in the region! We do not support this. - ets_printf("%s: region %d: hole punching is not supported!\n", i); + ESP_EARLY_LOGE(TAG, "region %d: hole punching is not supported!", i); regions[i].xTag=-1; //Just disable memory region. That'll teach them! } } @@ -204,12 +207,13 @@ void heap_alloc_caps_init() { } } -#if 1 //Change to 1 to show the regions the heap allocator is initialized with. - ets_printf("Initializing heap allocator:\n"); + ESP_EARLY_LOGI(TAG, "Initializing heap allocator:"); for (i=0; regions[i].xSizeInBytes!=0; i++) { - if ( regions[i].xTag != -1 ) ets_printf("Region %02d: %08X len %08X tag %d\n", i, (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag); + if (regions[i].xTag != -1) { + ESP_EARLY_LOGI(TAG, "Region %02d: %08X len %08X tag %d", i, + (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag); + } } -#endif //Initialize the malloc implementation. vPortDefineHeapRegionsTagged( regions ); } diff --git a/components/log/Kconfig b/components/log/Kconfig new file mode 100644 index 000000000..1627ea183 --- /dev/null +++ b/components/log/Kconfig @@ -0,0 +1,48 @@ +menu "Log output" + +choice LOG_DEFAULT_LEVEL + bool "Default log verbosity" + default LOG_DEFAULT_LEVEL_INFO + help + Specify how much output to see in logs by default. + You can set lower verbosity level at runtime using + esp_log_level_set function. + + Note that this setting limits which log statements + are compiled into the program. So setting this to, say, + "Warning" would mean that changing log level to "Debug" + at runtime will not be possible. + +config LOG_DEFAULT_LEVEL_NONE + bool "No output" +config LOG_DEFAULT_LEVEL_ERROR + bool "Error" +config LOG_DEFAULT_LEVEL_WARN + bool "Warning" +config LOG_DEFAULT_LEVEL_INFO + bool "Info" +config LOG_DEFAULT_LEVEL_DEBUG + bool "Debug" +config LOG_DEFAULT_LEVEL_VERBOSE + bool "Verbose" +endchoice + +config LOG_DEFAULT_LEVEL + int + default 0 if LOG_DEFAULT_LEVEL_NONE + default 1 if LOG_DEFAULT_LEVEL_ERROR + default 2 if LOG_DEFAULT_LEVEL_WARN + default 3 if LOG_DEFAULT_LEVEL_INFO + default 4 if LOG_DEFAULT_LEVEL_DEBUG + default 5 if LOG_DEFAULT_LEVEL_VERBOSE + +config LOG_COLORS + bool "Use ANSI terminal colors in log output" + default "y" + help + Enable ANSI terminal color codes in bootloader output. + + In order to view these, your terminal program must support ANSI color codes. + + +endmenu diff --git a/components/log/component.mk b/components/log/component.mk new file mode 100755 index 000000000..ef497a7ec --- /dev/null +++ b/components/log/component.mk @@ -0,0 +1,3 @@ +COMPONENT_ADD_INCLUDEDIRS := include + +include $(IDF_PATH)/make/component_common.mk diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h index e8ecf875b..32f6d0bb3 100644 --- a/components/log/include/esp_log.h +++ b/components/log/include/esp_log.h @@ -16,6 +16,8 @@ #define __ESP_LOG_H__ #include +#include +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -24,6 +26,20 @@ extern "C" { /** * @brief Logging library * + * Log library has two ways of managing log verbosity: compile time, set via + * menuconfig, and runtime, using esp_log_set_level function. + * + * At compile time, filtering is done using CONFIG_LOG_DEFAULT_LEVEL macro, set via + * menuconfig. All logging statments for levels higher than CONFIG_LOG_DEFAULT_LEVEL + * will be removed by the preprocessor. + * + * At run time, all logs below CONFIG_LOG_DEFAULT_LEVEL are enabled by default. + * esp_log_set_level function may be used to set logging level per module. + * Modules are identified by their tags, which are human-readable ASCII + * zero-terminated strings. + * + * How to use this library: + * * In each C file which uses logging functionality, define TAG variable like this: * * static const char* TAG = "MyModule"; @@ -32,31 +48,46 @@ extern "C" { * * ESP_LOGW(TAG, "Baud rate error %.1f%%. Requested: %d baud, actual: %d baud", error * 100, baud_req, baud_real); * - * Log filtering happens both at compile time and at runtime. + * Several macros are available for different verbosity levels: * - * At compile time, filtering is done using CONFIG_ESP_LOG_LEVEL macro, set via menuconfig. - * All logging statments for levels higher than CONFIG_ESP_LOG_LEVEL will be removed by the preprocessor. + * ESP_LOGE — error + * ESP_LOGW — warning + * ESP_LOGI — info + * ESP_LOGD - debug + * ESP_LOGV - verbose * - * At run time, all logs below CONFIG_ESP_LOG_LEVEL are enabled by default. - * esp_log_set function may be used to set logging level per tag. + * Additionally there is an _EARLY_ variant for each of these macros (e.g. ESP_EARLY_LOGE). + * These variants can run in startup code, before heap allocator and syscalls + * have been initialized. + * When compiling bootloader, normal ESP_LOGx macros fall back to the same implementation + * as ESP_EARLY_LOGx macros. So the only place where ESP_EARLY_LOGx have to be used explicitly + * is the early startup code, such as heap allocator initialization code. * - * esp_log_set("*", ESP_LOG_ERROR); // set all components to ERROR level - * esp_log_set("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack - * esp_log_set("dhcpc", ESP_LOG_INFO); // enable INFO logs from DHCP client + * (Note that such distinction would not have been necessary if we would have an + * ets_vprintf function in the ROM. Then it would be possible to switch implementation + * from _EARLY version to normal version on the fly. Unfortunately, ets_vprintf in ROM + * has been inlined by the compiler into ets_printf, so it is not accessible outside.) * * + * To configure logging output per module, add calls to esp_log_set_level function: + * + * esp_log_set_level("*", ESP_LOG_ERROR); // set all components to ERROR level + * esp_log_set_level("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack + * esp_log_set_level("dhcpc", ESP_LOG_INFO); // enable INFO logs from DHCP client + * */ typedef enum { - ESP_LOG_NONE, - ESP_LOG_ERROR, - ESP_LOG_WARN, - ESP_LOG_INFO, - ESP_LOG_DEBUG, - ESP_LOG_VERBOSE + ESP_LOG_NONE, // No log output + ESP_LOG_ERROR, // Critical errors, software module can not recover on its own + ESP_LOG_WARN, // Error conditions from which recovery measures have been taken + ESP_LOG_INFO, // Information messages which describe normal flow of events + ESP_LOG_DEBUG, // Extra information which is not necessary for normal use (values, pointers, sizes, etc). + ESP_LOG_VERBOSE // Bigger chunks of debugging information, or frequent messages which can potentially flood the output. } esp_log_level_t; +typedef int (*vprintf_like_t)(const char *, va_list); /** * @brief Set log level for given tag @@ -64,52 +95,134 @@ typedef enum { * If logging for given component has already been enabled, changes previous setting. * * @param tag Tag of the log entries to enable. Must be a non-NULL zero terminated string. - * Value "*" means that all tags are affected. + * Value "*" resets log level for all tags to the given value. * * @param level Selects log level to enable. Only logs at this and lower levels will be shown. */ -void esp_log_set(const char* tag, esp_log_level_t level); +void esp_log_level_set(const char* tag, esp_log_level_t level); + +/** + * @brief Set function used to output log entries + * + * By default, log output goes to UART0. This function can be used to redirect log + * output to some other destination, such as file or network. + * + * @param func Function used for output. Must have same signature as vprintf. + */ +void esp_log_set_vprintf(vprintf_like_t func); /** * @brief Write message into the log * * This function is not intended to be used directly. Instead, use one of * ESP_LOGE, ESP_LOGW, ESP_LOGI, ESP_LOGD, ESP_LOGV macros. + * + * This function or these macros should not be used from an interrupt. */ void esp_log_write(esp_log_level_t level, const char* tag, const char* format, ...) __attribute__ ((format (printf, 3, 4))); -#ifndef CONFIG_ESP_LOG_LEVEL -#define CONFIG_ESP_LOG_LEVEL ESP_LOG_NONE -#endif -#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_ERROR) -#define ESP_LOGE( tag, format, ... ) esp_log_write(ESP_LOG_ERROR, tag, format, ##__VA_ARGS__) + +/** + * @brief Function which returns timestamp to be used in log output + * + * This function is used in expansion of ESP_LOGx macros. + * In the 2nd stage bootloader, and at early application startup stage + * this function uses CPU cycle counter as time source. Later when + * FreeRTOS scheduler start running, it switches to FreeRTOS tick count. + * + * For now, we ignore millisecond counter overflow. + * + * @return timestamp, in milliseconds + */ +uint32_t esp_log_timestamp(); + + +#if CONFIG_LOG_COLORS +#define LOG_COLOR_BLACK "30" +#define LOG_COLOR_RED "31" +#define LOG_COLOR_GREEN "32" +#define LOG_COLOR_BROWN "33" +#define LOG_COLOR_BLUE "34" +#define LOG_COLOR_PURPLE "35" +#define LOG_COLOR_CYAN "36" +#define LOG_COLOR(COLOR) "\033[0;"COLOR"m" +#define LOG_BOLD(COLOR) "\033[1;"COLOR"m" +#define LOG_RESET_COLOR "\033[0m" +#define LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED) +#define LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN) +#define LOG_COLOR_I LOG_COLOR(LOG_COLOR_GREEN) +#define LOG_COLOR_D +#define LOG_COLOR_V +#else //CONFIG_LOG_COLORS +#define LOG_COLOR_E +#define LOG_COLOR_W +#define LOG_COLOR_I +#define LOG_COLOR_D +#define LOG_COLOR_V +#define LOG_RESET_COLOR +#endif //CONFIG_LOG_COLORS + +#define LOG_FORMAT(letter, format) LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n" + +#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_ERROR) +#define ESP_EARLY_LOGE( tag, format, ... ) ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#ifndef BOOTLOADER_BUILD +#define ESP_LOGE( tag, format, ... ) esp_log_write(ESP_LOG_ERROR, tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#else +#define ESP_LOGE( tag, format, ... ) ESP_EARLY_LOGE( tag, format, ##__VA_ARGS__) +#endif // BOOTLOADER_BUILD #else #define ESP_LOGE( tag, format, ... ) +#define ESP_EARLY_LOGE( tag, format, ... ) #endif -#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_WARN) -#define ESP_LOGW( tag, format, ... ) esp_log_write(ESP_LOG_WARN, tag, format, ##__VA_ARGS__) +#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_WARN) +#define ESP_EARLY_LOGW( tag, format, ... ) ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#ifndef BOOTLOADER_BUILD +#define ESP_LOGW( tag, format, ... ) esp_log_write(ESP_LOG_WARN, tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#else +#define ESP_LOGW( tag, format, ... ) ESP_EARLY_LOGW( tag, format, ##__VA_ARGS__) +#endif // BOOTLOADER_BUILD #else #define ESP_LOGW( tag, format, ... ) +#define ESP_EARLY_LOGW( tag, format, ... ) #endif -#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_INFO) -#define ESP_LOGI( tag, format, ... ) esp_log_write(ESP_LOG_INFO, tag, format, ##__VA_ARGS__) +#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_INFO) +#define ESP_EARLY_LOGI( tag, format, ... ) ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#ifndef BOOTLOADER_BUILD +#define ESP_LOGI( tag, format, ... ) esp_log_write(ESP_LOG_INFO, tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#else +#define ESP_LOGI( tag, format, ... ) ESP_EARLY_LOGI( tag, format, ##__VA_ARGS__) +#endif //BOOTLOADER_BUILD #else #define ESP_LOGI( tag, format, ... ) +#define ESP_EARLY_LOGI( tag, format, ... ) #endif -#if (CONFIG_ESP_LOG_LEVEL < ESP_LOG_DEBUG) -#define ESP_LOGD( tag, format, ... ) esp_log_write(ESP_LOG_DEBUG, tag, format, ##__VA_ARGS__) +#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_DEBUG) +#define ESP_EARLY_LOGD( tag, format, ... ) ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#ifndef BOOTLOADER_BUILD +#define ESP_LOGD( tag, format, ... ) esp_log_write(ESP_LOG_DEBUG, tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#else +#define ESP_LOGD( tag, format, ... ) ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__) +#endif // BOOTLOADER_BUILD #else #define ESP_LOGD( tag, format, ... ) +#define ESP_EARLY_LOGD( tag, format, ... ) #endif -#if (CONFIG_ESP_LOG_VERBOSE < ESP_LOG_ERROR) -#define ESP_LOGV( tag, format, ... ) esp_log_write(ESP_LOG_VERBOSE, tag, format, ##__VA_ARGS__) +#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_VERBOSE) +#define ESP_EARLY_LOGV( tag, format, ... ) ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#ifndef BOOTLOADER_BUILD +#define ESP_LOGV( tag, format, ... ) esp_log_write(ESP_LOG_VERBOSE, tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#else +#define ESP_LOGV( tag, format, ... ) ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__) +#endif // BOOTLOADER_BUILD #else #define ESP_LOGV( tag, format, ... ) +#define ESP_EARLY_LOGV( tag, format, ... ) #endif #ifdef __cplusplus diff --git a/components/log/log.c b/components/log/log.c new file mode 100644 index 000000000..bd6df01b2 --- /dev/null +++ b/components/log/log.c @@ -0,0 +1,283 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/* + * Log library — implementation notes. + * + * Log library stores all tags provided to esp_log_set_level as a linked + * list. See uncached_tag_entry_t structure. + * + * To avoid looking up log level for given tag each time message is + * printed, this library caches pointers to tags. Because the suggested + * way of creating tags uses one 'TAG' constant per file, this caching + * should be effective. Cache is a binary min-heap of cached_tag_entry_t + * items, ordering is done on 'generation' member. In this context, + * generation is an integer which is incremented each time an operation + * with cache is performed. When cache is full, new item is inserted in + * place of an oldest item (that is, with smallest 'generation' value). + * After that, bubble-down operation is performed to fix ordering in the + * min-heap. + * + * The potential problem with wrap-around of cache generation counter is + * ignored for now. This will happen if someone happens to output more + * than 4 billion log entries, at which point wrap-around will not be + * the biggest problem. + * + */ + +#ifndef BOOTLOADER_BUILD +#include +#include +#include +#include +#endif + +#include "esp_attr.h" +#include "xtensa/hal.h" +#include "soc/soc.h" +#include +#include +#include +#include +#include +#include "esp_log.h" + + +#ifndef BOOTLOADER_BUILD + +#define TAG_CACHE_SIZE 32 +#define MAX_MUTEX_WAIT_TICKS ((10 + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS) + +typedef struct { + const char* tag; + uint32_t level : 3; + uint32_t generation : 29; +} cached_tag_entry_t; + +typedef struct uncached_tag_entry_{ + struct uncached_tag_entry_* next; + uint8_t level; // esp_log_level_t as uint8_t + char tag[0]; // beginning of a zero-terminated string +} uncached_tag_entry_t; + +static esp_log_level_t s_default_level = (esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL; +static uncached_tag_entry_t* s_head = NULL; +static uncached_tag_entry_t* s_tail = NULL; +static cached_tag_entry_t s_cache[TAG_CACHE_SIZE]; +static uint32_t s_cache_max_generation = 0; +static uint32_t s_cache_entry_count = 0; +static vprintf_like_t s_print_func = &vprintf; +static SemaphoreHandle_t s_mutex = NULL; + +static inline bool get_cached_log_level(const char* tag, esp_log_level_t* level); +static inline bool get_uncached_log_level(const char* tag, esp_log_level_t* level); +static inline void add_to_cache(const char* tag, esp_log_level_t level); +static void heap_bubble_down(int index); +static inline void heap_swap(int i, int j); +static inline bool should_output(esp_log_level_t level_for_message, esp_log_level_t level_for_tag); +static inline void clear_log_level_list(); + +void esp_log_set_vprintf(vprintf_like_t func) +{ + s_print_func = func; +} + +void esp_log_level_set(const char* tag, esp_log_level_t level) +{ + if (!s_mutex) { + s_mutex = xSemaphoreCreateMutex(); + } + xSemaphoreTake(&s_mutex, portMAX_DELAY); + + // for wildcard tag, remove all linked list items and clear the cache + if (strcmp(tag, "*") == 0) { + s_default_level = level; + clear_log_level_list(); + xSemaphoreGive(&s_mutex); + return; + } + + // allocate new linked list entry and append it to the endo of the list + size_t entry_size = offsetof(uncached_tag_entry_t, tag) + strlen(tag) + 1; + uncached_tag_entry_t* new_entry = (uncached_tag_entry_t*) malloc(entry_size); + if (!new_entry) { + xSemaphoreGive(&s_mutex); + return; + } + new_entry->next = NULL; + new_entry->level = (uint8_t) level; + strcpy(new_entry->tag, tag); + if (s_tail) { + s_tail->next = new_entry; + } + s_tail = new_entry; + if (!s_head) { + s_head = new_entry; + } + xSemaphoreGive(&s_mutex); +} + +void clear_log_level_list() +{ + for (uncached_tag_entry_t* it = s_head; it != NULL; ) { + uncached_tag_entry_t* next = it->next; + free(it); + it = next; + } + + s_cache_entry_count = 0; + s_cache_max_generation = 0; +} + +void IRAM_ATTR esp_log_write(esp_log_level_t level, + const char* tag, + const char* format, ...) +{ + if (!s_mutex) { + s_mutex = xSemaphoreCreateMutex(); + } + if (xSemaphoreTake(&s_mutex, MAX_MUTEX_WAIT_TICKS) == pdFALSE) { + return; + } + esp_log_level_t level_for_tag; + // Look for the tag in cache first, then in the linked list of all tags + if (!get_cached_log_level(tag, &level_for_tag)) { + if (!get_uncached_log_level(tag, &level_for_tag)) { + level_for_tag = s_default_level; + } + add_to_cache(tag, level_for_tag); + } + xSemaphoreGive(&s_mutex); + if (!should_output(level, level_for_tag)) { + return; + } + + va_list list; + va_start(list, format); + (*s_print_func)(format, list); + va_end(list); +} + +static inline bool get_cached_log_level(const char* tag, esp_log_level_t* level) +{ + // Look for `tag` in cache + int i; + for (i = 0; i < s_cache_entry_count; ++i) { + if (s_cache[i].tag == tag) { + break; + } + } + if (i == s_cache_entry_count) { // Not found in cache + return false; + } + // Return level from cache + *level = (esp_log_level_t) s_cache[i].level; + // Update item generation + s_cache[i].generation = s_cache_max_generation++; + // Restore heap ordering + heap_bubble_down(i); + return true; +} + +static inline void add_to_cache(const char* tag, esp_log_level_t level) +{ + uint32_t generation = s_cache_max_generation++; + // First consider the case when cache is not filled yet. + // In this case, just add new entry at the end. + // This happens to satisfy binary min-heap ordering. + if (s_cache_entry_count < TAG_CACHE_SIZE) { + s_cache[s_cache_entry_count] = (cached_tag_entry_t) { + .generation = generation, + .level = level, + .tag = tag + }; + ++s_cache_entry_count; + return; + } + + // Cache is full, so we replace the oldest entry (which is at index 0 + // because this is a min-heap) with the new one, and do bubble-down + // operation to restore min-heap ordering. + s_cache[0] = (cached_tag_entry_t) { + .tag = tag, + .level = level, + .generation = generation + }; + heap_bubble_down(0); +} + +static inline bool get_uncached_log_level(const char* tag, esp_log_level_t* level) +{ + // Walk the linked list of all tags and see if given tag is present in the list. + // This is slow because tags are compared as strings. + for (uncached_tag_entry_t* it = s_head; it != NULL; ++it) { + if (strcmp(tag, it->tag) == 0) { + *level = it->level; + return true; + } + } + return false; +} + +static inline bool should_output(esp_log_level_t level_for_message, esp_log_level_t level_for_tag) +{ + return level_for_message <= level_for_tag; +} + +static void heap_bubble_down(int index) +{ + while (index < TAG_CACHE_SIZE / 2) { + int left_index = index * 2 + 1; + int right_index = left_index + 1; + int next = (s_cache[left_index].generation < s_cache[right_index].generation) ? left_index : right_index; + heap_swap(index, next); + index = next; + } +} + +static inline void heap_swap(int i, int j) +{ + cached_tag_entry_t tmp = s_cache[i]; + s_cache[i] = s_cache[j]; + s_cache[j] = tmp; +} +#endif //BOOTLOADER_BUILD + +inline uint32_t esp_log_early_timestamp() +{ + return xthal_get_ccount() / (CPU_CLK_FREQ_ROM / 1000); +} + +#ifndef BOOTLOADER_BUILD + +uint32_t IRAM_ATTR esp_log_timestamp() +{ + if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) { + return esp_log_early_timestamp(); + } + static uint32_t base = 0; + if (base == 0) { + base = esp_log_early_timestamp(); + } + return base + xTaskGetTickCount() * configTICK_RATE_HZ; +} + +#else + +uint32_t esp_log_timestamp() +{ + return esp_log_early_timestamp(); +} + +#endif //BOOTLOADER_BUILD From 0290a34b55328ffe9a82a2d8cf5507a5ef2c0d4e Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 15 Sep 2016 01:59:42 +0800 Subject: [PATCH 32/57] components/esp32: clean up cpu_start Move CPU region protection setup into soc/cpu.h change tabs to spaces remove unused extern declarations use RTC_WDTCONFIG0 instead of numeric address (still need to fix BB reg) --- .../bootloader/src/main/bootloader_start.c | 32 +-- components/esp32/cpu_start.c | 251 +++++++----------- components/esp32/include/soc/cpu.h | 35 +++ 3 files changed, 130 insertions(+), 188 deletions(-) diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c index f56bc5e6b..116c7a98d 100644 --- a/components/bootloader/src/main/bootloader_start.c +++ b/components/bootloader/src/main/bootloader_start.c @@ -24,6 +24,7 @@ #include "rom/crc.h" #include "soc/soc.h" +#include "soc/cpu.h" #include "soc/dport_reg.h" #include "soc/io_mux_reg.h" #include "soc/efuse_reg.h" @@ -60,36 +61,7 @@ void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr, void IRAM_ATTR call_start_cpu0() { - //Make page 0 access raise an exception - //Also some other unused pages so we can catch weirdness - //ToDo: this but nicer. - asm volatile (\ - "movi a4,0x00000000\n" \ - "movi a5,0xf\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x80000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xa0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xc0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xe0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x20000000\n" \ - "movi a5,0x0\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x40000000\n" \ - "movi a5,0x2\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "isync\n" \ - :::"a4","a5"); + cpu_configure_region_protection(); //Clear bss memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index cfc628b12..20c6d379c 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -20,8 +20,10 @@ #include "rom/ets_sys.h" #include "rom/uart.h" +#include "soc/cpu.h" #include "soc/dport_reg.h" #include "soc/io_mux_reg.h" +#include "soc/rtc_cntl_reg.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -45,169 +47,104 @@ static void IRAM_ATTR user_start_cpu0(void); static void IRAM_ATTR call_user_start_cpu1(); static void IRAM_ATTR user_start_cpu1(void); extern void ets_setup_syscalls(void); +extern esp_err_t app_main(void *ctx); - -extern int __cpu1_entry_point; extern int _bss_start; extern int _bss_end; extern int _init_start; -extern int _init_end; -extern int _iram_romjumptable_start; -extern int _iram_romjumptable_end; -extern int _iram_text_start; -extern int _iram_text_end; - -static const char* TAG = "cpu_start"; - -/* -We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized, -flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C. -*/ - -static bool app_cpu_started = false; - -void IRAM_ATTR call_user_start_cpu0() { - //Kill wdt - REG_CLR_BIT(0x3ff4808c, BIT(10)); //RTCCNTL+8C RTC_WDTCONFIG0 RTC_ - REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48 - - //Move exception vectors to IRAM - asm volatile (\ - "wsr %0, vecbase\n" \ - ::"r"(&_init_start)); - - uartAttach(); - ets_install_uart_printf(); - - //Make page 0 access raise an exception - //Also some other unused pages so we can catch weirdness - //ToDo: this but nicer. - asm volatile (\ - "movi a4,0x00000000\n" \ - "movi a5,0xf\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x80000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xa0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xc0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xe0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x20000000\n" \ - "movi a5,0x0\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x40000000\n" \ - "movi a5,0x2\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "isync\n" \ - :::"a4","a5"); - - memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); - - // Initialize heap allocator - heap_alloc_caps_init(); - - ESP_EARLY_LOGI(TAG, "Pro cpu up."); - -#ifndef CONFIG_FREERTOS_UNICORE - ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1); - - SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN); - CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL); - SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING); - CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING); - ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1); - - while (!app_cpu_started) { - ets_delay_us(100); - } -#else - ESP_EARLY_LOGI(TAG, "Single core mode"); - CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN); -#endif - ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); - user_start_cpu0(); -} - - -extern int _init_start; - -void IRAM_ATTR call_user_start_cpu1() { - asm volatile (\ - "wsr %0, vecbase\n" \ - ::"r"(&_init_start)); - - //Make page 0 access raise an exception - //Also some other unused pages so we can catch weirdness - //ToDo: this but nicer. - asm volatile (\ - "movi a4,0x00000000\n" \ - "movi a5,0xf\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x80000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xa0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xc0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0xe0000000\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x20000000\n" \ - "movi a5,0x0\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "movi a4,0x40000000\n" \ - "movi a5,0x2\n" \ - "wdtlb a5,a4\n" \ - "witlb a5,a4\n" \ - "isync\n" \ - :::"a4","a5"); - - ESP_EARLY_LOGI(TAG, "App cpu up."); - app_cpu_started = 1; - user_start_cpu1(); -} - -extern volatile int port_xSchedulerRunning[2]; - -void IRAM_ATTR user_start_cpu1(void) { - // Wait for FreeRTOS initialization to finish on PRO CPU - while (port_xSchedulerRunning[0] == 0) { - ; - } - ESP_LOGI(TAG, "Starting scheduler on APP CPU."); - xPortStartScheduler(); -} - extern void (*__init_array_start)(void); extern void (*__init_array_end)(void); +extern volatile int port_xSchedulerRunning[2]; -static void do_global_ctors(void) { - void (**p)(void); - for(p = &__init_array_start; p != &__init_array_end; ++p) - (*p)(); +static const char* TAG = "cpu_start"; +static bool app_cpu_started = false; + +/* + * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized, + * and the app CPU is in reset. We do have a stack, so we can do the initialization in C. + */ + +void IRAM_ATTR call_user_start_cpu0() +{ + //Kill wdt + REG_CLR_BIT(RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); + REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48 + + cpu_configure_region_protection(); + + //Move exception vectors to IRAM + asm volatile (\ + "wsr %0, vecbase\n" \ + ::"r"(&_init_start)); + + uartAttach(); + ets_install_uart_printf(); + + memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); + + // Initialize heap allocator + heap_alloc_caps_init(); + + ESP_EARLY_LOGI(TAG, "Pro cpu up."); + +#ifndef CONFIG_FREERTOS_UNICORE + ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1); + + SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN); + CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL); + SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING); + CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING); + ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1); + + while (!app_cpu_started) { + ets_delay_us(100); + } +#else + ESP_EARLY_LOGI(TAG, "Single core mode"); + CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN); +#endif + ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); + user_start_cpu0(); } -extern esp_err_t app_main(void *ctx); -void user_start_cpu0(void) { +void IRAM_ATTR call_user_start_cpu1() +{ + asm volatile (\ + "wsr %0, vecbase\n" \ + ::"r"(&_init_start)); + + cpu_configure_region_protection(); + + ESP_EARLY_LOGI(TAG, "App cpu up."); + app_cpu_started = 1; + user_start_cpu1(); +} + +void IRAM_ATTR user_start_cpu1(void) +{ + // Wait for FreeRTOS initialization to finish on PRO CPU + while (port_xSchedulerRunning[0] == 0) { + ; + } + ESP_LOGI(TAG, "Starting scheduler on APP CPU."); + xPortStartScheduler(); +} + +static void do_global_ctors(void) +{ + void (**p)(void); + for (p = &__init_array_start; p != &__init_array_end; ++p) { + (*p)(); + } +} + +void user_start_cpu0(void) +{ ets_setup_syscalls(); - do_global_ctors(); - esp_ipc_init(); - spi_flash_init(); + do_global_ctors(); + esp_ipc_init(); + spi_flash_init(); #if CONFIG_WIFI_ENABLED esp_err_t ret = nvs_flash_init(5, 3); @@ -216,20 +153,18 @@ void user_start_cpu0(void) { } system_init(); - esp_event_init(NULL, NULL); - tcpip_adapter_init(); #endif #if CONFIG_WIFI_ENABLED && CONFIG_WIFI_AUTO_STARTUP #include "esp_wifi.h" - esp_wifi_startup(app_main, NULL); + esp_wifi_startup(app_main, NULL); #else - app_main(NULL); + app_main(NULL); #endif - ESP_LOGI(TAG, "Starting scheduler on PRO CPU."); - vTaskStartScheduler(); + ESP_LOGI(TAG, "Starting scheduler on PRO CPU."); + vTaskStartScheduler(); } diff --git a/components/esp32/include/soc/cpu.h b/components/esp32/include/soc/cpu.h index fdcf62190..b45f742ce 100644 --- a/components/esp32/include/soc/cpu.h +++ b/components/esp32/include/soc/cpu.h @@ -33,4 +33,39 @@ static inline bool cpu_in_interrupt_context(void) return (ps & PS_UM) == 0; } +/* Functions to set page attributes for Region Protection option in the CPU. + * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2). + */ + +static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr) +{ + asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr)); +} + + +static inline void cpu_write_itlb(unsigned vpn, unsigned attr) +{ + asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); +} + +/* Make page 0 access raise an exception. + * Also protect some other unused pages so we can catch weirdness. + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + */ + +static inline void cpu_configure_region_protection() +{ + const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000}; + for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) { + cpu_write_dtlb(pages_to_protect[i], 0xf); + cpu_write_itlb(pages_to_protect[i], 0xf); + } + cpu_write_dtlb(0x20000000, 0); + cpu_write_itlb(0x20000000, 0); +} + + #endif From 90e37d9eda0a56be49c5f0d1ffc795f3192a5167 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 15 Sep 2016 02:17:08 +0800 Subject: [PATCH 33/57] fix whitespace after merge --- components/esp32/cpu_start.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index 764a62c22..4bf812238 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -90,18 +90,18 @@ void IRAM_ATTR call_user_start_cpu0() #ifndef CONFIG_FREERTOS_UNICORE ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1); - SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); - CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); - SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); - CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); - ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1); + SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); + CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL); + SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); + CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING); + ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1); while (!app_cpu_started) { ets_delay_us(100); } #else ESP_EARLY_LOGI(TAG, "Single core mode"); - CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); + CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); #endif ESP_EARLY_LOGI(TAG, "Pro cpu start user code"); user_start_cpu0(); From b0683b0bb4c22bd98aa4805ed933773fa7d8dae8 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 15 Sep 2016 02:37:54 +0800 Subject: [PATCH 34/57] components/esp32,bootloader: fix build esp32: use new register name in cpu_start bootloader: EXTRA_CFLAGS don't work any more, set global CFLAGS in Makefile.projbuild --- components/bootloader/Makefile.projbuild | 3 +++ components/bootloader/src/Makefile | 4 ++-- components/esp32/cpu_start.c | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/components/bootloader/Makefile.projbuild b/components/bootloader/Makefile.projbuild index cf8b05673..d45cf144e 100644 --- a/components/bootloader/Makefile.projbuild +++ b/components/bootloader/Makefile.projbuild @@ -45,4 +45,7 @@ $(COMPONENT_PATH)/src/sdkconfig: $(PROJECT_PATH)/sdkconfig bootloader-flash: $(BOOTLOADER_BIN) $(MAKE) -C $(BOOTLOADER_COMPONENT_PATH)/src flash MAKEFLAGS= V=$(V) +else +CFLAGS += -D BOOTLOADER_BUILD=1 -I $(IDF_PATH)/components/esp32/include + endif diff --git a/components/bootloader/src/Makefile b/components/bootloader/src/Makefile index 065593ccb..f30e314a5 100644 --- a/components/bootloader/src/Makefile +++ b/components/bootloader/src/Makefile @@ -11,7 +11,7 @@ COMPONENTS := esptool_py bootloader log # IS_BOOTLOADER_BUILD tells the component Makefile.projbuild to be a no-op IS_BOOTLOADER_BUILD := 1 -#We cannot include the esp32 component directly but we need its includes. This is fixed by -EXTRA_CFLAGS := -D BOOTLOADER_BUILD=1 -I $(IDF_PATH)/components/esp32/include +#We cannot include the esp32 component directly but we need its includes. +#This is fixed by adding CFLAGS from Makefile.projbuild include $(IDF_PATH)/make/project.mk diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index 4bf812238..cb31fbd46 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -67,7 +67,7 @@ static bool app_cpu_started = false; void IRAM_ATTR call_user_start_cpu0() { //Kill wdt - REG_CLR_BIT(RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); + REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN); REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48 cpu_configure_region_protection(); From 6cffb5d8b4b3b84daa0744021356be066f7ca698 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 16 Sep 2016 09:43:52 +1000 Subject: [PATCH 35/57] rom/gpio.h: Use new GPIO_PIN0_REG register name Closes github #12 --- components/esp32/include/rom/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp32/include/rom/gpio.h b/components/esp32/include/rom/gpio.h index a6ca66f1d..b740a020b 100644 --- a/components/esp32/include/rom/gpio.h +++ b/components/esp32/include/rom/gpio.h @@ -38,7 +38,7 @@ extern "C" { #define GPIO_PIN_COUNT 40 #define GPIO_ID_PIN0 0 #define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) -#define GPIO_PIN_ADDR(i) (GPIO_PIN0 + i*4) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) #define GPIO_ID_IS_PIN_REGISTER(reg_id) \ ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) From 567cabb3f5c926828d70bb7f12aabcfd338ac9d0 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 16 Sep 2016 14:31:46 +1000 Subject: [PATCH 36/57] docs: Add note about esp-idf not supporting spaces in paths Ref Github #10 --- docs/linux-setup.rst | 1 + docs/macos-setup.rst | 1 + docs/windows-setup.rst | 2 ++ 3 files changed, 4 insertions(+) diff --git a/docs/linux-setup.rst b/docs/linux-setup.rst index ee9765156..13e1b3a9c 100644 --- a/docs/linux-setup.rst +++ b/docs/linux-setup.rst @@ -108,6 +108,7 @@ Note the ``--recursive`` option! If you have already cloned ESP-IDF without this cd ~/esp/esp-idf git submodule update --init +**IMPORTANT:** The esp-idf build system does not support spaces in paths to esp-idf or to projects. Step 3: Starting a project ========================== diff --git a/docs/macos-setup.rst b/docs/macos-setup.rst index d3869f426..8178a17ad 100644 --- a/docs/macos-setup.rst +++ b/docs/macos-setup.rst @@ -122,6 +122,7 @@ The easiest way to start a project is to download the template project from GitH This will download ``esp-idf-template`` project into ``~/esp/myapp`` directory. +**IMPORTANT:** The esp-idf build system does not support spaces in paths to esp-idf or to projects. Step 4: Building and flashing the application ============================================= diff --git a/docs/windows-setup.rst b/docs/windows-setup.rst index 89b134181..a368e3305 100644 --- a/docs/windows-setup.rst +++ b/docs/windows-setup.rst @@ -59,6 +59,8 @@ The easiest way to start a project is to download the Getting Started project fr The process is the same as for checking out the ESP-IDF from github. Change to the parent directory and run ``git clone https://github.com/espressif/esp-idf-template.git``. +**IMPORTANT:** The esp-idf build system does not support spaces in paths to esp-idf or to projects. + Step 4: Configuring the project =============================== From cdd1b95b6e509d97ba5b89c8f45eb9eb45fb4b73 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 16 Sep 2016 17:56:50 +1000 Subject: [PATCH 37/57] config system: Support Windows when CRLFs used for eol markers Includes a test in test_build_system.sh to prevent regressions w/ CRLFs in text files. Fixes Github #10 --- make/test_build_system.sh | 16 ++++++++++++++++ tools/kconfig/Makefile | 3 ++- tools/kconfig/zconf.l | 14 +++++++------- 3 files changed, 25 insertions(+), 8 deletions(-) diff --git a/make/test_build_system.sh b/make/test_build_system.sh index cb42356f0..5be1504e3 100755 --- a/make/test_build_system.sh +++ b/make/test_build_system.sh @@ -80,6 +80,22 @@ function run_tests() failure "Files weren't cleaned: ${ALL_BUILD_FILES}" fi + print_status "Can still clean build if all text files are CRLFs" + make clean + find . -exec unix2dos {} \; # CRLFify template dir + # make a copy of esp-idf and CRLFify it + CRLF_ESPIDF=${TESTDIR}/esp-idf-crlf + mkdir -p ${CRLF_ESPIDF} + cp -rv ${IDF_PATH}/* ${CRLF_ESPIDF} + # don't CRLFify executable files, as Linux will fail to execute them + find ${CRLF_ESPIDF} -type f ! -perm 755 -exec unix2dos {} \; + make IDF_PATH=${CRLF_ESPIDF} + # do the same checks we do for the clean build + assert_built ${APP_BINS} ${BOOTLOADER_BINS} partitions_singleapp.bin + [ -f ${BUILD}/partition*.bin ] || failure "A partition table should have been built in CRLF mode" + + # NOTE: If adding new tests, add them above this CRLF test... + print_status "All tests completed" if [ -n "${FAILURES}" ]; then echo "Some failures were detected:" diff --git a/tools/kconfig/Makefile b/tools/kconfig/Makefile index 2df04f3f2..65b236d34 100644 --- a/tools/kconfig/Makefile +++ b/tools/kconfig/Makefile @@ -301,7 +301,8 @@ zconf.lex.c: zconf.l flex -L -P zconf -o zconf.lex.c zconf.l zconf.hash.c: zconf.gperf - gperf -t --output-file zconf.hash.c -a -C -E -g -k '1,3,$$' -p -t zconf.gperf +# strip CRs on Windows systems where gperf will otherwise barf on them + sed -E "s/\r//" zconf.gperf | gperf -t --output-file zconf.hash.c -a -C -E -g -k '1,3,$$' -p -t zconf.tab.c: zconf.y bison -t -l -p zconf -o zconf.tab.c zconf.y diff --git a/tools/kconfig/zconf.l b/tools/kconfig/zconf.l index 8c787b509..f0b65608f 100644 --- a/tools/kconfig/zconf.l +++ b/tools/kconfig/zconf.l @@ -114,8 +114,8 @@ n [A-Za-z0-9_-] zconflval.string = text; return T_WORD; } - . warn_ignored_character(*yytext); - \n { + [^\r\n] warn_ignored_character(*yytext); + \r?\n { BEGIN(INITIAL); current_file->lineno++; return T_EOL; @@ -139,7 +139,7 @@ n [A-Za-z0-9_-] new_string(); BEGIN(STRING); } - \n BEGIN(INITIAL); current_file->lineno++; return T_EOL; + \r?\n BEGIN(INITIAL); current_file->lineno++; return T_EOL; ({n}|[/.])+ { const struct kconf_id *id = kconf_id_lookup(yytext, yyleng); if (id && id->flags & TF_PARAM) { @@ -184,7 +184,7 @@ n [A-Za-z0-9_-] } else append_string(yytext, 1); } - \n { + \r?\n { printf("%s:%d:warning: multi-line strings not supported\n", zconf_curname(), zconf_lineno()); current_file->lineno++; BEGIN(INITIAL); @@ -218,16 +218,16 @@ n [A-Za-z0-9_-] append_string(" ", ts); } } - [ \t]*\n/[^ \t\n] { + [ \t]*\r?\n/[^ \t\r\n] { current_file->lineno++; zconf_endhelp(); return T_HELPTEXT; } - [ \t]*\n { + [ \t]*\r?\n { current_file->lineno++; append_string("\n", 1); } - [^ \t\n].* { + [^ \t\r?\n].* { while (yyleng) { if ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\t')) break; From 90017397e517be09b77b07cbe0a0ca690f756979 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 16 Sep 2016 18:05:52 +1000 Subject: [PATCH 38/57] Docs: Add note about unusual submodule messages when cloning on Windows Related to github #11 --- docs/windows-setup.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/windows-setup.rst b/docs/windows-setup.rst index a368e3305..baea1ac40 100644 --- a/docs/windows-setup.rst +++ b/docs/windows-setup.rst @@ -50,6 +50,8 @@ Change to the directory you want to clone the SDK into by typing a command like If you'd rather use a Windows UI tool to manage your git repositories, this is also possible. A wide range are available. +*NOTE*: While cloning submodules, the ``git clone`` command may print some output starting ``': not a valid identifier...``. This is a `known issue`_ but the git clone still succeeds without any problems. + Step 3: Starting a project ========================== @@ -76,3 +78,4 @@ If you'd like to use the Eclipse IDE instead of running ``make``, check out the .. _Eclipse: eclipse-setup.rst .. _MSYS2: https://msys2.github.io/ .. _github: https://github.com/espressif/esp-idf-template +.. _known issue: https://github.com/espressif/esp-idf/issues/11 From 6cf5d44b31789beafcacd5f74e337bea09206e04 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Fri, 16 Sep 2016 18:22:16 +1000 Subject: [PATCH 39/57] build system docs: Add note about no spaces in component names --- docs/build_system.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/build_system.rst b/docs/build_system.rst index 43055a478..4df65b1b5 100644 --- a/docs/build_system.rst +++ b/docs/build_system.rst @@ -193,10 +193,13 @@ Because components usually live under the project directory (although they can also reside in an other folder), the path to this may be something like /home/myuser/projects/myprojects/components/httpd . +Components can have any name (unique to the project) but the name +cannot contain spaces (esp-idf does not support spaces in paths). + One of the things that most components will have is a component.mk makefile, containing instructions on how to build the component. Because the build environment tries to set reasonable defaults that will work most -of the time, component.mk can be very small. +of the time, component.mk can be very small. Simplest component.mk ===================== From 489b4f31a90cfcdd6056106dedf51c4057f7d6d1 Mon Sep 17 00:00:00 2001 From: Wangjialin Date: Sun, 18 Sep 2016 03:14:18 +0800 Subject: [PATCH 40/57] add peripheral module struct headers --- components/esp32/include/soc/gpio_sd_struct.h | 48 ++ components/esp32/include/soc/gpio_struct.h | 204 ++++++ components/esp32/include/soc/i2c_struct.h | 289 ++++++++ components/esp32/include/soc/i2s_struct.h | 461 ++++++++++++ components/esp32/include/soc/ledc_struct.h | 300 ++++++++ components/esp32/include/soc/pcnt_struct.h | 161 +++++ components/esp32/include/soc/rmt_struct.h | 228 ++++++ components/esp32/include/soc/spi_struct.h | 677 ++++++++++++++++++ .../esp32/include/soc/timer_group_struct.h | 195 +++++ components/esp32/include/soc/uart_struct.h | 365 ++++++++++ components/esp32/include/soc/uhci_struct.h | 337 +++++++++ components/esp32/ld/esp32.rom.ld | 23 +- 12 files changed, 3287 insertions(+), 1 deletion(-) create mode 100644 components/esp32/include/soc/gpio_sd_struct.h create mode 100644 components/esp32/include/soc/gpio_struct.h create mode 100644 components/esp32/include/soc/i2c_struct.h create mode 100644 components/esp32/include/soc/i2s_struct.h create mode 100644 components/esp32/include/soc/ledc_struct.h create mode 100644 components/esp32/include/soc/pcnt_struct.h create mode 100644 components/esp32/include/soc/rmt_struct.h create mode 100644 components/esp32/include/soc/spi_struct.h create mode 100644 components/esp32/include/soc/timer_group_struct.h create mode 100644 components/esp32/include/soc/uart_struct.h create mode 100644 components/esp32/include/soc/uhci_struct.h diff --git a/components/esp32/include/soc/gpio_sd_struct.h b/components/esp32/include/soc/gpio_sd_struct.h new file mode 100644 index 000000000..a1b17bfc5 --- /dev/null +++ b/components/esp32/include/soc/gpio_sd_struct.h @@ -0,0 +1,48 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_SD_STRUCT_H_ +#define _SOC_GPIO_SD_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t sd_in: 8; + volatile uint32_t prescale: 8; + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }sigmadelta[8]; + union { + struct { + volatile uint32_t reserved0: 31; + volatile uint32_t clk_en: 1; + }; + volatile uint32_t val; + }sigmadelta_cg; + union { + struct { + volatile uint32_t reserved0: 31; + volatile uint32_t spi_swap: 1; + }; + volatile uint32_t val; + }sigmadelta_misc; + union { + struct { + volatile uint32_t date: 28; + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }sigmadelta_version; +} gpio_sd_dev_t; +extern volatile gpio_sd_dev_t SIGMADELTA; +#endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/components/esp32/include/soc/gpio_struct.h b/components/esp32/include/soc/gpio_struct.h new file mode 100644 index 000000000..f42de7a29 --- /dev/null +++ b/components/esp32/include/soc/gpio_struct.h @@ -0,0 +1,204 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_GPIO_STRUCT_H_ +#define _SOC_GPIO_STRUCT_H_ +typedef struct { + volatile uint32_t bt_select; /*NA*/ + volatile uint32_t out; /*GPIO0~31 output value*/ + volatile uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ + volatile uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ + union { + struct { + volatile uint32_t out_data: 8; /*GPIO32~39 output value*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }out1; + union { + struct { + volatile uint32_t out_data: 8; /*GPIO32~39 output value write 1 to set*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }out1_w1ts; + union { + struct { + volatile uint32_t out_data: 8; /*GPIO32~39 output value write 1 to clear*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }out1_w1tc; + union { + struct { + volatile uint32_t sdio_sel: 8; /*SDIO PADS on/off control from outside*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }sdio_select; + volatile uint32_t enable; /*GPIO0~31 output enable*/ + volatile uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ + volatile uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ + union { + struct { + volatile uint32_t enable_data: 8; /*GPIO32~39 output enable*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }enable1; + union { + struct { + volatile uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to set*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }enable1_w1ts; + union { + struct { + volatile uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to clear*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }enable1_w1tc; + union { + struct { + volatile uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/ + volatile uint32_t reserved16:16; + }; + volatile uint32_t val; + }strap; + volatile uint32_t in; /*GPIO0~31 input value*/ + union { + struct { + volatile uint32_t in_data: 8; /*GPIO32~39 input value*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }in1; + volatile uint32_t status; /*GPIO0~31 interrupt status*/ + volatile uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ + volatile uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ + union { + struct { + volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }status1; + union { + struct { + volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to set*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }status1_w1ts; + union { + struct { + volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to clear*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }status1_w1tc; + volatile uint32_t reserved_5c; + volatile uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ + volatile uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ + volatile uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ + volatile uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ + volatile uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ + union { + struct { + volatile uint32_t appcpu_int: 8; /*GPIO32~39 APP CPU interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }acpu_int1; + union { + struct { + volatile uint32_t appcpu_nmi_int: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }acpu_nmi_int1; + union { + struct { + volatile uint32_t procpu_int: 8; /*GPIO32~39 PRO CPU interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pcpu_int1; + union { + struct { + volatile uint32_t procpu_nmi_int: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }pcpu_nmi_int1; + union { + struct { + volatile uint32_t sdio_int: 8; /*SDIO's extent GPIO32~39 interrupt*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }cpusdio_int1; + union { + struct { + volatile uint32_t reserved0: 2; + volatile uint32_t pin_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + volatile uint32_t reserved3: 4; + volatile uint32_t pin_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + volatile uint32_t pin_wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + volatile uint32_t pin_config: 2; /*NA*/ + volatile uint32_t pin_int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ + volatile uint32_t reserved18: 14; + }; + volatile uint32_t val; + }pin[40]; + union { + struct { + volatile uint32_t cali_rtc_max:10; + volatile uint32_t reserved10: 21; + volatile uint32_t cali_start: 1; + }; + volatile uint32_t val; + }cali_conf; + union { + struct { + volatile uint32_t cali_value_sync2:20; + volatile uint32_t reserved20: 10; + volatile uint32_t cali_rdy_real: 1; + volatile uint32_t cali_rdy_sync2: 1; + }; + volatile uint32_t val; + }cali_data; + union { + struct { + volatile uint32_t func_in_sel: 6; /*select one of the 256 inputs*/ + volatile uint32_t func_in_inv_sel: 1; /*revert the value of the input if you want to revert please set the value to 1*/ + volatile uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ + volatile uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ + }; + volatile uint32_t val; + }func_in_sel_cfg[256]; + union { + struct { + volatile uint32_t func_out_sel: 9; /*select one of the 256 output to 40 GPIO*/ + volatile uint32_t func_out_inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ + volatile uint32_t func_oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ + volatile uint32_t func_oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ + volatile uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ + }; + volatile uint32_t val; + }func_out_sel_cfg[40]; +} gpio_dev_t; +extern volatile gpio_dev_t GPIO; +#endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/components/esp32/include/soc/i2c_struct.h b/components/esp32/include/soc/i2c_struct.h new file mode 100644 index 000000000..78f895c02 --- /dev/null +++ b/components/esp32/include/soc/i2c_struct.h @@ -0,0 +1,289 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2C_STRUCT_H_ +#define _SOC_I2C_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/ + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }scl_low_period; + union { + struct { + volatile uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ + volatile uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ + volatile uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ + volatile uint32_t reserved3: 1; + volatile uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ + volatile uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ + volatile uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ + volatile uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ + volatile uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ + volatile uint32_t reserved9: 23; + }; + volatile uint32_t val; + }ctr; + union { + struct { + volatile uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + volatile uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + volatile uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + volatile uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + volatile uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + volatile uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + volatile uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + volatile uint32_t reserved7: 1; + volatile uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + volatile uint32_t reserved14: 4; + volatile uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + volatile uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + volatile uint32_t reserved27: 1; + volatile uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + volatile uint32_t reserved31: 1; + }; + volatile uint32_t val; + }status_reg; + union { + struct { + volatile uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/ + volatile uint32_t reserved20:12; + }; + volatile uint32_t val; + }timeout; + union { + struct { + volatile uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ + volatile uint32_t reserved15: 16; + volatile uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/ + }; + volatile uint32_t val; + }slave_addr; + union { + struct { + volatile uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + volatile uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + volatile uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + volatile uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }rx_fifo_st; + union { + struct { + volatile uint32_t rx_fifo_full_thrhd: 5; + volatile uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ + volatile uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ + volatile uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ + volatile uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ + volatile uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ + volatile uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ + volatile uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ + volatile uint32_t reserved26: 6; + }; + volatile uint32_t val; + }fifo_conf; + union { + struct { + volatile uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }fifo_data; + union { + struct { + volatile uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ + volatile uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ + volatile uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ + volatile uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ + volatile uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ + volatile uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ + volatile uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ + volatile uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ + volatile uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ + volatile uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ + volatile uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/ + volatile uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/ + volatile uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ + volatile uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ + volatile uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ + volatile uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/ + volatile uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/ + volatile uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/ + volatile uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ + volatile uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ + volatile uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ + volatile uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/ + volatile uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ + volatile uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ + volatile uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ + volatile uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ + volatile uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/ + volatile uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/ + volatile uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/ + volatile uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ + volatile uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }int_status; + union { + struct { + volatile uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }sda_hold; + union { + struct { + volatile uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }sda_sample; + union { + struct { + volatile uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/ + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }scl_high_period; + volatile uint32_t reserved_3c; + union { + struct { + volatile uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }scl_start_hold; + union { + struct { + volatile uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }scl_rstart_setup; + union { + struct { + volatile uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }scl_stop_hold; + union { + struct { + volatile uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }scl_stop_setup; + union { + struct { + volatile uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + volatile uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/ + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }scl_filter_cfg; + union { + struct { + volatile uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + volatile uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/ + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }sda_filter_cfg; + union { + struct { + volatile uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + volatile uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + volatile uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + volatile uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + volatile uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + volatile uint32_t reserved14: 17; + volatile uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + }; + volatile uint32_t val; + }command[16]; + volatile uint32_t reserved_98; + volatile uint32_t reserved_9c; + volatile uint32_t reserved_a0; + volatile uint32_t reserved_a4; + volatile uint32_t reserved_a8; + volatile uint32_t reserved_ac; + volatile uint32_t reserved_b0; + volatile uint32_t reserved_b4; + volatile uint32_t reserved_b8; + volatile uint32_t reserved_bc; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t date; /**/ + volatile uint32_t reserved_fc; + volatile uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/ +} i2c_dev_t; +extern volatile i2c_dev_t I2C0; +extern volatile i2c_dev_t I2C1; +#endif /* _SOC_I2C_STRUCT_H_ */ diff --git a/components/esp32/include/soc/i2s_struct.h b/components/esp32/include/soc/i2s_struct.h new file mode 100644 index 000000000..beea328a3 --- /dev/null +++ b/components/esp32/include/soc/i2s_struct.h @@ -0,0 +1,461 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_I2S_STRUCT_H_ +#define _SOC_I2S_STRUCT_H_ +typedef struct { + volatile uint32_t reserved_0; + volatile uint32_t reserved_4; + union { + struct { + volatile uint32_t tx_reset: 1; + volatile uint32_t rx_reset: 1; + volatile uint32_t tx_fifo_reset: 1; + volatile uint32_t rx_fifo_reset: 1; + volatile uint32_t tx_start: 1; + volatile uint32_t rx_start: 1; + volatile uint32_t tx_slave_mod: 1; + volatile uint32_t rx_slave_mod: 1; + volatile uint32_t tx_right_first: 1; + volatile uint32_t rx_right_first: 1; + volatile uint32_t tx_msb_shift: 1; + volatile uint32_t rx_msb_shift: 1; + volatile uint32_t tx_short_sync: 1; + volatile uint32_t rx_short_sync: 1; + volatile uint32_t tx_mono: 1; + volatile uint32_t rx_mono: 1; + volatile uint32_t tx_msb_right: 1; + volatile uint32_t rx_msb_right: 1; + volatile uint32_t sig_loopback: 1; + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }conf; + union { + struct { + volatile uint32_t rx_take_data_int_raw: 1; + volatile uint32_t tx_put_data_int_raw: 1; + volatile uint32_t rx_wfull_int_raw: 1; + volatile uint32_t rx_rempty_int_raw: 1; + volatile uint32_t tx_wfull_int_raw: 1; + volatile uint32_t tx_rempty_int_raw: 1; + volatile uint32_t rx_hung_int_raw: 1; + volatile uint32_t tx_hung_int_raw: 1; + volatile uint32_t in_done_int_raw: 1; + volatile uint32_t in_suc_eof_int_raw: 1; + volatile uint32_t in_err_eof_int_raw: 1; + volatile uint32_t out_done_int_raw: 1; + volatile uint32_t out_eof_int_raw: 1; + volatile uint32_t in_dscr_err_int_raw: 1; + volatile uint32_t out_dscr_err_int_raw: 1; + volatile uint32_t in_dscr_empty_int_raw: 1; + volatile uint32_t out_total_eof_int_raw: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rx_take_data_int_st: 1; + volatile uint32_t tx_put_data_int_st: 1; + volatile uint32_t rx_wfull_int_st: 1; + volatile uint32_t rx_rempty_int_st: 1; + volatile uint32_t tx_wfull_int_st: 1; + volatile uint32_t tx_rempty_int_st: 1; + volatile uint32_t rx_hung_int_st: 1; + volatile uint32_t tx_hung_int_st: 1; + volatile uint32_t in_done_int_st: 1; + volatile uint32_t in_suc_eof_int_st: 1; + volatile uint32_t in_err_eof_int_st: 1; + volatile uint32_t out_done_int_st: 1; + volatile uint32_t out_eof_int_st: 1; + volatile uint32_t in_dscr_err_int_st: 1; + volatile uint32_t out_dscr_err_int_st: 1; + volatile uint32_t in_dscr_empty_int_st: 1; + volatile uint32_t out_total_eof_int_st: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t rx_take_data_int_ena: 1; + volatile uint32_t tx_put_data_int_ena: 1; + volatile uint32_t rx_wfull_int_ena: 1; + volatile uint32_t rx_rempty_int_ena: 1; + volatile uint32_t tx_wfull_int_ena: 1; + volatile uint32_t tx_rempty_int_ena: 1; + volatile uint32_t rx_hung_int_ena: 1; + volatile uint32_t tx_hung_int_ena: 1; + volatile uint32_t in_done_int_ena: 1; + volatile uint32_t in_suc_eof_int_ena: 1; + volatile uint32_t in_err_eof_int_ena: 1; + volatile uint32_t out_done_int_ena: 1; + volatile uint32_t out_eof_int_ena: 1; + volatile uint32_t in_dscr_err_int_ena: 1; + volatile uint32_t out_dscr_err_int_ena: 1; + volatile uint32_t in_dscr_empty_int_ena: 1; + volatile uint32_t out_total_eof_int_ena: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t take_data_int_clr: 1; + volatile uint32_t put_data_int_clr: 1; + volatile uint32_t rx_wfull_int_clr: 1; + volatile uint32_t rx_rempty_int_clr: 1; + volatile uint32_t tx_wfull_int_clr: 1; + volatile uint32_t tx_rempty_int_clr: 1; + volatile uint32_t rx_hung_int_clr: 1; + volatile uint32_t tx_hung_int_clr: 1; + volatile uint32_t in_done_int_clr: 1; + volatile uint32_t in_suc_eof_int_clr: 1; + volatile uint32_t in_err_eof_int_clr: 1; + volatile uint32_t out_done_int_clr: 1; + volatile uint32_t out_eof_int_clr: 1; + volatile uint32_t in_dscr_err_int_clr: 1; + volatile uint32_t out_dscr_err_int_clr: 1; + volatile uint32_t in_dscr_empty_int_clr: 1; + volatile uint32_t out_total_eof_int_clr: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t tx_bck_in_delay: 2; + volatile uint32_t tx_ws_in_delay: 2; + volatile uint32_t rx_bck_in_delay: 2; + volatile uint32_t rx_ws_in_delay: 2; + volatile uint32_t rx_sd_in_delay: 2; + volatile uint32_t tx_bck_out_delay: 2; + volatile uint32_t tx_ws_out_delay: 2; + volatile uint32_t tx_sd_out_delay: 2; + volatile uint32_t rx_ws_out_delay: 2; + volatile uint32_t rx_bck_out_delay: 2; + volatile uint32_t tx_dsync_sw: 1; + volatile uint32_t rx_dsync_sw: 1; + volatile uint32_t data_enable_delay: 2; + volatile uint32_t tx_bck_in_inv: 1; + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }timing; + union { + struct { + volatile uint32_t rx_data_num: 6; + volatile uint32_t tx_data_num: 6; + volatile uint32_t dscr_en: 1; + volatile uint32_t tx_fifo_mod: 3; + volatile uint32_t rx_fifo_mod: 3; + volatile uint32_t tx_fifo_mod_force_en: 1; + volatile uint32_t rx_fifo_mod_force_en: 1; + volatile uint32_t reserved21: 11; + }; + volatile uint32_t val; + }fifo_conf; + volatile uint32_t rx_eof_num; + volatile uint32_t conf_single_data; + union { + struct { + volatile uint32_t tx_chan_mod: 3; + volatile uint32_t rx_chan_mod: 2; + volatile uint32_t reserved5: 27; + }; + volatile uint32_t val; + }conf_chan; + union { + struct { + volatile uint32_t outlink_addr: 20; + volatile uint32_t reserved20: 8; + volatile uint32_t outlink_stop: 1; + volatile uint32_t outlink_start: 1; + volatile uint32_t outlink_restart: 1; + volatile uint32_t outlink_park: 1; + }; + volatile uint32_t val; + }out_link; + union { + struct { + volatile uint32_t inlink_addr: 20; + volatile uint32_t reserved20: 8; + volatile uint32_t inlink_stop: 1; + volatile uint32_t inlink_start: 1; + volatile uint32_t inlink_restart: 1; + volatile uint32_t inlink_park: 1; + }; + volatile uint32_t val; + }in_link; + volatile uint32_t out_eof_des_addr; + volatile uint32_t in_eof_des_addr; + volatile uint32_t out_eof_bfr_des_addr; + union { + struct { + volatile uint32_t ahb_testmode: 3; + volatile uint32_t reserved3: 1; + volatile uint32_t ahb_testaddr: 2; + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }ahb_test; + volatile uint32_t in_link_dscr; + volatile uint32_t in_link_dscr_bf0; + volatile uint32_t in_link_dscr_bf1; + volatile uint32_t out_link_dscr; + volatile uint32_t out_link_dscr_bf0; + volatile uint32_t out_link_dscr_bf1; + union { + struct { + volatile uint32_t in_rst: 1; + volatile uint32_t out_rst: 1; + volatile uint32_t ahbm_fifo_rst: 1; + volatile uint32_t ahbm_rst: 1; + volatile uint32_t out_loop_test: 1; + volatile uint32_t in_loop_test: 1; + volatile uint32_t out_auto_wrback: 1; + volatile uint32_t out_no_restart_clr: 1; + volatile uint32_t out_eof_mode: 1; + volatile uint32_t outdscr_burst_en: 1; + volatile uint32_t indscr_burst_en: 1; + volatile uint32_t out_data_burst_en: 1; + volatile uint32_t check_owner: 1; + volatile uint32_t mem_trans_en: 1; + volatile uint32_t reserved14: 18; + }; + volatile uint32_t val; + }lc_conf; + union { + struct { + volatile uint32_t out_fifo_wdata: 9; + volatile uint32_t reserved9: 7; + volatile uint32_t out_fifo_push: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }out_fifo_push; + union { + struct { + volatile uint32_t in_fifo_rdata:12; + volatile uint32_t reserved12: 4; + volatile uint32_t in_fifo_pop: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }in_fifo_pop; + volatile uint32_t lc_state0; + volatile uint32_t lc_state1; + union { + struct { + volatile uint32_t lc_fifo_timeout: 8; + volatile uint32_t lc_fifo_timeout_shift: 3; + volatile uint32_t lc_fifo_timeout_ena: 1; + volatile uint32_t reserved12: 20; + }; + volatile uint32_t val; + }lc_hung_conf; + volatile uint32_t reserved_78; + volatile uint32_t reserved_7c; + union { + struct { + volatile uint32_t cvsd_y_max:16; + volatile uint32_t cvsd_y_min:16; + }; + volatile uint32_t val; + }cvsd_conf0; + union { + struct { + volatile uint32_t cvsd_sigma_max:16; + volatile uint32_t cvsd_sigma_min:16; + }; + volatile uint32_t val; + }cvsd_conf1; + union { + struct { + volatile uint32_t cvsd_k: 3; + volatile uint32_t cvsd_j: 3; + volatile uint32_t cvsd_beta: 10; + volatile uint32_t cvsd_h: 3; + volatile uint32_t reserved19:13; + }; + volatile uint32_t val; + }cvsd_conf2; + union { + struct { + volatile uint32_t good_pack_max: 6; + volatile uint32_t n_err_seg: 3; + volatile uint32_t shift_rate: 3; + volatile uint32_t max_slide_sample: 8; + volatile uint32_t pack_len_8k: 5; + volatile uint32_t n_min_err: 3; + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }plc_conf0; + union { + struct { + volatile uint32_t bad_cef_atten_para: 8; + volatile uint32_t bad_cef_atten_para_shift: 4; + volatile uint32_t bad_ola_win2_para_shift: 4; + volatile uint32_t bad_ola_win2_para: 8; + volatile uint32_t slide_win_len: 8; + }; + volatile uint32_t val; + }plc_conf1; + union { + struct { + volatile uint32_t cvsd_seg_mod: 2; + volatile uint32_t min_period: 5; + volatile uint32_t reserved7: 25; + }; + volatile uint32_t val; + }plc_conf2; + union { + struct { + volatile uint32_t esco_en: 1; + volatile uint32_t esco_chan_mod: 1; + volatile uint32_t esco_cvsd_dec_pack_err: 1; + volatile uint32_t esco_cvsd_pack_len_8k: 5; + volatile uint32_t esco_cvsd_inf_en: 1; + volatile uint32_t cvsd_dec_start: 1; + volatile uint32_t cvsd_dec_reset: 1; + volatile uint32_t plc_en: 1; + volatile uint32_t plc2dma_en: 1; + volatile uint32_t reserved13: 19; + }; + volatile uint32_t val; + }esco_conf0; + union { + struct { + volatile uint32_t sco_with_en: 1; + volatile uint32_t sco_no_en: 1; + volatile uint32_t cvsd_enc_start: 1; + volatile uint32_t cvsd_enc_reset: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }sco_conf0; + union { + struct { + volatile uint32_t tx_pcm_conf: 3; + volatile uint32_t tx_pcm_bypass: 1; + volatile uint32_t rx_pcm_conf: 3; + volatile uint32_t rx_pcm_bypass: 1; + volatile uint32_t tx_stop_en: 1; + volatile uint32_t tx_zeros_rm_en: 1; + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t fifo_force_pd: 1; + volatile uint32_t fifo_force_pu: 1; + volatile uint32_t plc_mem_force_pd: 1; + volatile uint32_t plc_mem_force_pu: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }pd_conf; + union { + struct { + volatile uint32_t camera_en: 1; + volatile uint32_t lcd_tx_wrx2_en: 1; + volatile uint32_t lcd_tx_sdx2_en: 1; + volatile uint32_t data_enable_test_en: 1; + volatile uint32_t data_enable: 1; + volatile uint32_t lcd_en: 1; + volatile uint32_t ext_adc_start_en: 1; + volatile uint32_t inter_valid_en: 1; + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }conf2; + union { + struct { + volatile uint32_t clkm_div_num: 8; + volatile uint32_t clkm_div_b: 6; + volatile uint32_t clkm_div_a: 6; + volatile uint32_t clk_en: 1; + volatile uint32_t clka_ena: 1; + volatile uint32_t reserved22: 10; + }; + volatile uint32_t val; + }clkm_conf; + union { + struct { + volatile uint32_t tx_bck_div_num: 6; + volatile uint32_t rx_bck_div_num: 6; + volatile uint32_t tx_bits_mod: 6; + volatile uint32_t rx_bits_mod: 6; + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }sample_rate_conf; + union { + struct { + volatile uint32_t tx_pdm_en: 1; + volatile uint32_t rx_pdm_en: 1; + volatile uint32_t pcm2pdm_conv_en: 1; + volatile uint32_t pdm2pcm_conv_en: 1; + volatile uint32_t tx_pdm_sinc_osr2: 4; + volatile uint32_t tx_pdm_prescale: 8; + volatile uint32_t tx_pdm_hp_in_shift: 2; + volatile uint32_t tx_pdm_lp_in_shift: 2; + volatile uint32_t tx_pdm_sinc_in_shift: 2; + volatile uint32_t tx_pdm_sigmadelta_in_shift: 2; + volatile uint32_t rx_pdm_sinc_dsr_16_en: 1; + volatile uint32_t tx_pdm_hp_bypass: 1; + volatile uint32_t reserved26: 6; + }; + volatile uint32_t val; + }pdm_conf; + union { + struct { + volatile uint32_t tx_pdm_fs: 10; + volatile uint32_t tx_pdm_fp: 10; + volatile uint32_t reserved20:12; + }; + volatile uint32_t val; + }pdm_freq_conf; + union { + struct { + volatile uint32_t tx_idle: 1; + volatile uint32_t tx_fifo_reset_back: 1; + volatile uint32_t rx_fifo_reset_back: 1; + volatile uint32_t reserved3: 29; + }; + volatile uint32_t val; + }state; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /**/ +} i2s_dev_t; +extern volatile i2s_dev_t I2S0; +extern volatile i2s_dev_t I2S1; + +#endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/components/esp32/include/soc/ledc_struct.h b/components/esp32/include/soc/ledc_struct.h new file mode 100644 index 000000000..302a9e4bc --- /dev/null +++ b/components/esp32/include/soc/ledc_struct.h @@ -0,0 +1,300 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_LEDC_STRUCT_H_ +#define _SOC_LEDC_STRUCT_H_ +typedef struct { + struct{ + union { + struct { + volatile uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ + volatile uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ + volatile uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ + volatile uint32_t reserved4: 27; + volatile uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }hpoint; + union { + struct { + volatile uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty; + union { + struct { + volatile uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ + volatile uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ + volatile uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ + volatile uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ + volatile uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty_rd; + }high_speed_channel[8]; + struct{ + union { + struct { + volatile uint32_t timer_sel: 2; /*There are four low speed timers the two bits are used to select one of them for low speed channel. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ + volatile uint32_t sig_out_en: 1; /*This is the output enable control bit for low speed channel.*/ + volatile uint32_t idle_lv: 1; /*This bit is used to control the output value when low speed channel is off.*/ + volatile uint32_t para_up: 1; /*This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel.*/ + volatile uint32_t reserved5: 27; + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t hpoint: 20; /*The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel has reached reg_hpoint_lsch0[19:0]*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }hpoint; + union { + struct { + volatile uint32_t duty: 25; /*The register is used to control output duty. When lstimerx(x=[0 3]) choosed by low speed channel has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty; + union { + struct { + volatile uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for low speed channel.*/ + volatile uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel.*/ + volatile uint32_t duty_num: 10; /*This register is used to control the num of increased or decreased times for low speed channel6.*/ + volatile uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6.*/ + volatile uint32_t duty_start: 1; /*When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t duty_read: 25; /*This register represents the current duty of the output signal for low speed channel.*/ + volatile uint32_t reserved25: 7; + }; + volatile uint32_t val; + }duty_r; + }low_speed_channel[8]; + struct{ + union { + struct { + volatile uint32_t timer_lim: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ + volatile uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ + volatile uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ + volatile uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ + volatile uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ + volatile uint32_t reserved26: 6; + }; + volatile uint32_t val; + }conf; + union { + struct { + volatile uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }value; + }high_speed_timer[4]; + struct{ + union { + struct { + volatile uint32_t timer_lim: 5; /*This register controls the range of the counter in low speed timer. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ + volatile uint32_t div_num: 18; /*This register is used to configure parameter for divider in low speed timer the least significant eight bits represent the decimal part.*/ + volatile uint32_t pause: 1; /*This bit is used to pause the counter in low speed timer.*/ + volatile uint32_t rst: 1; /*This bit is used to reset low speed timer the counter will be 0 after reset.*/ + volatile uint32_t tick_sel: 1; /*This bit is used to choose slow_clk or ref_tick for low speed timer. 1'b1:slow_clk 0:ref_tick*/ + volatile uint32_t param_update: 1; /*Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ + volatile uint32_t reserved27: 5; + }; + volatile uint32_t val; + }conf; + union { + struct { + volatile uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in low speed timer.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }value; + }low_speed_timer[4]; + union { + struct { + volatile uint32_t hstimer0_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ + volatile uint32_t hstimer1_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ + volatile uint32_t hstimer2_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ + volatile uint32_t hstimer3_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ + volatile uint32_t lstimer0_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ + volatile uint32_t lstimer1_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ + volatile uint32_t lstimer2_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ + volatile uint32_t lstimer3_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ + volatile uint32_t duty_chng_end_hsch0_int_raw: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ + volatile uint32_t duty_chng_end_hsch1_int_raw: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ + volatile uint32_t duty_chng_end_hsch2_int_raw: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ + volatile uint32_t duty_chng_end_hsch3_int_raw: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ + volatile uint32_t duty_chng_end_hsch4_int_raw: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ + volatile uint32_t duty_chng_end_hsch5_int_raw: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ + volatile uint32_t duty_chng_end_hsch6_int_raw: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ + volatile uint32_t duty_chng_end_hsch7_int_raw: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ + volatile uint32_t duty_chng_end_lsch0_int_raw: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ + volatile uint32_t duty_chng_end_lsch1_int_raw: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ + volatile uint32_t duty_chng_end_lsch2_int_raw: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ + volatile uint32_t duty_chng_end_lsch3_int_raw: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ + volatile uint32_t duty_chng_end_lsch4_int_raw: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ + volatile uint32_t duty_chng_end_lsch5_int_raw: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ + volatile uint32_t duty_chng_end_lsch6_int_raw: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ + volatile uint32_t duty_chng_end_lsch7_int_raw: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t hstimer0_ovf_int_st: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ + volatile uint32_t hstimer1_ovf_int_st: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ + volatile uint32_t hstimer2_ovf_int_st: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ + volatile uint32_t hstimer3_ovf_int_st: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ + volatile uint32_t lstimer0_ovf_int_st: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ + volatile uint32_t lstimer1_ovf_int_st: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ + volatile uint32_t lstimer2_ovf_int_st: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ + volatile uint32_t lstimer3_ovf_int_st: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ + volatile uint32_t duty_chng_end_hsch0_int_st: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch1_int_st: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch2_int_st: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch3_int_st: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch4_int_st: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch5_int_st: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch6_int_st: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ + volatile uint32_t duty_chng_end_hsch7_int_st: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch0_int_st: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch1_int_st: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch2_int_st: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch3_int_st: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch4_int_st: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch5_int_st: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch6_int_st: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ + volatile uint32_t duty_chng_end_lsch7_int_st: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t hstimer0_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ + volatile uint32_t hstimer1_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ + volatile uint32_t hstimer2_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ + volatile uint32_t hstimer3_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ + volatile uint32_t lstimer0_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ + volatile uint32_t lstimer1_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ + volatile uint32_t lstimer2_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ + volatile uint32_t lstimer3_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ + volatile uint32_t duty_chng_end_hsch0_int_ena: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch1_int_ena: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch2_int_ena: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch3_int_ena: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch4_int_ena: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch5_int_ena: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch6_int_ena: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch7_int_ena: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch0_int_ena: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch1_int_ena: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch2_int_ena: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch3_int_ena: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch4_int_ena: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch5_int_ena: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch6_int_ena: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch7_int_ena: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t hstimer0_ovf_int_clr: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ + volatile uint32_t hstimer1_ovf_int_clr: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ + volatile uint32_t hstimer2_ovf_int_clr: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ + volatile uint32_t hstimer3_ovf_int_clr: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ + volatile uint32_t lstimer0_ovf_int_clr: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ + volatile uint32_t lstimer1_ovf_int_clr: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ + volatile uint32_t lstimer2_ovf_int_clr: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ + volatile uint32_t lstimer3_ovf_int_clr: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ + volatile uint32_t duty_chng_end_hsch0_int_clr: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch1_int_clr: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch2_int_clr: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch3_int_clr: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch4_int_clr: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch5_int_clr: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch6_int_clr: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_hsch7_int_clr: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch0_int_clr: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch1_int_clr: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch2_int_clr: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch3_int_clr: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch4_int_clr: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch5_int_clr: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch6_int_clr: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ + volatile uint32_t duty_chng_end_lsch7_int_clr: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ + volatile uint32_t reserved1: 31; + }; + volatile uint32_t val; + }conf; + volatile uint32_t reserved_194; + volatile uint32_t reserved_198; + volatile uint32_t reserved_19c; + volatile uint32_t reserved_1a0; + volatile uint32_t reserved_1a4; + volatile uint32_t reserved_1a8; + volatile uint32_t reserved_1ac; + volatile uint32_t reserved_1b0; + volatile uint32_t reserved_1b4; + volatile uint32_t reserved_1b8; + volatile uint32_t reserved_1bc; + volatile uint32_t reserved_1c0; + volatile uint32_t reserved_1c4; + volatile uint32_t reserved_1c8; + volatile uint32_t reserved_1cc; + volatile uint32_t reserved_1d0; + volatile uint32_t reserved_1d4; + volatile uint32_t reserved_1d8; + volatile uint32_t reserved_1dc; + volatile uint32_t reserved_1e0; + volatile uint32_t reserved_1e4; + volatile uint32_t reserved_1e8; + volatile uint32_t reserved_1ec; + volatile uint32_t reserved_1f0; + volatile uint32_t reserved_1f4; + volatile uint32_t reserved_1f8; + volatile uint32_t date; /*This register represents the version .*/ +} ledc_dev_t; +extern volatile ledc_dev_t LEDC; +#endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/components/esp32/include/soc/pcnt_struct.h b/components/esp32/include/soc/pcnt_struct.h new file mode 100644 index 000000000..bf9679399 --- /dev/null +++ b/components/esp32/include/soc/pcnt_struct.h @@ -0,0 +1,161 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_PCNT_STRUCT_H_ +#define _SOC_PCNT_STRUCT_H_ +typedef struct { + struct{ + union { + struct { + volatile uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ + volatile uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ + volatile uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ + volatile uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ + volatile uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ + volatile uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ + volatile uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ + volatile uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + volatile uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + volatile uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + volatile uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + volatile uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + volatile uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + volatile uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + volatile uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ + volatile uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ + volatile uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ + }; + volatile uint32_t val; + }conf2; + }conf_unit[8]; + union { + struct { + volatile uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }cnt_unit[8]; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_raw: 1; /*This is the interrupt raw bit for channel0 event.*/ + volatile uint32_t cnt_thr_event_u1_int_raw: 1; /*This is the interrupt raw bit for channel1 event.*/ + volatile uint32_t cnt_thr_event_u2_int_raw: 1; /*This is the interrupt raw bit for channel2 event.*/ + volatile uint32_t cnt_thr_event_u3_int_raw: 1; /*This is the interrupt raw bit for channel3 event.*/ + volatile uint32_t cnt_thr_event_u4_int_raw: 1; /*This is the interrupt raw bit for channel4 event.*/ + volatile uint32_t cnt_thr_event_u5_int_raw: 1; /*This is the interrupt raw bit for channel5 event.*/ + volatile uint32_t cnt_thr_event_u6_int_raw: 1; /*This is the interrupt raw bit for channel6 event.*/ + volatile uint32_t cnt_thr_event_u7_int_raw: 1; /*This is the interrupt raw bit for channel7 event.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_st: 1; /*This is the interrupt status bit for channel0 event.*/ + volatile uint32_t cnt_thr_event_u1_int_st: 1; /*This is the interrupt status bit for channel1 event.*/ + volatile uint32_t cnt_thr_event_u2_int_st: 1; /*This is the interrupt status bit for channel2 event.*/ + volatile uint32_t cnt_thr_event_u3_int_st: 1; /*This is the interrupt status bit for channel3 event.*/ + volatile uint32_t cnt_thr_event_u4_int_st: 1; /*This is the interrupt status bit for channel4 event.*/ + volatile uint32_t cnt_thr_event_u5_int_st: 1; /*This is the interrupt status bit for channel5 event.*/ + volatile uint32_t cnt_thr_event_u6_int_st: 1; /*This is the interrupt status bit for channel6 event.*/ + volatile uint32_t cnt_thr_event_u7_int_st: 1; /*This is the interrupt status bit for channel7 event.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_ena: 1; /*This is the interrupt enable bit for channel0 event.*/ + volatile uint32_t cnt_thr_event_u1_int_ena: 1; /*This is the interrupt enable bit for channel1 event.*/ + volatile uint32_t cnt_thr_event_u2_int_ena: 1; /*This is the interrupt enable bit for channel2 event.*/ + volatile uint32_t cnt_thr_event_u3_int_ena: 1; /*This is the interrupt enable bit for channel3 event.*/ + volatile uint32_t cnt_thr_event_u4_int_ena: 1; /*This is the interrupt enable bit for channel4 event.*/ + volatile uint32_t cnt_thr_event_u5_int_ena: 1; /*This is the interrupt enable bit for channel5 event.*/ + volatile uint32_t cnt_thr_event_u6_int_ena: 1; /*This is the interrupt enable bit for channel6 event.*/ + volatile uint32_t cnt_thr_event_u7_int_ena: 1; /*This is the interrupt enable bit for channel7 event.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t cnt_thr_event_u0_int_clr: 1; /*Set this bit to clear channel0 event interrupt.*/ + volatile uint32_t cnt_thr_event_u1_int_clr: 1; /*Set this bit to clear channel1 event interrupt.*/ + volatile uint32_t cnt_thr_event_u2_int_clr: 1; /*Set this bit to clear channel2 event interrupt.*/ + volatile uint32_t cnt_thr_event_u3_int_clr: 1; /*Set this bit to clear channel3 event interrupt.*/ + volatile uint32_t cnt_thr_event_u4_int_clr: 1; /*Set this bit to clear channel4 event interrupt.*/ + volatile uint32_t cnt_thr_event_u5_int_clr: 1; /*Set this bit to clear channel5 event interrupt.*/ + volatile uint32_t cnt_thr_event_u6_int_clr: 1; /*Set this bit to clear channel6 event interrupt.*/ + volatile uint32_t cnt_thr_event_u7_int_clr: 1; /*Set this bit to clear channel7 event interrupt.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }int_clr; + volatile uint32_t status_unit[8]; + union { + struct { + volatile uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ + volatile uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ + volatile uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ + volatile uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ + volatile uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ + volatile uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ + volatile uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ + volatile uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ + volatile uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ + volatile uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ + volatile uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ + volatile uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ + volatile uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ + volatile uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ + volatile uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ + volatile uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ + volatile uint32_t clk_en: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }ctrl; + volatile uint32_t reserved_b4; + volatile uint32_t reserved_b8; + volatile uint32_t reserved_bc; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /**/ +} pcnt_dev_t; +extern volatile pcnt_dev_t PCNT; +#endif /* _SOC_PCNT_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rmt_struct.h b/components/esp32/include/soc/rmt_struct.h new file mode 100644 index 000000000..7310e18d5 --- /dev/null +++ b/components/esp32/include/soc/rmt_struct.h @@ -0,0 +1,228 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_RMT_STRUCT_H_ +#define _SOC_RMT_STRUCT_H_ +typedef struct { + volatile uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/ + struct{ + union { + struct { + volatile uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ + volatile uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/ + volatile uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/ + volatile uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/ + volatile uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ + volatile uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/ + volatile uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/ + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/ + volatile uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/ + volatile uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/ + volatile uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/ + volatile uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/ + volatile uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/ + volatile uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/ + volatile uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/ + volatile uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/ + volatile uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ + volatile uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ + volatile uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/ + volatile uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }conf1; + }conf_ch[8]; + volatile uint32_t status_ch[8]; /*The status for channel0-7*/ + volatile uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/ + union { + struct { + volatile uint32_t ch0_tx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ + volatile uint32_t ch0_rx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ + volatile uint32_t ch0_err_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ + volatile uint32_t ch1_tx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ + volatile uint32_t ch1_rx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ + volatile uint32_t ch1_err_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ + volatile uint32_t ch2_tx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ + volatile uint32_t ch2_rx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ + volatile uint32_t ch2_err_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ + volatile uint32_t ch3_tx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ + volatile uint32_t ch3_rx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ + volatile uint32_t ch3_err_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ + volatile uint32_t ch4_tx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ + volatile uint32_t ch4_rx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ + volatile uint32_t ch4_err_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ + volatile uint32_t ch5_tx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ + volatile uint32_t ch5_rx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ + volatile uint32_t ch5_err_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ + volatile uint32_t ch6_tx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ + volatile uint32_t ch6_rx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ + volatile uint32_t ch6_err_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ + volatile uint32_t ch7_tx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ + volatile uint32_t ch7_rx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ + volatile uint32_t ch7_err_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ + volatile uint32_t ch0_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch1_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch2_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch3_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch4_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch5_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch6_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ + volatile uint32_t ch7_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t ch0_tx_end_int_st: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ + volatile uint32_t ch0_rx_end_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ + volatile uint32_t ch0_err_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ + volatile uint32_t ch1_tx_end_int_st: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch1_rx_end_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch1_err_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ + volatile uint32_t ch2_tx_end_int_st: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch2_rx_end_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch2_err_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ + volatile uint32_t ch3_tx_end_int_st: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch3_rx_end_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch3_err_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ + volatile uint32_t ch4_tx_end_int_st: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch4_rx_end_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch4_err_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ + volatile uint32_t ch5_tx_end_int_st: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch5_rx_end_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch5_err_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ + volatile uint32_t ch6_tx_end_int_st: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch6_rx_end_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch6_err_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ + volatile uint32_t ch7_tx_end_int_st: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ + volatile uint32_t ch7_rx_end_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ + volatile uint32_t ch7_err_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ + volatile uint32_t ch0_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch1_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch2_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch3_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch4_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch5_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch6_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ + volatile uint32_t ch7_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t ch0_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ + volatile uint32_t ch0_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ + volatile uint32_t ch0_err_int_ena: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ + volatile uint32_t ch1_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ + volatile uint32_t ch1_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ + volatile uint32_t ch1_err_int_ena: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ + volatile uint32_t ch2_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ + volatile uint32_t ch2_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ + volatile uint32_t ch2_err_int_ena: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ + volatile uint32_t ch3_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ + volatile uint32_t ch3_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ + volatile uint32_t ch3_err_int_ena: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ + volatile uint32_t ch4_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ + volatile uint32_t ch4_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ + volatile uint32_t ch4_err_int_ena: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ + volatile uint32_t ch5_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ + volatile uint32_t ch5_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ + volatile uint32_t ch5_err_int_ena: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ + volatile uint32_t ch6_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ + volatile uint32_t ch6_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ + volatile uint32_t ch6_err_int_ena: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ + volatile uint32_t ch7_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ + volatile uint32_t ch7_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ + volatile uint32_t ch7_err_int_ena: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ + volatile uint32_t ch0_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ + volatile uint32_t ch1_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ + volatile uint32_t ch2_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ + volatile uint32_t ch3_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ + volatile uint32_t ch4_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ + volatile uint32_t ch5_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ + volatile uint32_t ch6_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ + volatile uint32_t ch7_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t ch0_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ + volatile uint32_t ch0_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ + volatile uint32_t ch0_err_int_clr: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ + volatile uint32_t ch1_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ + volatile uint32_t ch1_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ + volatile uint32_t ch1_err_int_clr: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ + volatile uint32_t ch2_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ + volatile uint32_t ch2_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ + volatile uint32_t ch2_err_int_clr: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ + volatile uint32_t ch3_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ + volatile uint32_t ch3_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ + volatile uint32_t ch3_err_int_clr: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ + volatile uint32_t ch4_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ + volatile uint32_t ch4_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ + volatile uint32_t ch4_err_int_clr: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ + volatile uint32_t ch5_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ + volatile uint32_t ch5_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ + volatile uint32_t ch5_err_int_clr: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ + volatile uint32_t ch6_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ + volatile uint32_t ch6_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ + volatile uint32_t ch6_err_int_clr: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ + volatile uint32_t ch7_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ + volatile uint32_t ch7_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ + volatile uint32_t ch7_err_int_clr: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ + volatile uint32_t ch0_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch1_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch2_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch3_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch4_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch5_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch6_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ + volatile uint32_t ch7_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t carrier_low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ + volatile uint32_t carrier_high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + }; + volatile uint32_t val; + }carrier_duty_ch[8]; + union { + struct { + volatile uint32_t tx_lim: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ + volatile uint32_t reserved9: 23; + }; + volatile uint32_t val; + }tx_lim_ch[8]; + union { + struct { + volatile uint32_t apb_fifo_mask: 1; /*Set this bit to disable apb fifo access*/ + volatile uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ + volatile uint32_t reserved2: 30; + }; + volatile uint32_t val; + }apb_conf; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /*This is the version register.*/ +} rmt_dev_t; +extern volatile rmt_dev_t RMT; +#endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/esp32/include/soc/spi_struct.h b/components/esp32/include/soc/spi_struct.h new file mode 100644 index 000000000..e76590537 --- /dev/null +++ b/components/esp32/include/soc/spi_struct.h @@ -0,0 +1,677 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_SPI_STRUCT_H_ +#define _SOC_SPI_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t reserved0: 16; /*reserved*/ + volatile uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ + volatile uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + volatile uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + volatile uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + volatile uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + volatile uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + }; + volatile uint32_t val; + }cmd; + union { + struct { + volatile uint32_t reserved : 8; + volatile uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/ + }; + volatile uint32_t val; + }addr; + union { + struct { + volatile uint32_t reserved0: 10; /*reserved*/ + volatile uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + volatile uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + volatile uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ + volatile uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ + volatile uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + volatile uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ + volatile uint32_t reserved16: 4; /*reserved*/ + volatile uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + volatile uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + volatile uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + volatile uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + volatile uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + volatile uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ + volatile uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ + volatile uint32_t reserved27: 5; /*reserved*/ + }; + volatile uint32_t val; + }ctrl; + union { + struct { + volatile uint32_t reserved0: 16; /*reserved*/ + volatile uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ + volatile uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ + }; + volatile uint32_t val; + }ctrl1; + union { + struct { + volatile uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ + volatile uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ + volatile uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ + }; + volatile uint32_t val; + }rd_status; + union { + struct { + volatile uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ + volatile uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ + volatile uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ + volatile uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ + volatile uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + volatile uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ + volatile uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + volatile uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ + volatile uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + volatile uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ + }; + volatile uint32_t val; + }ctrl2; + union { + struct { + volatile uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ + volatile uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + volatile uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ + volatile uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ + volatile uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ + }; + volatile uint32_t val; + }clock; + union { + struct { + volatile uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ + volatile uint32_t reserved1: 3; /*reserved*/ + volatile uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ + volatile uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ + volatile uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ + volatile uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ + volatile uint32_t reserved8: 2; /*reserved*/ + volatile uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ + volatile uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ + volatile uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ + volatile uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ + volatile uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + volatile uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + volatile uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ + volatile uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ + volatile uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ + volatile uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + volatile uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + volatile uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + volatile uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ + volatile uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ + volatile uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + volatile uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ + volatile uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ + }; + volatile uint32_t val; + }user; + union { + struct { + volatile uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + volatile uint32_t reserved8: 18; /*reserved*/ + volatile uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + volatile uint32_t val; + }user1; + union { + struct { + volatile uint32_t usr_command_value: 16; /*The value of command.*/ + volatile uint32_t reserved16: 12; /*reserved*/ + volatile uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + volatile uint32_t val; + }user2; + union { + struct { + volatile uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }mosi_dlen; + union { + struct { + volatile uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }miso_dlen; + volatile uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ + union { + struct { + volatile uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ + volatile uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ + volatile uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ + volatile uint32_t reserved3: 2; /*reserved*/ + volatile uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ + volatile uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ + volatile uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ + volatile uint32_t reserved16: 13; /*reserved*/ + volatile uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + volatile uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + volatile uint32_t reserved31: 1; /*reserved*/ + }; + volatile uint32_t val; + }pin; + union { + struct { + volatile uint32_t slv_rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ + volatile uint32_t slv_wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ + volatile uint32_t slv_rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ + volatile uint32_t slv_wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ + volatile uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + volatile uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ + volatile uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ + volatile uint32_t reserved12: 5; /*reserved*/ + volatile uint32_t slv_last_command: 3; /*In the slave mode it is the value of command.*/ + volatile uint32_t slv_last_state: 3; /*In the slave mode it is the state of spi state machine.*/ + volatile uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ + volatile uint32_t slv_cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ + volatile uint32_t slv_wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ + volatile uint32_t slv_wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ + volatile uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ + volatile uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ + }; + volatile uint32_t val; + }slave; + union { + struct { + volatile uint32_t slv_rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ + volatile uint32_t slv_wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ + volatile uint32_t slv_rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ + volatile uint32_t slv_wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ + volatile uint32_t slv_wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ + volatile uint32_t slv_rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved16: 9; /*reserved*/ + volatile uint32_t slv_status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ + volatile uint32_t slv_status_fast_en: 1; /*In the slave mode enable fast read status.*/ + volatile uint32_t slv_status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ + }; + volatile uint32_t val; + }slave1; + union { + struct { + volatile uint32_t slv_rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ + volatile uint32_t slv_wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ + volatile uint32_t slv_rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ + volatile uint32_t slv_wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ + }; + volatile uint32_t val; + }slave2; + union { + struct { + volatile uint32_t slv_rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ + volatile uint32_t slv_wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ + volatile uint32_t slv_rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ + volatile uint32_t slv_wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ + }; + volatile uint32_t val; + }slave3; + union { + struct { + volatile uint32_t slv_wrbuf_dbitlen:24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }slv_wrbuf_dlen; + union { + struct { + volatile uint32_t slv_rdbuf_dbitlen:24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }slv_rdbuf_dlen; + union { + struct { + volatile uint32_t cache_req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + volatile uint32_t cache_usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + volatile uint32_t cache_flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + volatile uint32_t cache_flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ + volatile uint32_t reserved4: 28; /*reserved*/ + }; + volatile uint32_t val; + }cache_fctrl; + union { + struct { + volatile uint32_t reserved0: 1; /*reserved*/ + volatile uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ + volatile uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ + volatile uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ + volatile uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ + volatile uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ + volatile uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ + volatile uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + volatile uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + volatile uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ + volatile uint32_t reserved29: 3; /*reserved*/ + }; + volatile uint32_t val; + }cache_sctrl; + union { + struct { + volatile uint32_t sram_dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + volatile uint32_t sram_qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + volatile uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ + volatile uint32_t sram_rstio: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ + volatile uint32_t reserved5: 27; /*reserved*/ + }; + volatile uint32_t val; + }sram_cmd; + union { + struct { + volatile uint32_t cache_sram_usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ + volatile uint32_t reserved16: 12; /*reserved*/ + volatile uint32_t cache_sram_usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + volatile uint32_t val; + }sram_drd_cmd; + union { + struct { + volatile uint32_t cache_sram_usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ + volatile uint32_t reserved16: 12; /*reserved*/ + volatile uint32_t cache_sram_usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + }; + volatile uint32_t val; + }sram_dwr_cmd; + union { + struct { + volatile uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ + volatile uint32_t reserved24: 8; /*reserved*/ + }; + volatile uint32_t val; + }slv_rd_bit; + volatile uint32_t reserved_68; + volatile uint32_t reserved_6c; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t reserved_78; + volatile uint32_t reserved_7c; + volatile uint32_t data_buf[16]; /*data buffer*/ + volatile uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + union { + struct { + volatile uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ + volatile uint32_t reserved12: 4; /*reserved*/ + volatile uint32_t t_pp_shift: 4; /*page program delay time shift .*/ + volatile uint32_t reserved20:11; /*reserved*/ + volatile uint32_t t_pp_ena: 1; /*page program delay enable.*/ + }; + volatile uint32_t val; + }ext0; + union { + struct { + volatile uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ + volatile uint32_t reserved12: 4; /*reserved*/ + volatile uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ + volatile uint32_t reserved20: 11; /*reserved*/ + volatile uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ + }; + volatile uint32_t val; + }ext1; + union { + struct { + volatile uint32_t st: 3; /*The status of spi state machine .*/ + volatile uint32_t reserved3: 29; /*reserved*/ + }; + volatile uint32_t val; + }ext2; + union { + struct { + volatile uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ + volatile uint32_t reserved2: 30; /*reserved*/ + }; + volatile uint32_t val; + }ext3; + union { + struct { + volatile uint32_t reserved0: 2; /*reserved*/ + volatile uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ + volatile uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ + volatile uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ + volatile uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ + volatile uint32_t in_loop_test: 1; /*Set bit to test in link.*/ + volatile uint32_t out_loop_test: 1; /*Set bit to test out link.*/ + volatile uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ + volatile uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ + volatile uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ + volatile uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ + volatile uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ + volatile uint32_t reserved13: 1; /*reserved*/ + volatile uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ + volatile uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ + volatile uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ + volatile uint32_t reserved17: 15; /*reserved*/ + }; + volatile uint32_t val; + }dma_conf; + union { + struct { + volatile uint32_t outlink_addr: 20; /*The address of the first outlink descriptor.*/ + volatile uint32_t reserved20: 8; /*reserved*/ + volatile uint32_t outlink_stop: 1; /*Set the bit to stop to use outlink descriptor.*/ + volatile uint32_t outlink_start: 1; /*Set the bit to start to use outlink descriptor.*/ + volatile uint32_t outlink_restart: 1; /*Set the bit to mount on new outlink descriptors.*/ + volatile uint32_t reserved31: 1; /*reserved*/ + }; + volatile uint32_t val; + }dma_out_link; + union { + struct { + volatile uint32_t inlink_addr: 20; /*The address of the first inlink descriptor.*/ + volatile uint32_t inlink_auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ + volatile uint32_t reserved21: 7; /*reserved*/ + volatile uint32_t inlink_stop: 1; /*Set the bit to stop to use inlink descriptor.*/ + volatile uint32_t inlink_start: 1; /*Set the bit to start to use inlink descriptor.*/ + volatile uint32_t inlink_restart: 1; /*Set the bit to mount on new inlink descriptors.*/ + volatile uint32_t reserved31: 1; /*reserved*/ + }; + volatile uint32_t val; + }dma_in_link; + union { + struct { + volatile uint32_t dma_rx_en: 1; /*spi dma read data status bit.*/ + volatile uint32_t dma_tx_en: 1; /*spi dma write data status bit.*/ + volatile uint32_t reserved2: 30; /*spi dma read data from memory count.*/ + }; + volatile uint32_t val; + }dma_status; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_ena: 1; /*The enable bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_ena: 1; /*The enable bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_ena: 1; /*The enable bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_ena: 1; /*The enable bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_ena: 1; /*The enable bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_ena: 1; /*The enable bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_ena: 1; /*The enable bit for completing usage of a outlink descriptor .*/ + volatile uint32_t out_eof_int_ena: 1; /*The enable bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_ena: 1; /*The enable bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_ena; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_raw: 1; /*The raw bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_raw: 1; /*The raw bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_raw: 1; /*The raw bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_raw: 1; /*The raw bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_raw: 1; /*The raw bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_raw: 1; /*The raw bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_raw: 1; /*The raw bit for completing usage of a outlink descriptor.*/ + volatile uint32_t out_eof_int_raw: 1; /*The raw bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_raw: 1; /*The raw bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_raw; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_st: 1; /*The status bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_st: 1; /*The status bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_st: 1; /*The status bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_st: 1; /*The status bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_st: 1; /*The status bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_st: 1; /*The status bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_st: 1; /*The status bit for completing usage of a outlink descriptor.*/ + volatile uint32_t out_eof_int_st: 1; /*The status bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_st: 1; /*The status bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_st; + union { + struct { + volatile uint32_t inlink_dscr_empty_int_clr: 1; /*The clear bit for lack of enough inlink descriptors.*/ + volatile uint32_t outlink_dscr_error_int_clr: 1; /*The clear bit for outlink descriptor error.*/ + volatile uint32_t inlink_dscr_error_int_clr: 1; /*The clear bit for inlink descriptor error.*/ + volatile uint32_t in_done_int_clr: 1; /*The clear bit for completing usage of a inlink descriptor.*/ + volatile uint32_t in_err_eof_int_clr: 1; /*The clear bit for receiving error.*/ + volatile uint32_t in_suc_eof_int_clr: 1; /*The clear bit for completing receiving all the packets from host.*/ + volatile uint32_t out_done_int_clr: 1; /*The clear bit for completing usage of a outlink descriptor.*/ + volatile uint32_t out_eof_int_clr: 1; /*The clear bit for sending a packet to host done.*/ + volatile uint32_t out_total_eof_int_clr: 1; /*The clear bit for sending all the packets to host done.*/ + volatile uint32_t reserved9: 23; /*reserved*/ + }; + volatile uint32_t val; + }dma_int_clr; + volatile uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ + volatile uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ + volatile uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ + volatile uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ + volatile uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ + volatile uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ + volatile uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ + volatile uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ + volatile uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ + volatile uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ + volatile uint32_t dma_rx_status; /*spi dma read data from memory status.*/ + volatile uint32_t dma_tx_status; /*spi dma write data to memory status.*/ + volatile uint32_t reserved_150; + volatile uint32_t reserved_154; + volatile uint32_t reserved_158; + volatile uint32_t reserved_15c; + volatile uint32_t reserved_160; + volatile uint32_t reserved_164; + volatile uint32_t reserved_168; + volatile uint32_t reserved_16c; + volatile uint32_t reserved_170; + volatile uint32_t reserved_174; + volatile uint32_t reserved_178; + volatile uint32_t reserved_17c; + volatile uint32_t reserved_180; + volatile uint32_t reserved_184; + volatile uint32_t reserved_188; + volatile uint32_t reserved_18c; + volatile uint32_t reserved_190; + volatile uint32_t reserved_194; + volatile uint32_t reserved_198; + volatile uint32_t reserved_19c; + volatile uint32_t reserved_1a0; + volatile uint32_t reserved_1a4; + volatile uint32_t reserved_1a8; + volatile uint32_t reserved_1ac; + volatile uint32_t reserved_1b0; + volatile uint32_t reserved_1b4; + volatile uint32_t reserved_1b8; + volatile uint32_t reserved_1bc; + volatile uint32_t reserved_1c0; + volatile uint32_t reserved_1c4; + volatile uint32_t reserved_1c8; + volatile uint32_t reserved_1cc; + volatile uint32_t reserved_1d0; + volatile uint32_t reserved_1d4; + volatile uint32_t reserved_1d8; + volatile uint32_t reserved_1dc; + volatile uint32_t reserved_1e0; + volatile uint32_t reserved_1e4; + volatile uint32_t reserved_1e8; + volatile uint32_t reserved_1ec; + volatile uint32_t reserved_1f0; + volatile uint32_t reserved_1f4; + volatile uint32_t reserved_1f8; + volatile uint32_t reserved_1fc; + volatile uint32_t reserved_200; + volatile uint32_t reserved_204; + volatile uint32_t reserved_208; + volatile uint32_t reserved_20c; + volatile uint32_t reserved_210; + volatile uint32_t reserved_214; + volatile uint32_t reserved_218; + volatile uint32_t reserved_21c; + volatile uint32_t reserved_220; + volatile uint32_t reserved_224; + volatile uint32_t reserved_228; + volatile uint32_t reserved_22c; + volatile uint32_t reserved_230; + volatile uint32_t reserved_234; + volatile uint32_t reserved_238; + volatile uint32_t reserved_23c; + volatile uint32_t reserved_240; + volatile uint32_t reserved_244; + volatile uint32_t reserved_248; + volatile uint32_t reserved_24c; + volatile uint32_t reserved_250; + volatile uint32_t reserved_254; + volatile uint32_t reserved_258; + volatile uint32_t reserved_25c; + volatile uint32_t reserved_260; + volatile uint32_t reserved_264; + volatile uint32_t reserved_268; + volatile uint32_t reserved_26c; + volatile uint32_t reserved_270; + volatile uint32_t reserved_274; + volatile uint32_t reserved_278; + volatile uint32_t reserved_27c; + volatile uint32_t reserved_280; + volatile uint32_t reserved_284; + volatile uint32_t reserved_288; + volatile uint32_t reserved_28c; + volatile uint32_t reserved_290; + volatile uint32_t reserved_294; + volatile uint32_t reserved_298; + volatile uint32_t reserved_29c; + volatile uint32_t reserved_2a0; + volatile uint32_t reserved_2a4; + volatile uint32_t reserved_2a8; + volatile uint32_t reserved_2ac; + volatile uint32_t reserved_2b0; + volatile uint32_t reserved_2b4; + volatile uint32_t reserved_2b8; + volatile uint32_t reserved_2bc; + volatile uint32_t reserved_2c0; + volatile uint32_t reserved_2c4; + volatile uint32_t reserved_2c8; + volatile uint32_t reserved_2cc; + volatile uint32_t reserved_2d0; + volatile uint32_t reserved_2d4; + volatile uint32_t reserved_2d8; + volatile uint32_t reserved_2dc; + volatile uint32_t reserved_2e0; + volatile uint32_t reserved_2e4; + volatile uint32_t reserved_2e8; + volatile uint32_t reserved_2ec; + volatile uint32_t reserved_2f0; + volatile uint32_t reserved_2f4; + volatile uint32_t reserved_2f8; + volatile uint32_t reserved_2fc; + volatile uint32_t reserved_300; + volatile uint32_t reserved_304; + volatile uint32_t reserved_308; + volatile uint32_t reserved_30c; + volatile uint32_t reserved_310; + volatile uint32_t reserved_314; + volatile uint32_t reserved_318; + volatile uint32_t reserved_31c; + volatile uint32_t reserved_320; + volatile uint32_t reserved_324; + volatile uint32_t reserved_328; + volatile uint32_t reserved_32c; + volatile uint32_t reserved_330; + volatile uint32_t reserved_334; + volatile uint32_t reserved_338; + volatile uint32_t reserved_33c; + volatile uint32_t reserved_340; + volatile uint32_t reserved_344; + volatile uint32_t reserved_348; + volatile uint32_t reserved_34c; + volatile uint32_t reserved_350; + volatile uint32_t reserved_354; + volatile uint32_t reserved_358; + volatile uint32_t reserved_35c; + volatile uint32_t reserved_360; + volatile uint32_t reserved_364; + volatile uint32_t reserved_368; + volatile uint32_t reserved_36c; + volatile uint32_t reserved_370; + volatile uint32_t reserved_374; + volatile uint32_t reserved_378; + volatile uint32_t reserved_37c; + volatile uint32_t reserved_380; + volatile uint32_t reserved_384; + volatile uint32_t reserved_388; + volatile uint32_t reserved_38c; + volatile uint32_t reserved_390; + volatile uint32_t reserved_394; + volatile uint32_t reserved_398; + volatile uint32_t reserved_39c; + volatile uint32_t reserved_3a0; + volatile uint32_t reserved_3a4; + volatile uint32_t reserved_3a8; + volatile uint32_t reserved_3ac; + volatile uint32_t reserved_3b0; + volatile uint32_t reserved_3b4; + volatile uint32_t reserved_3b8; + volatile uint32_t reserved_3bc; + volatile uint32_t reserved_3c0; + volatile uint32_t reserved_3c4; + volatile uint32_t reserved_3c8; + volatile uint32_t reserved_3cc; + volatile uint32_t reserved_3d0; + volatile uint32_t reserved_3d4; + volatile uint32_t reserved_3d8; + volatile uint32_t reserved_3dc; + volatile uint32_t reserved_3e0; + volatile uint32_t reserved_3e4; + volatile uint32_t reserved_3e8; + volatile uint32_t reserved_3ec; + volatile uint32_t reserved_3f0; + volatile uint32_t reserved_3f4; + volatile uint32_t reserved_3f8; + union { + struct { + volatile uint32_t date: 28; /*SPI register version.*/ + volatile uint32_t reserved28: 4; /*reserved*/ + }; + volatile uint32_t val; + }date; +} spi_dev_t; +extern volatile spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ +extern volatile spi_dev_t SPI1; +extern volatile spi_dev_t SPI2; +extern volatile spi_dev_t SPI3; +#endif /* _SOC_SPI_STRUCT_H_ */ diff --git a/components/esp32/include/soc/timer_group_struct.h b/components/esp32/include/soc/timer_group_struct.h new file mode 100644 index 000000000..b385f04f7 --- /dev/null +++ b/components/esp32/include/soc/timer_group_struct.h @@ -0,0 +1,195 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_TIMG_STRUCT_H_ +#define _SOC_TIMG_STRUCT_H_ +typedef struct { + struct{ + union { + struct { + volatile uint32_t reserved0: 10; + volatile uint32_t alarm_en: 1; /*When set alarm is enabled*/ + volatile uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + volatile uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + volatile uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + volatile uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + volatile uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + volatile uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + }; + volatile uint32_t val; + }config; + volatile uint32_t timer_cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + volatile uint32_t timer_cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + volatile uint32_t timer_update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + volatile uint32_t timer_alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + volatile uint32_t timer_alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + volatile uint32_t timer_load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + volatile uint32_t timer_load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + volatile uint32_t timer_reload; /*Write any value will trigger timer 0 time-base counter reload*/ + }hw_timer[2]; + union { + struct { + volatile uint32_t reserved0: 14; + volatile uint32_t wdt_flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ + volatile uint32_t wdt_sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + volatile uint32_t wdt_cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + volatile uint32_t wdt_level_int_en: 1; /*When set level type interrupt generation is enabled*/ + volatile uint32_t wdt_edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ + volatile uint32_t wdt_stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + volatile uint32_t wdt_en: 1; /*When set SWDT is enabled*/ + }; + volatile uint32_t val; + }wdt_config0; + union { + struct { + volatile uint32_t reserved0: 16; + volatile uint32_t wdt_clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ + }; + volatile uint32_t val; + }wdt_config1; + volatile uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ + volatile uint32_t wdt_feed; /*Write any value will feed SWDT*/ + volatile uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ + union { + struct { + volatile uint32_t reserved0: 12; + volatile uint32_t rtc_cali_start_cycling: 1; + volatile uint32_t rtc_cali_clk_sel: 2; + volatile uint32_t rtc_cali_rdy: 1; + volatile uint32_t rtc_cali_max: 15; + volatile uint32_t rtc_cali_start: 1; + }; + volatile uint32_t val; + }rtc_cali_cfg; + union { + struct { + volatile uint32_t reserved0: 7; + volatile uint32_t rtc_cali_value:25; + }; + volatile uint32_t val; + }rtc_cali_cfg1; + union { + struct { + volatile uint32_t reserved0: 7; + volatile uint32_t lact_rtc_only: 1; + volatile uint32_t lact_cpst_en: 1; + volatile uint32_t lact_lac_en: 1; + volatile uint32_t lact_alarm_en: 1; + volatile uint32_t lact_level_int_en: 1; + volatile uint32_t lact_edge_int_en: 1; + volatile uint32_t lact_divider: 16; + volatile uint32_t lact_autoreload: 1; + volatile uint32_t lact_increase: 1; + volatile uint32_t lact_en: 1; + }; + volatile uint32_t val; + }lactconfig; + union { + struct { + volatile uint32_t reserved0: 6; + volatile uint32_t lact_rtc_step_len:26; + }; + volatile uint32_t val; + }lactrtc; + volatile uint32_t lactlo; /**/ + volatile uint32_t lacthi; /**/ + volatile uint32_t lactupdate; /**/ + volatile uint32_t lactalarmlo; /**/ + volatile uint32_t lactalarmhi; /**/ + volatile uint32_t lactloadlo; /**/ + volatile uint32_t lactloadhi; /**/ + volatile uint32_t lactload; /**/ + union { + struct { + volatile uint32_t t0_int_ena: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_ena: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_ena: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_ena: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_ena_timers; + union { + struct { + volatile uint32_t t0_int_raw: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_raw: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_raw: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_raw: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_raw_timers; + union { + struct { + volatile uint32_t t0_int_st: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_st: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_st: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_st: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_st_timers; + union { + struct { + volatile uint32_t t0_int_clr: 1; /*interrupt when timer0 alarm*/ + volatile uint32_t t1_int_clr: 1; /*interrupt when timer1 alarm*/ + volatile uint32_t wdt_int_clr: 1; /*Interrupt when an interrupt stage timeout*/ + volatile uint32_t lact_int_clr: 1; + volatile uint32_t reserved4: 28; + }; + volatile uint32_t val; + }int_clr_timers; + volatile uint32_t reserved_a8; + volatile uint32_t reserved_ac; + volatile uint32_t reserved_b0; + volatile uint32_t reserved_b4; + volatile uint32_t reserved_b8; + volatile uint32_t reserved_bc; + volatile uint32_t reserved_c0; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + union { + struct { + volatile uint32_t date:28; /*Version of this regfile*/ + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }timg_date; + union { + struct { + volatile uint32_t reserved0: 31; + volatile uint32_t clk_en: 1; /*Force clock enable for this regfile*/ + }; + volatile uint32_t val; + }clk; +} timg_dev_t; +extern volatile timg_dev_t TIMERG0; +extern volatile timg_dev_t TIMERG1; +#endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/components/esp32/include/soc/uart_struct.h b/components/esp32/include/soc/uart_struct.h new file mode 100644 index 000000000..cd756bec3 --- /dev/null +++ b/components/esp32/include/soc/uart_struct.h @@ -0,0 +1,365 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UART_STRUCT_H_ +#define _SOC_UART_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t fifo_rw_byte: 8; /*This register stores one byte data read by rx fifo.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }fifo; + union { + struct { + volatile uint32_t rxfifo_full_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + volatile uint32_t txfifo_empty_int_raw: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ + volatile uint32_t parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ + volatile uint32_t frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ + volatile uint32_t rxfifo_ovf_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ + volatile uint32_t dsr_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ + volatile uint32_t cts_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ + volatile uint32_t brk_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ + volatile uint32_t rxfifo_tout_int_raw: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + volatile uint32_t sw_xon_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ + volatile uint32_t sw_xoff_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ + volatile uint32_t glitch_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ + volatile uint32_t tx_brk_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ + volatile uint32_t tx_brk_idle_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ + volatile uint32_t tx_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ + volatile uint32_t rs485_parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ + volatile uint32_t rs485_frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ + volatile uint32_t rs485_clash_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ + volatile uint32_t at_cmd_char_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rxfifo_full_int_st: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + volatile uint32_t txfifo_empty_int_st: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + volatile uint32_t parity_err_int_st: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + volatile uint32_t frm_err_int_st: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ + volatile uint32_t rxfifo_ovf_int_st: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + volatile uint32_t dsr_chg_int_st: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + volatile uint32_t cts_chg_int_st: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + volatile uint32_t brk_det_int_st: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + volatile uint32_t rxfifo_tout_int_st: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + volatile uint32_t sw_xon_int_st: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + volatile uint32_t sw_xoff_int_st: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + volatile uint32_t glitch_det_int_st: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + volatile uint32_t tx_brk_done_int_st: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + volatile uint32_t tx_brk_idle_done_int_st: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + volatile uint32_t tx_done_int_st: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + volatile uint32_t rs485_parity_err_int_st: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + volatile uint32_t rs485_frm_err_int_st: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + volatile uint32_t rs485_clash_int_st: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + volatile uint32_t at_cmd_char_det_int_st: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t rxfifo_full_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + volatile uint32_t txfifo_empty_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + volatile uint32_t parity_err_int_ena: 1; /*This is the enable bit for parity_err_int_st register.*/ + volatile uint32_t frm_err_int_ena: 1; /*This is the enable bit for frm_err_int_st register.*/ + volatile uint32_t rxfifo_ovf_int_ena: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + volatile uint32_t dsr_chg_int_ena: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + volatile uint32_t cts_chg_int_ena: 1; /*This is the enable bit for cts_chg_int_st register.*/ + volatile uint32_t brk_det_int_ena: 1; /*This is the enable bit for brk_det_int_st register.*/ + volatile uint32_t rxfifo_tout_int_ena: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + volatile uint32_t sw_xon_int_ena: 1; /*This is the enable bit for sw_xon_int_st register.*/ + volatile uint32_t sw_xoff_int_ena: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + volatile uint32_t glitch_det_int_ena: 1; /*This is the enable bit for glitch_det_int_st register.*/ + volatile uint32_t tx_brk_done_int_ena: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + volatile uint32_t tx_brk_idle_done_int_ena: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + volatile uint32_t tx_done_int_ena: 1; /*This is the enable bit for tx_done_int_st register.*/ + volatile uint32_t rs485_parity_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + volatile uint32_t rs485_frm_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + volatile uint32_t rs485_clash_int_ena: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + volatile uint32_t at_cmd_char_det_int_ena: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t rxfifo_full_int_clr: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + volatile uint32_t txfifo_empty_int_clr: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + volatile uint32_t parity_err_int_clr: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + volatile uint32_t frm_err_int_clr: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + volatile uint32_t rxfifo_ovf_int_clr: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + volatile uint32_t dsr_chg_int_clr: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + volatile uint32_t cts_chg_int_clr: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + volatile uint32_t brk_det_int_clr: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + volatile uint32_t rxfifo_tout_int_clr: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + volatile uint32_t sw_xon_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + volatile uint32_t sw_xoff_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + volatile uint32_t glitch_det_int_clr: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + volatile uint32_t tx_brk_done_int_clr: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + volatile uint32_t tx_brk_idle_done_int_clr: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + volatile uint32_t tx_done_int_clr: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + volatile uint32_t rs485_parity_err_int_clr: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + volatile uint32_t rs485_frm_err_int_clr: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + volatile uint32_t rs485_clash_int_clr: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + volatile uint32_t at_cmd_char_det_int_clr: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + volatile uint32_t reserved19: 13; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t clkdiv: 20; /*The register value is the integer part of the frequency divider's factor.*/ + volatile uint32_t clkdiv_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }clk_div; + union { + struct { + volatile uint32_t auto_baud_en: 1; /*This is the enable bit for detecting baudrate.*/ + volatile uint32_t reserved1: 7; + volatile uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }auto_baud; + union { + struct { + volatile uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ + volatile uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ + volatile uint32_t reserved12: 1; + volatile uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ + volatile uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ + volatile uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ + volatile uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ + volatile uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ + volatile uint32_t reserved28: 1; + volatile uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ + volatile uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ + volatile uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + }; + volatile uint32_t val; + }status; + union { + struct { + volatile uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ + volatile uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ + volatile uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ + volatile uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ + volatile uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + volatile uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ + volatile uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ + volatile uint32_t irda_dplx: 1; /*Set this bit to enable irda loopback mode.*/ + volatile uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ + volatile uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ + volatile uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ + volatile uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ + volatile uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ + volatile uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ + volatile uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ + volatile uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ + volatile uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ + volatile uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + volatile uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ + volatile uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + volatile uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ + volatile uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ + volatile uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + volatile uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ + volatile uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ + volatile uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ + volatile uint32_t reserved7: 1; + volatile uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ + volatile uint32_t reserved15: 1; + volatile uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + volatile uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ + volatile uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ + volatile uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ + }; + volatile uint32_t val; + }conf1; + union { + struct { + volatile uint32_t lowpulse_min_cnt:20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }lowpulse; + union { + struct { + volatile uint32_t highpulse_min_cnt:20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }highpulse; + union { + struct { + volatile uint32_t rxd_edge_cnt:10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }rxd_cnt; + union { + struct { + volatile uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ + volatile uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ + volatile uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ + volatile uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ + volatile uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ + volatile uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }flow_conf; + union { + struct { + volatile uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }sleep_conf; + union { + struct { + volatile uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ + volatile uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ + volatile uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ + volatile uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + }; + volatile uint32_t val; + }swfc_conf; + union { + struct { + volatile uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ + volatile uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ + volatile uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + volatile uint32_t reserved28: 4; + }; + volatile uint32_t val; + }idle_conf; + union { + struct { + volatile uint32_t rs485_en: 1; /*Set this bit to choose rs485 mode.*/ + volatile uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + volatile uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + volatile uint32_t rs485tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ + volatile uint32_t rs485rxby_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ + volatile uint32_t rs485_rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + volatile uint32_t rs485_tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + volatile uint32_t reserved10: 22; + }; + volatile uint32_t val; + }rs485_conf; + union { + struct { + volatile uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }at_cmd_precnt; + union { + struct { + volatile uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }at_cmd_postcnt; + union { + struct { + volatile uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }at_cmd_gaptout; + union { + struct { + volatile uint32_t at_cmd_char: 8; /*This register is used to configure the content of at_cmd char.*/ + volatile uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + volatile uint32_t reserved16: 16; + }; + volatile uint32_t val; + }at_cmd_char; + union { + struct { + volatile uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ + volatile uint32_t reserved1: 1; + volatile uint32_t reserved2: 1; + volatile uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ + volatile uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ + volatile uint32_t reserved11: 4; + volatile uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ + volatile uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ + volatile uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ + volatile uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ + volatile uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ + volatile uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ + volatile uint32_t reserved31: 1; + }; + volatile uint32_t val; + }mem_conf; + union { + struct { + volatile uint32_t mem_tx_status:24; + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }mem_tx_status; + union { + struct { + volatile uint32_t mem_rx_status:24; + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }mem_rx_status; + union { + struct { + volatile uint32_t rx_mem_cnt: 3; /*refer to the rxfifo_cnt's description.*/ + volatile uint32_t tx_mem_cnt: 3; /*refer to the txfifo_cnt's description.*/ + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }mem_cnt_status; + union { + struct { + volatile uint32_t posedge_min_cnt:20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }pospulse; + union { + struct { + volatile uint32_t negedge_min_cnt:20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ + volatile uint32_t reserved20: 12; + }; + volatile uint32_t val; + }negpulse; + volatile uint32_t reserved_70; + volatile uint32_t reserved_74; + volatile uint32_t date; /**/ + volatile uint32_t id; /**/ +} uart_dev_t; +extern volatile uart_dev_t UART0; +extern volatile uart_dev_t UART1; +extern volatile uart_dev_t UART2; +#endif /* _SOC_UART_STRUCT_H_ */ diff --git a/components/esp32/include/soc/uhci_struct.h b/components/esp32/include/soc/uhci_struct.h new file mode 100644 index 000000000..323d3beac --- /dev/null +++ b/components/esp32/include/soc/uhci_struct.h @@ -0,0 +1,337 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#ifndef _SOC_UHCI_STRUCT_H_ +#define _SOC_UHCI_STRUCT_H_ +typedef struct { + union { + struct { + volatile uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ + volatile uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ + volatile uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ + volatile uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ + volatile uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ + volatile uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ + volatile uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ + volatile uint32_t out_no_restart_clr: 1; /*don't use*/ + volatile uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ + volatile uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ + volatile uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ + volatile uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ + volatile uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ + volatile uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ + volatile uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ + volatile uint32_t mem_trans_en: 1; + volatile uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ + volatile uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ + volatile uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ + volatile uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ + volatile uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ + volatile uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ + volatile uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ + volatile uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }conf0; + union { + struct { + volatile uint32_t rx_start_int_raw: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ + volatile uint32_t tx_start_int_raw: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ + volatile uint32_t rx_hung_int_raw: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ + volatile uint32_t tx_hung_int_raw: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ + volatile uint32_t in_done_int_raw: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ + volatile uint32_t in_suc_eof_int_raw: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ + volatile uint32_t in_err_eof_int_raw: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ + volatile uint32_t out_done_int_raw: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ + volatile uint32_t out_eof_int_raw: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ + volatile uint32_t in_dscr_err_int_raw: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ + volatile uint32_t out_dscr_err_int_raw: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ + volatile uint32_t in_dscr_empty_int_raw: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ + volatile uint32_t outlink_eof_err_int_raw: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ + volatile uint32_t out_total_eof_int_raw: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ + volatile uint32_t send_s_q_int_raw: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ + volatile uint32_t send_a_q_int_raw: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ + volatile uint32_t dma_infifo_full_wm_int_raw: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_raw; + union { + struct { + volatile uint32_t rx_start_int_st: 1; + volatile uint32_t tx_start_int_st: 1; + volatile uint32_t rx_hung_int_st: 1; + volatile uint32_t tx_hung_int_st: 1; + volatile uint32_t in_done_int_st: 1; + volatile uint32_t in_suc_eof_int_st: 1; + volatile uint32_t in_err_eof_int_st: 1; + volatile uint32_t out_done_int_st: 1; + volatile uint32_t out_eof_int_st: 1; + volatile uint32_t in_dscr_err_int_st: 1; + volatile uint32_t out_dscr_err_int_st: 1; + volatile uint32_t in_dscr_empty_int_st: 1; + volatile uint32_t outlink_eof_err_int_st: 1; + volatile uint32_t out_total_eof_int_st: 1; + volatile uint32_t send_s_q_int_st: 1; + volatile uint32_t send_a_q_int_st: 1; + volatile uint32_t dma_infifo_full_wm_int_st: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_st; + union { + struct { + volatile uint32_t rx_start_int_ena: 1; + volatile uint32_t tx_start_int_ena: 1; + volatile uint32_t rx_hung_int_ena: 1; + volatile uint32_t tx_hung_int_ena: 1; + volatile uint32_t in_done_int_ena: 1; + volatile uint32_t in_suc_eof_int_ena: 1; + volatile uint32_t in_err_eof_int_ena: 1; + volatile uint32_t out_done_int_ena: 1; + volatile uint32_t out_eof_int_ena: 1; + volatile uint32_t in_dscr_err_int_ena: 1; + volatile uint32_t out_dscr_err_int_ena: 1; + volatile uint32_t in_dscr_empty_int_ena: 1; + volatile uint32_t outlink_eof_err_int_ena: 1; + volatile uint32_t out_total_eof_int_ena: 1; + volatile uint32_t send_s_q_int_ena: 1; + volatile uint32_t send_a_q_int_ena: 1; + volatile uint32_t dma_infifo_full_wm_int_ena: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_ena; + union { + struct { + volatile uint32_t rx_start_int_clr: 1; + volatile uint32_t tx_start_int_clr: 1; + volatile uint32_t rx_hung_int_clr: 1; + volatile uint32_t tx_hung_int_clr: 1; + volatile uint32_t in_done_int_clr: 1; + volatile uint32_t in_suc_eof_int_clr: 1; + volatile uint32_t in_err_eof_int_clr: 1; + volatile uint32_t out_done_int_clr: 1; + volatile uint32_t out_eof_int_clr: 1; + volatile uint32_t in_dscr_err_int_clr: 1; + volatile uint32_t out_dscr_err_int_clr: 1; + volatile uint32_t in_dscr_empty_int_clr: 1; + volatile uint32_t outlink_eof_err_int_clr: 1; + volatile uint32_t out_total_eof_int_clr: 1; + volatile uint32_t send_s_q_int_clr: 1; + volatile uint32_t send_a_q_int_clr: 1; + volatile uint32_t dma_infifo_full_wm_int_clr: 1; + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }int_clr; + union { + struct { + volatile uint32_t out_full: 1; /*1:DMA out link descriptor's fifo is full.*/ + volatile uint32_t out_empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ + volatile uint32_t reserved2: 30; + }; + volatile uint32_t val; + }dma_out_status; + union { + struct { + volatile uint32_t outfifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ + volatile uint32_t reserved9: 7; + volatile uint32_t outfifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }dma_out_push; + union { + struct { + volatile uint32_t in_full: 1; + volatile uint32_t in_empty: 1; + volatile uint32_t reserved2: 2; + volatile uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ + volatile uint32_t reserved7: 25; + }; + volatile uint32_t val; + }dma_in_status; + union { + struct { + volatile uint32_t infifo_rdata:12; /*This register stores the data pop from in link descriptor's fifo.*/ + volatile uint32_t reserved12: 4; + volatile uint32_t infifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ + volatile uint32_t reserved17: 15; + }; + volatile uint32_t val; + }dma_in_pop; + union { + struct { + volatile uint32_t outlink_addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ + volatile uint32_t reserved20: 8; + volatile uint32_t outlink_stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ + volatile uint32_t outlink_start: 1; /*Set this bit to start dealing with the out link descriptors.*/ + volatile uint32_t outlink_restart: 1; /*Set this bit to mount on new out link descriptors*/ + volatile uint32_t outlink_park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ + }; + volatile uint32_t val; + }dma_out_link; + union { + struct { + volatile uint32_t inlink_addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ + volatile uint32_t inlink_auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ + volatile uint32_t reserved21: 7; + volatile uint32_t inlink_stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ + volatile uint32_t inlink_start: 1; /*Set this bit to start dealing with the in link descriptors.*/ + volatile uint32_t inlink_restart: 1; /*Set this bit to mount on new in link descriptors*/ + volatile uint32_t inlink_park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ + }; + volatile uint32_t val; + }dma_in_link; + union { + struct { + volatile uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ + volatile uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ + volatile uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ + volatile uint32_t save_head: 1; /*Set this bit to save packet header .*/ + volatile uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ + volatile uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ + volatile uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ + volatile uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ + volatile uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ + volatile uint32_t dma_infifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ + volatile uint32_t reserved21: 11; + }; + volatile uint32_t val; + }conf1; + volatile uint32_t state0; /**/ + volatile uint32_t state1; /**/ + volatile uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ + volatile uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ + volatile uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ + volatile uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ + union { + struct { + volatile uint32_t ahb_testmode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ + volatile uint32_t reserved3: 1; + volatile uint32_t ahb_testaddr: 2; /*The two bits represent ahb bus address bit[20:19]*/ + volatile uint32_t reserved6: 26; + }; + volatile uint32_t val; + }ahb_test; + volatile uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ + volatile uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ + volatile uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ + volatile uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ + volatile uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ + volatile uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ + union { + struct { + volatile uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ + volatile uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ + volatile uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ + volatile uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ + volatile uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ + volatile uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ + volatile uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ + volatile uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }escape_conf; + union { + struct { + volatile uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ + volatile uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ + volatile uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ + volatile uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ + volatile uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ + volatile uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }hung_conf; + volatile uint32_t ack_num; /**/ + volatile uint32_t rx_head; /*This register stores the packet header received by DMA*/ + union { + struct { + volatile uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ + volatile uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ + volatile uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ + volatile uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ + volatile uint32_t reserved8: 24; + }; + volatile uint32_t val; + }quick_sent; + struct{ + volatile uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ + }q_data[7]; + union { + struct { + volatile uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ + volatile uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ + volatile uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf0; + union { + struct { + volatile uint32_t esc_seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ + volatile uint32_t esc_seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ + volatile uint32_t esc_seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf1; + union { + struct { + volatile uint32_t esc_seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ + volatile uint32_t esc_seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ + volatile uint32_t esc_seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf2; + union { + struct { + volatile uint32_t esc_seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ + volatile uint32_t esc_seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ + volatile uint32_t esc_seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ + volatile uint32_t reserved24: 8; + }; + volatile uint32_t val; + }esc_conf3; + union { + struct { + volatile uint32_t pkt_thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ + volatile uint32_t reserved13:19; + }; + volatile uint32_t val; + }pkt_thres; + volatile uint32_t reserved_c4; + volatile uint32_t reserved_c8; + volatile uint32_t reserved_cc; + volatile uint32_t reserved_d0; + volatile uint32_t reserved_d4; + volatile uint32_t reserved_d8; + volatile uint32_t reserved_dc; + volatile uint32_t reserved_e0; + volatile uint32_t reserved_e4; + volatile uint32_t reserved_e8; + volatile uint32_t reserved_ec; + volatile uint32_t reserved_f0; + volatile uint32_t reserved_f4; + volatile uint32_t reserved_f8; + volatile uint32_t date; /*version information*/ +} uhci_dev_t; +extern volatile uhci_dev_t UHCI0; +extern volatile uhci_dev_t UHCI1; +#endif /* _SOC_UHCI_STRUCT_H_ */ diff --git a/components/esp32/ld/esp32.rom.ld b/components/esp32/ld/esp32.rom.ld index 823ca4c6e..f8aa70631 100644 --- a/components/esp32/ld/esp32.rom.ld +++ b/components/esp32/ld/esp32.rom.ld @@ -1836,4 +1836,25 @@ PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); -PROVIDE ( I2S0 = 0x6000F000 ); +PROVIDE ( I2S0 = 0x3ff4F000 ); +PROVIDE ( I2S1 = 0x3ff6D000 ); +PROVIDE ( GPIO = 0x3ff44000 ); +PROVIDE ( SIGMADELTA = 0x3ff44f00 ); +PROVIDE ( I2C0 = 0x3ff53000 ); +PROVIDE ( I2C1 = 0x3ff67000 ); +PROVIDE ( LEDC = 0x3ff59000 ); +PROVIDE ( PCNT = 0x3ff57000 ); +PROVIDE ( RMT = 0x3ff56000 ); +PROVIDE ( SPI0 = 0x3ff43000 ); +PROVIDE ( SPI1 = 0x3ff42000 ); +PROVIDE ( SPI2 = 0x3ff64000 ); +PROVIDE ( SPI3 = 0x3ff65000 ); +PROVIDE ( TIMERG0 = 0x3ff5F000 ); +PROVIDE ( TIMERG1 = 0x3ff60000 ); +PROVIDE ( UART0 = 0x3ff40000 ); +PROVIDE ( UART1 = 0x3ff50000 ); +PROVIDE ( UART2 = 0x3ff6E000 ); +PROVIDE ( UHCI0 = 0x3ff54000 ); +PROVIDE ( UHCI1 = 0x3ff4C000 ); + + From f703acd34464b2ca3e27c16bd3540b55f54d5393 Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Sun, 18 Sep 2016 12:10:01 +0800 Subject: [PATCH 41/57] Adding -fstrict-volatile-bitfields to the CFLAGS/CXXFLAGS. Without this, gcc tries to access bitfields using the smallest possible methods (eg l8i to grab an 8-bit field from a 32-bit). Our hardware does not like that. This flag tells gcc that if a bitfield is volatile, it should always use the type the field is defined at (uint32_t in our case) to size its access to the field. This fixes accessing the hardware through the xxx_struct.h headers. --- make/project.mk | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/make/project.mk b/make/project.mk index b86470bf6..35dccaf24 100644 --- a/make/project.mk +++ b/make/project.mk @@ -158,13 +158,14 @@ LDFLAGS ?= -nostdlib \ # files, set CFLAGS += in your component's Makefile.projbuild # CPPFLAGS used by an compile pass that uses the C preprocessor -CPPFLAGS = -DESP_PLATFORM -Og -g3 -Wpointer-arith -Werror -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wall -ffunction-sections -fdata-sections -mlongcalls -nostdlib -MMD -MP +CPPFLAGS = -DESP_PLATFORM -Og -g3 -Wpointer-arith -Werror -Wno-error=unused-function -Wno-error=unused-but-set-variable \ + -Wno-error=unused-variable -Wall -ffunction-sections -fdata-sections -mlongcalls -nostdlib -MMD -MP # C flags use by C only -CFLAGS = $(CPPFLAGS) -std=gnu99 -g3 -fno-inline-functions +CFLAGS = $(CPPFLAGS) -std=gnu99 -g3 -fstrict-volatile-bitfields # CXXFLAGS uses by C++ only -CXXFLAGS = $(CPPFLAGS) -Og -std=gnu++11 -g3 -fno-exceptions +CXXFLAGS = $(CPPFLAGS) -Og -std=gnu++11 -g3 -fno-exceptions -fstrict-volatile-bitfields export CFLAGS CPPFLAGS CXXFLAGS From 9938f512f33f2daeca38dee36f2feef2da3fd42c Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Sun, 18 Sep 2016 12:36:33 +0800 Subject: [PATCH 42/57] peripheral structure headers: move volatile keyword from members to typedef --- components/esp32/include/soc/gpio_sd_struct.h | 30 +- components/esp32/include/soc/gpio_struct.h | 198 ++-- components/esp32/include/soc/i2c_struct.h | 368 +++--- components/esp32/include/soc/i2s_struct.h | 638 +++++------ components/esp32/include/soc/ledc_struct.h | 398 +++---- components/esp32/include/soc/pcnt_struct.h | 212 ++-- components/esp32/include/soc/rmt_struct.h | 346 +++--- components/esp32/include/soc/spi_struct.h | 1016 ++++++++--------- .../esp32/include/soc/timer_group_struct.h | 248 ++-- components/esp32/include/soc/uart_struct.h | 472 ++++---- components/esp32/include/soc/uhci_struct.h | 468 ++++---- 11 files changed, 2197 insertions(+), 2197 deletions(-) diff --git a/components/esp32/include/soc/gpio_sd_struct.h b/components/esp32/include/soc/gpio_sd_struct.h index a1b17bfc5..d06ad2e9a 100644 --- a/components/esp32/include/soc/gpio_sd_struct.h +++ b/components/esp32/include/soc/gpio_sd_struct.h @@ -13,36 +13,36 @@ // limitations under the License. #ifndef _SOC_GPIO_SD_STRUCT_H_ #define _SOC_GPIO_SD_STRUCT_H_ -typedef struct { +typedef volatile struct { union { struct { - volatile uint32_t sd_in: 8; - volatile uint32_t prescale: 8; - volatile uint32_t reserved16: 16; + uint32_t sd_in: 8; + uint32_t prescale: 8; + uint32_t reserved16: 16; }; - volatile uint32_t val; + uint32_t val; }sigmadelta[8]; union { struct { - volatile uint32_t reserved0: 31; - volatile uint32_t clk_en: 1; + uint32_t reserved0: 31; + uint32_t clk_en: 1; }; - volatile uint32_t val; + uint32_t val; }sigmadelta_cg; union { struct { - volatile uint32_t reserved0: 31; - volatile uint32_t spi_swap: 1; + uint32_t reserved0: 31; + uint32_t spi_swap: 1; }; - volatile uint32_t val; + uint32_t val; }sigmadelta_misc; union { struct { - volatile uint32_t date: 28; - volatile uint32_t reserved28: 4; + uint32_t date: 28; + uint32_t reserved28: 4; }; - volatile uint32_t val; + uint32_t val; }sigmadelta_version; } gpio_sd_dev_t; -extern volatile gpio_sd_dev_t SIGMADELTA; +extern gpio_sd_dev_t SIGMADELTA; #endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/components/esp32/include/soc/gpio_struct.h b/components/esp32/include/soc/gpio_struct.h index f42de7a29..080d638e9 100644 --- a/components/esp32/include/soc/gpio_struct.h +++ b/components/esp32/include/soc/gpio_struct.h @@ -13,192 +13,192 @@ // limitations under the License. #ifndef _SOC_GPIO_STRUCT_H_ #define _SOC_GPIO_STRUCT_H_ -typedef struct { - volatile uint32_t bt_select; /*NA*/ - volatile uint32_t out; /*GPIO0~31 output value*/ - volatile uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ - volatile uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ +typedef volatile struct { + uint32_t bt_select; /*NA*/ + uint32_t out; /*GPIO0~31 output value*/ + uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/ + uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ union { struct { - volatile uint32_t out_data: 8; /*GPIO32~39 output value*/ - volatile uint32_t reserved8: 24; + uint32_t out_data: 8; /*GPIO32~39 output value*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }out1; union { struct { - volatile uint32_t out_data: 8; /*GPIO32~39 output value write 1 to set*/ - volatile uint32_t reserved8: 24; + uint32_t out_data: 8; /*GPIO32~39 output value write 1 to set*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }out1_w1ts; union { struct { - volatile uint32_t out_data: 8; /*GPIO32~39 output value write 1 to clear*/ - volatile uint32_t reserved8: 24; + uint32_t out_data: 8; /*GPIO32~39 output value write 1 to clear*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }out1_w1tc; union { struct { - volatile uint32_t sdio_sel: 8; /*SDIO PADS on/off control from outside*/ - volatile uint32_t reserved8: 24; + uint32_t sdio_sel: 8; /*SDIO PADS on/off control from outside*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }sdio_select; - volatile uint32_t enable; /*GPIO0~31 output enable*/ - volatile uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ - volatile uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ + uint32_t enable; /*GPIO0~31 output enable*/ + uint32_t enable_w1ts; /*GPIO0~31 output enable write 1 to set*/ + uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ union { struct { - volatile uint32_t enable_data: 8; /*GPIO32~39 output enable*/ - volatile uint32_t reserved8: 24; + uint32_t enable_data: 8; /*GPIO32~39 output enable*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }enable1; union { struct { - volatile uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to set*/ - volatile uint32_t reserved8: 24; + uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to set*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }enable1_w1ts; union { struct { - volatile uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to clear*/ - volatile uint32_t reserved8: 24; + uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to clear*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }enable1_w1tc; union { struct { - volatile uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/ - volatile uint32_t reserved16:16; + uint32_t strapping: 16; /*GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5}*/ + uint32_t reserved16:16; }; - volatile uint32_t val; + uint32_t val; }strap; - volatile uint32_t in; /*GPIO0~31 input value*/ + uint32_t in; /*GPIO0~31 input value*/ union { struct { - volatile uint32_t in_data: 8; /*GPIO32~39 input value*/ - volatile uint32_t reserved8: 24; + uint32_t in_data: 8; /*GPIO32~39 input value*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }in1; - volatile uint32_t status; /*GPIO0~31 interrupt status*/ - volatile uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ - volatile uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ + uint32_t status; /*GPIO0~31 interrupt status*/ + uint32_t status_w1ts; /*GPIO0~31 interrupt status write 1 to set*/ + uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ union { struct { - volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status*/ - volatile uint32_t reserved8: 24; + uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }status1; union { struct { - volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to set*/ - volatile uint32_t reserved8: 24; + uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to set*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }status1_w1ts; union { struct { - volatile uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to clear*/ - volatile uint32_t reserved8: 24; + uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to clear*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }status1_w1tc; - volatile uint32_t reserved_5c; - volatile uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ - volatile uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ - volatile uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ - volatile uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ - volatile uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ + uint32_t reserved_5c; + uint32_t acpu_int; /*GPIO0~31 APP CPU interrupt status*/ + uint32_t acpu_nmi_int; /*GPIO0~31 APP CPU non-maskable interrupt status*/ + uint32_t pcpu_int; /*GPIO0~31 PRO CPU interrupt status*/ + uint32_t pcpu_nmi_int; /*GPIO0~31 PRO CPU non-maskable interrupt status*/ + uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ union { struct { - volatile uint32_t appcpu_int: 8; /*GPIO32~39 APP CPU interrupt status*/ - volatile uint32_t reserved8: 24; + uint32_t appcpu_int: 8; /*GPIO32~39 APP CPU interrupt status*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }acpu_int1; union { struct { - volatile uint32_t appcpu_nmi_int: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ - volatile uint32_t reserved8: 24; + uint32_t appcpu_nmi_int: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }acpu_nmi_int1; union { struct { - volatile uint32_t procpu_int: 8; /*GPIO32~39 PRO CPU interrupt status*/ - volatile uint32_t reserved8: 24; + uint32_t procpu_int: 8; /*GPIO32~39 PRO CPU interrupt status*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }pcpu_int1; union { struct { - volatile uint32_t procpu_nmi_int: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ - volatile uint32_t reserved8: 24; + uint32_t procpu_nmi_int: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }pcpu_nmi_int1; union { struct { - volatile uint32_t sdio_int: 8; /*SDIO's extent GPIO32~39 interrupt*/ - volatile uint32_t reserved8: 24; + uint32_t sdio_int: 8; /*SDIO's extent GPIO32~39 interrupt*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }cpusdio_int1; union { struct { - volatile uint32_t reserved0: 2; - volatile uint32_t pin_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ - volatile uint32_t reserved3: 4; - volatile uint32_t pin_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ - volatile uint32_t pin_wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ - volatile uint32_t pin_config: 2; /*NA*/ - volatile uint32_t pin_int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ - volatile uint32_t reserved18: 14; + uint32_t reserved0: 2; + uint32_t pin_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t pin_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t pin_wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t pin_config: 2; /*NA*/ + uint32_t pin_int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ + uint32_t reserved18: 14; }; - volatile uint32_t val; + uint32_t val; }pin[40]; union { struct { - volatile uint32_t cali_rtc_max:10; - volatile uint32_t reserved10: 21; - volatile uint32_t cali_start: 1; + uint32_t cali_rtc_max:10; + uint32_t reserved10: 21; + uint32_t cali_start: 1; }; - volatile uint32_t val; + uint32_t val; }cali_conf; union { struct { - volatile uint32_t cali_value_sync2:20; - volatile uint32_t reserved20: 10; - volatile uint32_t cali_rdy_real: 1; - volatile uint32_t cali_rdy_sync2: 1; + uint32_t cali_value_sync2:20; + uint32_t reserved20: 10; + uint32_t cali_rdy_real: 1; + uint32_t cali_rdy_sync2: 1; }; - volatile uint32_t val; + uint32_t val; }cali_data; union { struct { - volatile uint32_t func_in_sel: 6; /*select one of the 256 inputs*/ - volatile uint32_t func_in_inv_sel: 1; /*revert the value of the input if you want to revert please set the value to 1*/ - volatile uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ - volatile uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ + uint32_t func_in_sel: 6; /*select one of the 256 inputs*/ + uint32_t func_in_inv_sel: 1; /*revert the value of the input if you want to revert please set the value to 1*/ + uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ + uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ }; - volatile uint32_t val; + uint32_t val; }func_in_sel_cfg[256]; union { struct { - volatile uint32_t func_out_sel: 9; /*select one of the 256 output to 40 GPIO*/ - volatile uint32_t func_out_inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ - volatile uint32_t func_oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ - volatile uint32_t func_oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ - volatile uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ + uint32_t func_out_sel: 9; /*select one of the 256 output to 40 GPIO*/ + uint32_t func_out_inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ + uint32_t func_oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ + uint32_t func_oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ + uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ }; - volatile uint32_t val; + uint32_t val; }func_out_sel_cfg[40]; } gpio_dev_t; -extern volatile gpio_dev_t GPIO; +extern gpio_dev_t GPIO; #endif /* _SOC_GPIO_STRUCT_H_ */ diff --git a/components/esp32/include/soc/i2c_struct.h b/components/esp32/include/soc/i2c_struct.h index 78f895c02..99c0e9743 100644 --- a/components/esp32/include/soc/i2c_struct.h +++ b/components/esp32/include/soc/i2c_struct.h @@ -13,277 +13,277 @@ // limitations under the License. #ifndef _SOC_I2C_STRUCT_H_ #define _SOC_I2C_STRUCT_H_ -typedef struct { +typedef volatile struct { union { struct { - volatile uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/ - volatile uint32_t reserved14: 18; + uint32_t scl_low_period:14; /*This register is used to configure the low level width of SCL clock.*/ + uint32_t reserved14: 18; }; - volatile uint32_t val; + uint32_t val; }scl_low_period; union { struct { - volatile uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ - volatile uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ - volatile uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ - volatile uint32_t reserved3: 1; - volatile uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ - volatile uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ - volatile uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ - volatile uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ - volatile uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ - volatile uint32_t reserved9: 23; + uint32_t sda_force_out: 1; /*1：normally output sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/ + uint32_t scl_force_out: 1; /*1：normally output scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)*/ + uint32_t sample_scl_level: 1; /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/ + uint32_t reserved3: 1; + uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/ + uint32_t trans_start: 1; /*Set this bit to start sending data in tx_fifo.*/ + uint32_t tx_lsb_first: 1; /*This bit is used to control the sending mode for data need to be send. 1：receive data from most significant bit 0：receive data from least significant bit*/ + uint32_t rx_lsb_first: 1; /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit 0：receive data from least significant bit*/ + uint32_t clk_en: 1; /*This is the clock gating control bit for reading or writing registers.*/ + uint32_t reserved9: 23; }; - volatile uint32_t val; + uint32_t val; }ctr; union { struct { - volatile uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ - volatile uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ - volatile uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ - volatile uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ - volatile uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ - volatile uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ - volatile uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ - volatile uint32_t reserved7: 1; - volatile uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ - volatile uint32_t reserved14: 4; - volatile uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ - volatile uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ - volatile uint32_t reserved27: 1; - volatile uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ - volatile uint32_t reserved31: 1; + uint32_t ack_rec: 1; /*This register stores the value of ACK bit.*/ + uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/ + uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/ + uint32_t arb_lost: 1; /*when I2C lost control of SDA line this register changes to high level.*/ + uint32_t bus_busy: 1; /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/ + uint32_t slave_addressed: 1; /*when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level.*/ + uint32_t byte_trans: 1; /*This register changes to high level when one byte is transferred.*/ + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; /*This register represent the amount of data need to send.*/ + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; /*This register stores the amount of received data in ram.*/ + uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP*/ + uint32_t reserved31: 1; }; - volatile uint32_t val; + uint32_t val; }status_reg; union { struct { - volatile uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/ - volatile uint32_t reserved20:12; + uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/ + uint32_t reserved20:12; }; - volatile uint32_t val; + uint32_t val; }timeout; union { struct { - volatile uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ - volatile uint32_t reserved15: 16; - volatile uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/ + uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ + uint32_t reserved15: 16; + uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/ }; - volatile uint32_t val; + uint32_t val; }slave_addr; union { struct { - volatile uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ - volatile uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ - volatile uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ - volatile uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ - volatile uint32_t reserved20: 12; + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }rx_fifo_st; union { struct { - volatile uint32_t rx_fifo_full_thrhd: 5; - volatile uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ - volatile uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ - volatile uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ - volatile uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ - volatile uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ - volatile uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ - volatile uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ - volatile uint32_t reserved26: 6; + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd:5; /*Config tx_fifo empty threhd value when using apb fifo access*/ + uint32_t nonfifo_en: 1; /*Set this bit to enble apb nonfifo access.*/ + uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/ + uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/ + uint32_t tx_fifo_rst: 1; /*Set this bit to reset tx fifo when using apb fifo access.*/ + uint32_t nonfifo_rx_thres: 6; /*when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/ + uint32_t nonfifo_tx_thres: 6; /*when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/ + uint32_t reserved26: 6; }; - volatile uint32_t val; + uint32_t val; }fifo_conf; union { struct { - volatile uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ - volatile uint32_t reserved8: 24; + uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }fifo_data; union { struct { - volatile uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ - volatile uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ - volatile uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ - volatile uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ - volatile uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ - volatile uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ - volatile uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ - volatile uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ - volatile uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ - volatile uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ - volatile uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ - volatile uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ - volatile uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ - volatile uint32_t reserved13: 19; + uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ + uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ + uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ + uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ + uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ + uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ + uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ + uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ + uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ + uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ + uint32_t reserved13: 19; }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ - volatile uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ - volatile uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ - volatile uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/ - volatile uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ - volatile uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ - volatile uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ - volatile uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ - volatile uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/ - volatile uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/ - volatile uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/ - volatile uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ - volatile uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ - volatile uint32_t reserved13: 19; + uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/ + uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ + uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ + uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/ + uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/ + uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/ + uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; }; - volatile uint32_t val; + uint32_t val; }int_clr; union { struct { - volatile uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ - volatile uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ - volatile uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ - volatile uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/ - volatile uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ - volatile uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/ - volatile uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/ - volatile uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/ - volatile uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/ - volatile uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/ - volatile uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/ - volatile uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/ - volatile uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/ - volatile uint32_t reserved13: 19; + uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/ + uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/ + uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/ + uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/ + uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/ + uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/ + uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ - volatile uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ - volatile uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ - volatile uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/ - volatile uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ - volatile uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ - volatile uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ - volatile uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ - volatile uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/ - volatile uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/ - volatile uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/ - volatile uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ - volatile uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ - volatile uint32_t reserved13: 19; + uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/ + uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ + uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ + uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/ + uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/ + uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/ + uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; }; - volatile uint32_t val; + uint32_t val; }int_status; union { struct { - volatile uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ - volatile uint32_t reserved10: 22; + uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }sda_hold; union { struct { - volatile uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ - volatile uint32_t reserved10: 22; + uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }sda_sample; union { struct { - volatile uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/ - volatile uint32_t reserved14: 18; + uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/ + uint32_t reserved14: 18; }; - volatile uint32_t val; + uint32_t val; }scl_high_period; - volatile uint32_t reserved_3c; + uint32_t reserved_3c; union { struct { - volatile uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ - volatile uint32_t reserved10: 22; + uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }scl_start_hold; union { struct { - volatile uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ - volatile uint32_t reserved10: 22; + uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }scl_rstart_setup; union { struct { - volatile uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ - volatile uint32_t reserved14: 18; + uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ + uint32_t reserved14: 18; }; - volatile uint32_t val; + uint32_t val; }scl_stop_hold; union { struct { - volatile uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ - volatile uint32_t reserved10: 22; + uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }scl_stop_setup; union { struct { - volatile uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ - volatile uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/ - volatile uint32_t reserved4: 28; + uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/ + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }scl_filter_cfg; union { struct { - volatile uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ - volatile uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/ - volatile uint32_t reserved4: 28; + uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/ + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }sda_filter_cfg; union { struct { - volatile uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ - volatile uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - volatile uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - volatile uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - volatile uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ - volatile uint32_t reserved14: 17; - volatile uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ }; - volatile uint32_t val; + uint32_t val; }command[16]; - volatile uint32_t reserved_98; - volatile uint32_t reserved_9c; - volatile uint32_t reserved_a0; - volatile uint32_t reserved_a4; - volatile uint32_t reserved_a8; - volatile uint32_t reserved_ac; - volatile uint32_t reserved_b0; - volatile uint32_t reserved_b4; - volatile uint32_t reserved_b8; - volatile uint32_t reserved_bc; - volatile uint32_t reserved_c0; - volatile uint32_t reserved_c4; - volatile uint32_t reserved_c8; - volatile uint32_t reserved_cc; - volatile uint32_t reserved_d0; - volatile uint32_t reserved_d4; - volatile uint32_t reserved_d8; - volatile uint32_t reserved_dc; - volatile uint32_t reserved_e0; - volatile uint32_t reserved_e4; - volatile uint32_t reserved_e8; - volatile uint32_t reserved_ec; - volatile uint32_t reserved_f0; - volatile uint32_t reserved_f4; - volatile uint32_t date; /**/ - volatile uint32_t reserved_fc; - volatile uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/ + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t date; /**/ + uint32_t reserved_fc; + uint32_t fifo_start_addr; /*This the start address for ram when use apb nonfifo access.*/ } i2c_dev_t; -extern volatile i2c_dev_t I2C0; -extern volatile i2c_dev_t I2C1; +extern i2c_dev_t I2C0; +extern i2c_dev_t I2C1; #endif /* _SOC_I2C_STRUCT_H_ */ diff --git a/components/esp32/include/soc/i2s_struct.h b/components/esp32/include/soc/i2s_struct.h index beea328a3..0bf990cd6 100644 --- a/components/esp32/include/soc/i2s_struct.h +++ b/components/esp32/include/soc/i2s_struct.h @@ -13,449 +13,449 @@ // limitations under the License. #ifndef _SOC_I2S_STRUCT_H_ #define _SOC_I2S_STRUCT_H_ -typedef struct { - volatile uint32_t reserved_0; - volatile uint32_t reserved_4; +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; union { struct { - volatile uint32_t tx_reset: 1; - volatile uint32_t rx_reset: 1; - volatile uint32_t tx_fifo_reset: 1; - volatile uint32_t rx_fifo_reset: 1; - volatile uint32_t tx_start: 1; - volatile uint32_t rx_start: 1; - volatile uint32_t tx_slave_mod: 1; - volatile uint32_t rx_slave_mod: 1; - volatile uint32_t tx_right_first: 1; - volatile uint32_t rx_right_first: 1; - volatile uint32_t tx_msb_shift: 1; - volatile uint32_t rx_msb_shift: 1; - volatile uint32_t tx_short_sync: 1; - volatile uint32_t rx_short_sync: 1; - volatile uint32_t tx_mono: 1; - volatile uint32_t rx_mono: 1; - volatile uint32_t tx_msb_right: 1; - volatile uint32_t rx_msb_right: 1; - volatile uint32_t sig_loopback: 1; - volatile uint32_t reserved19: 13; + uint32_t tx_reset: 1; + uint32_t rx_reset: 1; + uint32_t tx_fifo_reset: 1; + uint32_t rx_fifo_reset: 1; + uint32_t tx_start: 1; + uint32_t rx_start: 1; + uint32_t tx_slave_mod: 1; + uint32_t rx_slave_mod: 1; + uint32_t tx_right_first: 1; + uint32_t rx_right_first: 1; + uint32_t tx_msb_shift: 1; + uint32_t rx_msb_shift: 1; + uint32_t tx_short_sync: 1; + uint32_t rx_short_sync: 1; + uint32_t tx_mono: 1; + uint32_t rx_mono: 1; + uint32_t tx_msb_right: 1; + uint32_t rx_msb_right: 1; + uint32_t sig_loopback: 1; + uint32_t reserved19: 13; }; - volatile uint32_t val; + uint32_t val; }conf; union { struct { - volatile uint32_t rx_take_data_int_raw: 1; - volatile uint32_t tx_put_data_int_raw: 1; - volatile uint32_t rx_wfull_int_raw: 1; - volatile uint32_t rx_rempty_int_raw: 1; - volatile uint32_t tx_wfull_int_raw: 1; - volatile uint32_t tx_rempty_int_raw: 1; - volatile uint32_t rx_hung_int_raw: 1; - volatile uint32_t tx_hung_int_raw: 1; - volatile uint32_t in_done_int_raw: 1; - volatile uint32_t in_suc_eof_int_raw: 1; - volatile uint32_t in_err_eof_int_raw: 1; - volatile uint32_t out_done_int_raw: 1; - volatile uint32_t out_eof_int_raw: 1; - volatile uint32_t in_dscr_err_int_raw: 1; - volatile uint32_t out_dscr_err_int_raw: 1; - volatile uint32_t in_dscr_empty_int_raw: 1; - volatile uint32_t out_total_eof_int_raw: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_take_data_int_raw: 1; + uint32_t tx_put_data_int_raw: 1; + uint32_t rx_wfull_int_raw: 1; + uint32_t rx_rempty_int_raw: 1; + uint32_t tx_wfull_int_raw: 1; + uint32_t tx_rempty_int_raw: 1; + uint32_t rx_hung_int_raw: 1; + uint32_t tx_hung_int_raw: 1; + uint32_t in_done_int_raw: 1; + uint32_t in_suc_eof_int_raw: 1; + uint32_t in_err_eof_int_raw: 1; + uint32_t out_done_int_raw: 1; + uint32_t out_eof_int_raw: 1; + uint32_t in_dscr_err_int_raw: 1; + uint32_t out_dscr_err_int_raw: 1; + uint32_t in_dscr_empty_int_raw: 1; + uint32_t out_total_eof_int_raw: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t rx_take_data_int_st: 1; - volatile uint32_t tx_put_data_int_st: 1; - volatile uint32_t rx_wfull_int_st: 1; - volatile uint32_t rx_rempty_int_st: 1; - volatile uint32_t tx_wfull_int_st: 1; - volatile uint32_t tx_rempty_int_st: 1; - volatile uint32_t rx_hung_int_st: 1; - volatile uint32_t tx_hung_int_st: 1; - volatile uint32_t in_done_int_st: 1; - volatile uint32_t in_suc_eof_int_st: 1; - volatile uint32_t in_err_eof_int_st: 1; - volatile uint32_t out_done_int_st: 1; - volatile uint32_t out_eof_int_st: 1; - volatile uint32_t in_dscr_err_int_st: 1; - volatile uint32_t out_dscr_err_int_st: 1; - volatile uint32_t in_dscr_empty_int_st: 1; - volatile uint32_t out_total_eof_int_st: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_take_data_int_st: 1; + uint32_t tx_put_data_int_st: 1; + uint32_t rx_wfull_int_st: 1; + uint32_t rx_rempty_int_st: 1; + uint32_t tx_wfull_int_st: 1; + uint32_t tx_rempty_int_st: 1; + uint32_t rx_hung_int_st: 1; + uint32_t tx_hung_int_st: 1; + uint32_t in_done_int_st: 1; + uint32_t in_suc_eof_int_st: 1; + uint32_t in_err_eof_int_st: 1; + uint32_t out_done_int_st: 1; + uint32_t out_eof_int_st: 1; + uint32_t in_dscr_err_int_st: 1; + uint32_t out_dscr_err_int_st: 1; + uint32_t in_dscr_empty_int_st: 1; + uint32_t out_total_eof_int_st: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_st; union { struct { - volatile uint32_t rx_take_data_int_ena: 1; - volatile uint32_t tx_put_data_int_ena: 1; - volatile uint32_t rx_wfull_int_ena: 1; - volatile uint32_t rx_rempty_int_ena: 1; - volatile uint32_t tx_wfull_int_ena: 1; - volatile uint32_t tx_rempty_int_ena: 1; - volatile uint32_t rx_hung_int_ena: 1; - volatile uint32_t tx_hung_int_ena: 1; - volatile uint32_t in_done_int_ena: 1; - volatile uint32_t in_suc_eof_int_ena: 1; - volatile uint32_t in_err_eof_int_ena: 1; - volatile uint32_t out_done_int_ena: 1; - volatile uint32_t out_eof_int_ena: 1; - volatile uint32_t in_dscr_err_int_ena: 1; - volatile uint32_t out_dscr_err_int_ena: 1; - volatile uint32_t in_dscr_empty_int_ena: 1; - volatile uint32_t out_total_eof_int_ena: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_take_data_int_ena: 1; + uint32_t tx_put_data_int_ena: 1; + uint32_t rx_wfull_int_ena: 1; + uint32_t rx_rempty_int_ena: 1; + uint32_t tx_wfull_int_ena: 1; + uint32_t tx_rempty_int_ena: 1; + uint32_t rx_hung_int_ena: 1; + uint32_t tx_hung_int_ena: 1; + uint32_t in_done_int_ena: 1; + uint32_t in_suc_eof_int_ena: 1; + uint32_t in_err_eof_int_ena: 1; + uint32_t out_done_int_ena: 1; + uint32_t out_eof_int_ena: 1; + uint32_t in_dscr_err_int_ena: 1; + uint32_t out_dscr_err_int_ena: 1; + uint32_t in_dscr_empty_int_ena: 1; + uint32_t out_total_eof_int_ena: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t take_data_int_clr: 1; - volatile uint32_t put_data_int_clr: 1; - volatile uint32_t rx_wfull_int_clr: 1; - volatile uint32_t rx_rempty_int_clr: 1; - volatile uint32_t tx_wfull_int_clr: 1; - volatile uint32_t tx_rempty_int_clr: 1; - volatile uint32_t rx_hung_int_clr: 1; - volatile uint32_t tx_hung_int_clr: 1; - volatile uint32_t in_done_int_clr: 1; - volatile uint32_t in_suc_eof_int_clr: 1; - volatile uint32_t in_err_eof_int_clr: 1; - volatile uint32_t out_done_int_clr: 1; - volatile uint32_t out_eof_int_clr: 1; - volatile uint32_t in_dscr_err_int_clr: 1; - volatile uint32_t out_dscr_err_int_clr: 1; - volatile uint32_t in_dscr_empty_int_clr: 1; - volatile uint32_t out_total_eof_int_clr: 1; - volatile uint32_t reserved17: 15; + uint32_t take_data_int_clr: 1; + uint32_t put_data_int_clr: 1; + uint32_t rx_wfull_int_clr: 1; + uint32_t rx_rempty_int_clr: 1; + uint32_t tx_wfull_int_clr: 1; + uint32_t tx_rempty_int_clr: 1; + uint32_t rx_hung_int_clr: 1; + uint32_t tx_hung_int_clr: 1; + uint32_t in_done_int_clr: 1; + uint32_t in_suc_eof_int_clr: 1; + uint32_t in_err_eof_int_clr: 1; + uint32_t out_done_int_clr: 1; + uint32_t out_eof_int_clr: 1; + uint32_t in_dscr_err_int_clr: 1; + uint32_t out_dscr_err_int_clr: 1; + uint32_t in_dscr_empty_int_clr: 1; + uint32_t out_total_eof_int_clr: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_clr; union { struct { - volatile uint32_t tx_bck_in_delay: 2; - volatile uint32_t tx_ws_in_delay: 2; - volatile uint32_t rx_bck_in_delay: 2; - volatile uint32_t rx_ws_in_delay: 2; - volatile uint32_t rx_sd_in_delay: 2; - volatile uint32_t tx_bck_out_delay: 2; - volatile uint32_t tx_ws_out_delay: 2; - volatile uint32_t tx_sd_out_delay: 2; - volatile uint32_t rx_ws_out_delay: 2; - volatile uint32_t rx_bck_out_delay: 2; - volatile uint32_t tx_dsync_sw: 1; - volatile uint32_t rx_dsync_sw: 1; - volatile uint32_t data_enable_delay: 2; - volatile uint32_t tx_bck_in_inv: 1; - volatile uint32_t reserved25: 7; + uint32_t tx_bck_in_delay: 2; + uint32_t tx_ws_in_delay: 2; + uint32_t rx_bck_in_delay: 2; + uint32_t rx_ws_in_delay: 2; + uint32_t rx_sd_in_delay: 2; + uint32_t tx_bck_out_delay: 2; + uint32_t tx_ws_out_delay: 2; + uint32_t tx_sd_out_delay: 2; + uint32_t rx_ws_out_delay: 2; + uint32_t rx_bck_out_delay: 2; + uint32_t tx_dsync_sw: 1; + uint32_t rx_dsync_sw: 1; + uint32_t data_enable_delay: 2; + uint32_t tx_bck_in_inv: 1; + uint32_t reserved25: 7; }; - volatile uint32_t val; + uint32_t val; }timing; union { struct { - volatile uint32_t rx_data_num: 6; - volatile uint32_t tx_data_num: 6; - volatile uint32_t dscr_en: 1; - volatile uint32_t tx_fifo_mod: 3; - volatile uint32_t rx_fifo_mod: 3; - volatile uint32_t tx_fifo_mod_force_en: 1; - volatile uint32_t rx_fifo_mod_force_en: 1; - volatile uint32_t reserved21: 11; + uint32_t rx_data_num: 6; + uint32_t tx_data_num: 6; + uint32_t dscr_en: 1; + uint32_t tx_fifo_mod: 3; + uint32_t rx_fifo_mod: 3; + uint32_t tx_fifo_mod_force_en: 1; + uint32_t rx_fifo_mod_force_en: 1; + uint32_t reserved21: 11; }; - volatile uint32_t val; + uint32_t val; }fifo_conf; - volatile uint32_t rx_eof_num; - volatile uint32_t conf_single_data; + uint32_t rx_eof_num; + uint32_t conf_single_data; union { struct { - volatile uint32_t tx_chan_mod: 3; - volatile uint32_t rx_chan_mod: 2; - volatile uint32_t reserved5: 27; + uint32_t tx_chan_mod: 3; + uint32_t rx_chan_mod: 2; + uint32_t reserved5: 27; }; - volatile uint32_t val; + uint32_t val; }conf_chan; union { struct { - volatile uint32_t outlink_addr: 20; - volatile uint32_t reserved20: 8; - volatile uint32_t outlink_stop: 1; - volatile uint32_t outlink_start: 1; - volatile uint32_t outlink_restart: 1; - volatile uint32_t outlink_park: 1; + uint32_t outlink_addr: 20; + uint32_t reserved20: 8; + uint32_t outlink_stop: 1; + uint32_t outlink_start: 1; + uint32_t outlink_restart: 1; + uint32_t outlink_park: 1; }; - volatile uint32_t val; + uint32_t val; }out_link; union { struct { - volatile uint32_t inlink_addr: 20; - volatile uint32_t reserved20: 8; - volatile uint32_t inlink_stop: 1; - volatile uint32_t inlink_start: 1; - volatile uint32_t inlink_restart: 1; - volatile uint32_t inlink_park: 1; + uint32_t inlink_addr: 20; + uint32_t reserved20: 8; + uint32_t inlink_stop: 1; + uint32_t inlink_start: 1; + uint32_t inlink_restart: 1; + uint32_t inlink_park: 1; }; - volatile uint32_t val; + uint32_t val; }in_link; - volatile uint32_t out_eof_des_addr; - volatile uint32_t in_eof_des_addr; - volatile uint32_t out_eof_bfr_des_addr; + uint32_t out_eof_des_addr; + uint32_t in_eof_des_addr; + uint32_t out_eof_bfr_des_addr; union { struct { - volatile uint32_t ahb_testmode: 3; - volatile uint32_t reserved3: 1; - volatile uint32_t ahb_testaddr: 2; - volatile uint32_t reserved6: 26; + uint32_t ahb_testmode: 3; + uint32_t reserved3: 1; + uint32_t ahb_testaddr: 2; + uint32_t reserved6: 26; }; - volatile uint32_t val; + uint32_t val; }ahb_test; - volatile uint32_t in_link_dscr; - volatile uint32_t in_link_dscr_bf0; - volatile uint32_t in_link_dscr_bf1; - volatile uint32_t out_link_dscr; - volatile uint32_t out_link_dscr_bf0; - volatile uint32_t out_link_dscr_bf1; + uint32_t in_link_dscr; + uint32_t in_link_dscr_bf0; + uint32_t in_link_dscr_bf1; + uint32_t out_link_dscr; + uint32_t out_link_dscr_bf0; + uint32_t out_link_dscr_bf1; union { struct { - volatile uint32_t in_rst: 1; - volatile uint32_t out_rst: 1; - volatile uint32_t ahbm_fifo_rst: 1; - volatile uint32_t ahbm_rst: 1; - volatile uint32_t out_loop_test: 1; - volatile uint32_t in_loop_test: 1; - volatile uint32_t out_auto_wrback: 1; - volatile uint32_t out_no_restart_clr: 1; - volatile uint32_t out_eof_mode: 1; - volatile uint32_t outdscr_burst_en: 1; - volatile uint32_t indscr_burst_en: 1; - volatile uint32_t out_data_burst_en: 1; - volatile uint32_t check_owner: 1; - volatile uint32_t mem_trans_en: 1; - volatile uint32_t reserved14: 18; + uint32_t in_rst: 1; + uint32_t out_rst: 1; + uint32_t ahbm_fifo_rst: 1; + uint32_t ahbm_rst: 1; + uint32_t out_loop_test: 1; + uint32_t in_loop_test: 1; + uint32_t out_auto_wrback: 1; + uint32_t out_no_restart_clr: 1; + uint32_t out_eof_mode: 1; + uint32_t outdscr_burst_en: 1; + uint32_t indscr_burst_en: 1; + uint32_t out_data_burst_en: 1; + uint32_t check_owner: 1; + uint32_t mem_trans_en: 1; + uint32_t reserved14: 18; }; - volatile uint32_t val; + uint32_t val; }lc_conf; union { struct { - volatile uint32_t out_fifo_wdata: 9; - volatile uint32_t reserved9: 7; - volatile uint32_t out_fifo_push: 1; - volatile uint32_t reserved17: 15; + uint32_t out_fifo_wdata: 9; + uint32_t reserved9: 7; + uint32_t out_fifo_push: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }out_fifo_push; union { struct { - volatile uint32_t in_fifo_rdata:12; - volatile uint32_t reserved12: 4; - volatile uint32_t in_fifo_pop: 1; - volatile uint32_t reserved17: 15; + uint32_t in_fifo_rdata:12; + uint32_t reserved12: 4; + uint32_t in_fifo_pop: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }in_fifo_pop; - volatile uint32_t lc_state0; - volatile uint32_t lc_state1; + uint32_t lc_state0; + uint32_t lc_state1; union { struct { - volatile uint32_t lc_fifo_timeout: 8; - volatile uint32_t lc_fifo_timeout_shift: 3; - volatile uint32_t lc_fifo_timeout_ena: 1; - volatile uint32_t reserved12: 20; + uint32_t lc_fifo_timeout: 8; + uint32_t lc_fifo_timeout_shift: 3; + uint32_t lc_fifo_timeout_ena: 1; + uint32_t reserved12: 20; }; - volatile uint32_t val; + uint32_t val; }lc_hung_conf; - volatile uint32_t reserved_78; - volatile uint32_t reserved_7c; + uint32_t reserved_78; + uint32_t reserved_7c; union { struct { - volatile uint32_t cvsd_y_max:16; - volatile uint32_t cvsd_y_min:16; + uint32_t cvsd_y_max:16; + uint32_t cvsd_y_min:16; }; - volatile uint32_t val; + uint32_t val; }cvsd_conf0; union { struct { - volatile uint32_t cvsd_sigma_max:16; - volatile uint32_t cvsd_sigma_min:16; + uint32_t cvsd_sigma_max:16; + uint32_t cvsd_sigma_min:16; }; - volatile uint32_t val; + uint32_t val; }cvsd_conf1; union { struct { - volatile uint32_t cvsd_k: 3; - volatile uint32_t cvsd_j: 3; - volatile uint32_t cvsd_beta: 10; - volatile uint32_t cvsd_h: 3; - volatile uint32_t reserved19:13; + uint32_t cvsd_k: 3; + uint32_t cvsd_j: 3; + uint32_t cvsd_beta: 10; + uint32_t cvsd_h: 3; + uint32_t reserved19:13; }; - volatile uint32_t val; + uint32_t val; }cvsd_conf2; union { struct { - volatile uint32_t good_pack_max: 6; - volatile uint32_t n_err_seg: 3; - volatile uint32_t shift_rate: 3; - volatile uint32_t max_slide_sample: 8; - volatile uint32_t pack_len_8k: 5; - volatile uint32_t n_min_err: 3; - volatile uint32_t reserved28: 4; + uint32_t good_pack_max: 6; + uint32_t n_err_seg: 3; + uint32_t shift_rate: 3; + uint32_t max_slide_sample: 8; + uint32_t pack_len_8k: 5; + uint32_t n_min_err: 3; + uint32_t reserved28: 4; }; - volatile uint32_t val; + uint32_t val; }plc_conf0; union { struct { - volatile uint32_t bad_cef_atten_para: 8; - volatile uint32_t bad_cef_atten_para_shift: 4; - volatile uint32_t bad_ola_win2_para_shift: 4; - volatile uint32_t bad_ola_win2_para: 8; - volatile uint32_t slide_win_len: 8; + uint32_t bad_cef_atten_para: 8; + uint32_t bad_cef_atten_para_shift: 4; + uint32_t bad_ola_win2_para_shift: 4; + uint32_t bad_ola_win2_para: 8; + uint32_t slide_win_len: 8; }; - volatile uint32_t val; + uint32_t val; }plc_conf1; union { struct { - volatile uint32_t cvsd_seg_mod: 2; - volatile uint32_t min_period: 5; - volatile uint32_t reserved7: 25; + uint32_t cvsd_seg_mod: 2; + uint32_t min_period: 5; + uint32_t reserved7: 25; }; - volatile uint32_t val; + uint32_t val; }plc_conf2; union { struct { - volatile uint32_t esco_en: 1; - volatile uint32_t esco_chan_mod: 1; - volatile uint32_t esco_cvsd_dec_pack_err: 1; - volatile uint32_t esco_cvsd_pack_len_8k: 5; - volatile uint32_t esco_cvsd_inf_en: 1; - volatile uint32_t cvsd_dec_start: 1; - volatile uint32_t cvsd_dec_reset: 1; - volatile uint32_t plc_en: 1; - volatile uint32_t plc2dma_en: 1; - volatile uint32_t reserved13: 19; + uint32_t esco_en: 1; + uint32_t esco_chan_mod: 1; + uint32_t esco_cvsd_dec_pack_err: 1; + uint32_t esco_cvsd_pack_len_8k: 5; + uint32_t esco_cvsd_inf_en: 1; + uint32_t cvsd_dec_start: 1; + uint32_t cvsd_dec_reset: 1; + uint32_t plc_en: 1; + uint32_t plc2dma_en: 1; + uint32_t reserved13: 19; }; - volatile uint32_t val; + uint32_t val; }esco_conf0; union { struct { - volatile uint32_t sco_with_en: 1; - volatile uint32_t sco_no_en: 1; - volatile uint32_t cvsd_enc_start: 1; - volatile uint32_t cvsd_enc_reset: 1; - volatile uint32_t reserved4: 28; + uint32_t sco_with_en: 1; + uint32_t sco_no_en: 1; + uint32_t cvsd_enc_start: 1; + uint32_t cvsd_enc_reset: 1; + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }sco_conf0; union { struct { - volatile uint32_t tx_pcm_conf: 3; - volatile uint32_t tx_pcm_bypass: 1; - volatile uint32_t rx_pcm_conf: 3; - volatile uint32_t rx_pcm_bypass: 1; - volatile uint32_t tx_stop_en: 1; - volatile uint32_t tx_zeros_rm_en: 1; - volatile uint32_t reserved10: 22; + uint32_t tx_pcm_conf: 3; + uint32_t tx_pcm_bypass: 1; + uint32_t rx_pcm_conf: 3; + uint32_t rx_pcm_bypass: 1; + uint32_t tx_stop_en: 1; + uint32_t tx_zeros_rm_en: 1; + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }conf1; union { struct { - volatile uint32_t fifo_force_pd: 1; - volatile uint32_t fifo_force_pu: 1; - volatile uint32_t plc_mem_force_pd: 1; - volatile uint32_t plc_mem_force_pu: 1; - volatile uint32_t reserved4: 28; + uint32_t fifo_force_pd: 1; + uint32_t fifo_force_pu: 1; + uint32_t plc_mem_force_pd: 1; + uint32_t plc_mem_force_pu: 1; + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }pd_conf; union { struct { - volatile uint32_t camera_en: 1; - volatile uint32_t lcd_tx_wrx2_en: 1; - volatile uint32_t lcd_tx_sdx2_en: 1; - volatile uint32_t data_enable_test_en: 1; - volatile uint32_t data_enable: 1; - volatile uint32_t lcd_en: 1; - volatile uint32_t ext_adc_start_en: 1; - volatile uint32_t inter_valid_en: 1; - volatile uint32_t reserved8: 24; + uint32_t camera_en: 1; + uint32_t lcd_tx_wrx2_en: 1; + uint32_t lcd_tx_sdx2_en: 1; + uint32_t data_enable_test_en: 1; + uint32_t data_enable: 1; + uint32_t lcd_en: 1; + uint32_t ext_adc_start_en: 1; + uint32_t inter_valid_en: 1; + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }conf2; union { struct { - volatile uint32_t clkm_div_num: 8; - volatile uint32_t clkm_div_b: 6; - volatile uint32_t clkm_div_a: 6; - volatile uint32_t clk_en: 1; - volatile uint32_t clka_ena: 1; - volatile uint32_t reserved22: 10; + uint32_t clkm_div_num: 8; + uint32_t clkm_div_b: 6; + uint32_t clkm_div_a: 6; + uint32_t clk_en: 1; + uint32_t clka_ena: 1; + uint32_t reserved22: 10; }; - volatile uint32_t val; + uint32_t val; }clkm_conf; union { struct { - volatile uint32_t tx_bck_div_num: 6; - volatile uint32_t rx_bck_div_num: 6; - volatile uint32_t tx_bits_mod: 6; - volatile uint32_t rx_bits_mod: 6; - volatile uint32_t reserved24: 8; + uint32_t tx_bck_div_num: 6; + uint32_t rx_bck_div_num: 6; + uint32_t tx_bits_mod: 6; + uint32_t rx_bits_mod: 6; + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }sample_rate_conf; union { struct { - volatile uint32_t tx_pdm_en: 1; - volatile uint32_t rx_pdm_en: 1; - volatile uint32_t pcm2pdm_conv_en: 1; - volatile uint32_t pdm2pcm_conv_en: 1; - volatile uint32_t tx_pdm_sinc_osr2: 4; - volatile uint32_t tx_pdm_prescale: 8; - volatile uint32_t tx_pdm_hp_in_shift: 2; - volatile uint32_t tx_pdm_lp_in_shift: 2; - volatile uint32_t tx_pdm_sinc_in_shift: 2; - volatile uint32_t tx_pdm_sigmadelta_in_shift: 2; - volatile uint32_t rx_pdm_sinc_dsr_16_en: 1; - volatile uint32_t tx_pdm_hp_bypass: 1; - volatile uint32_t reserved26: 6; + uint32_t tx_pdm_en: 1; + uint32_t rx_pdm_en: 1; + uint32_t pcm2pdm_conv_en: 1; + uint32_t pdm2pcm_conv_en: 1; + uint32_t tx_pdm_sinc_osr2: 4; + uint32_t tx_pdm_prescale: 8; + uint32_t tx_pdm_hp_in_shift: 2; + uint32_t tx_pdm_lp_in_shift: 2; + uint32_t tx_pdm_sinc_in_shift: 2; + uint32_t tx_pdm_sigmadelta_in_shift: 2; + uint32_t rx_pdm_sinc_dsr_16_en: 1; + uint32_t tx_pdm_hp_bypass: 1; + uint32_t reserved26: 6; }; - volatile uint32_t val; + uint32_t val; }pdm_conf; union { struct { - volatile uint32_t tx_pdm_fs: 10; - volatile uint32_t tx_pdm_fp: 10; - volatile uint32_t reserved20:12; + uint32_t tx_pdm_fs: 10; + uint32_t tx_pdm_fp: 10; + uint32_t reserved20:12; }; - volatile uint32_t val; + uint32_t val; }pdm_freq_conf; union { struct { - volatile uint32_t tx_idle: 1; - volatile uint32_t tx_fifo_reset_back: 1; - volatile uint32_t rx_fifo_reset_back: 1; - volatile uint32_t reserved3: 29; + uint32_t tx_idle: 1; + uint32_t tx_fifo_reset_back: 1; + uint32_t rx_fifo_reset_back: 1; + uint32_t reserved3: 29; }; - volatile uint32_t val; + uint32_t val; }state; - volatile uint32_t reserved_c0; - volatile uint32_t reserved_c4; - volatile uint32_t reserved_c8; - volatile uint32_t reserved_cc; - volatile uint32_t reserved_d0; - volatile uint32_t reserved_d4; - volatile uint32_t reserved_d8; - volatile uint32_t reserved_dc; - volatile uint32_t reserved_e0; - volatile uint32_t reserved_e4; - volatile uint32_t reserved_e8; - volatile uint32_t reserved_ec; - volatile uint32_t reserved_f0; - volatile uint32_t reserved_f4; - volatile uint32_t reserved_f8; - volatile uint32_t date; /**/ + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ } i2s_dev_t; -extern volatile i2s_dev_t I2S0; -extern volatile i2s_dev_t I2S1; +extern i2s_dev_t I2S0; +extern i2s_dev_t I2S1; #endif /* _SOC_I2S_STRUCT_H_ */ diff --git a/components/esp32/include/soc/ledc_struct.h b/components/esp32/include/soc/ledc_struct.h index 302a9e4bc..2eb316b95 100644 --- a/components/esp32/include/soc/ledc_struct.h +++ b/components/esp32/include/soc/ledc_struct.h @@ -13,288 +13,288 @@ // limitations under the License. #ifndef _SOC_LEDC_STRUCT_H_ #define _SOC_LEDC_STRUCT_H_ -typedef struct { +typedef volatile struct { struct{ union { struct { - volatile uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ - volatile uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ - volatile uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ - volatile uint32_t reserved4: 27; - volatile uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ + uint32_t timer_sel: 2; /*There are four high speed timers the two bits are used to select one of them for high speed channel. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/ + uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/ + uint32_t idle_lv: 1; /*This bit is used to control the output value when high speed channel is off.*/ + uint32_t reserved4: 27; + uint32_t clk_en: 1; /*This bit is clock gating control signal. when software configure LED_PWM internal registers it controls the register clock.*/ }; - volatile uint32_t val; + uint32_t val; }conf0; union { struct { - volatile uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ - volatile uint32_t reserved20: 12; + uint32_t hpoint: 20; /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }hpoint; union { struct { - volatile uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ - volatile uint32_t reserved25: 7; + uint32_t duty: 25; /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + uint32_t reserved25: 7; }; - volatile uint32_t val; + uint32_t val; }duty; union { struct { - volatile uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ - volatile uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ - volatile uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ - volatile uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ - volatile uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ + uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for high speed channel.*/ + uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/ + uint32_t duty_num: 10; /*This register is used to control the number of increased or decreased times for high speed channel.*/ + uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/ + uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/ }; - volatile uint32_t val; + uint32_t val; }conf1; union { struct { - volatile uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ - volatile uint32_t reserved25: 7; + uint32_t duty_read: 25; /*This register represents the current duty of the output signal for high speed channel.*/ + uint32_t reserved25: 7; }; - volatile uint32_t val; + uint32_t val; }duty_rd; }high_speed_channel[8]; struct{ union { struct { - volatile uint32_t timer_sel: 2; /*There are four low speed timers the two bits are used to select one of them for low speed channel. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ - volatile uint32_t sig_out_en: 1; /*This is the output enable control bit for low speed channel.*/ - volatile uint32_t idle_lv: 1; /*This bit is used to control the output value when low speed channel is off.*/ - volatile uint32_t para_up: 1; /*This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel.*/ - volatile uint32_t reserved5: 27; + uint32_t timer_sel: 2; /*There are four low speed timers the two bits are used to select one of them for low speed channel. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3.*/ + uint32_t sig_out_en: 1; /*This is the output enable control bit for low speed channel.*/ + uint32_t idle_lv: 1; /*This bit is used to control the output value when low speed channel is off.*/ + uint32_t para_up: 1; /*This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel.*/ + uint32_t reserved5: 27; }; - volatile uint32_t val; + uint32_t val; }conf0; union { struct { - volatile uint32_t hpoint: 20; /*The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel has reached reg_hpoint_lsch0[19:0]*/ - volatile uint32_t reserved20: 12; + uint32_t hpoint: 20; /*The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel has reached reg_hpoint_lsch0[19:0]*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }hpoint; union { struct { - volatile uint32_t duty: 25; /*The register is used to control output duty. When lstimerx(x=[0 3]) choosed by low speed channel has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ - volatile uint32_t reserved25: 7; + uint32_t duty: 25; /*The register is used to control output duty. When lstimerx(x=[0 3]) choosed by low speed channel has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/ + uint32_t reserved25: 7; }; - volatile uint32_t val; + uint32_t val; }duty; union { struct { - volatile uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for low speed channel.*/ - volatile uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel.*/ - volatile uint32_t duty_num: 10; /*This register is used to control the num of increased or decreased times for low speed channel6.*/ - volatile uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6.*/ - volatile uint32_t duty_start: 1; /*When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ + uint32_t duty_scale:10; /*This register controls the increase or decrease step scale for low speed channel.*/ + uint32_t duty_cycle:10; /*This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel.*/ + uint32_t duty_num: 10; /*This register is used to control the num of increased or decreased times for low speed channel6.*/ + uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6.*/ + uint32_t duty_start: 1; /*When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/ }; - volatile uint32_t val; + uint32_t val; }conf1; union { struct { - volatile uint32_t duty_read: 25; /*This register represents the current duty of the output signal for low speed channel.*/ - volatile uint32_t reserved25: 7; + uint32_t duty_read: 25; /*This register represents the current duty of the output signal for low speed channel.*/ + uint32_t reserved25: 7; }; - volatile uint32_t val; + uint32_t val; }duty_r; }low_speed_channel[8]; struct{ union { struct { - volatile uint32_t timer_lim: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ - volatile uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ - volatile uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ - volatile uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ - volatile uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ - volatile uint32_t reserved26: 6; + uint32_t timer_lim: 5; /*This register controls the range of the counter in high speed timer. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/ + uint32_t div_num: 18; /*This register is used to configure parameter for divider in high speed timer the least significant eight bits represent the decimal part.*/ + uint32_t pause: 1; /*This bit is used to pause the counter in high speed timer*/ + uint32_t rst: 1; /*This bit is used to reset high speed timer the counter will be 0 after reset.*/ + uint32_t tick_sel: 1; /*This bit is used to choose apb_clk or ref_tick for high speed timer. 1'b1:apb_clk 0:ref_tick*/ + uint32_t reserved26: 6; }; - volatile uint32_t val; + uint32_t val; }conf; union { struct { - volatile uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ - volatile uint32_t reserved20: 12; + uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in high speed timer*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }value; }high_speed_timer[4]; struct{ union { struct { - volatile uint32_t timer_lim: 5; /*This register controls the range of the counter in low speed timer. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ - volatile uint32_t div_num: 18; /*This register is used to configure parameter for divider in low speed timer the least significant eight bits represent the decimal part.*/ - volatile uint32_t pause: 1; /*This bit is used to pause the counter in low speed timer.*/ - volatile uint32_t rst: 1; /*This bit is used to reset low speed timer the counter will be 0 after reset.*/ - volatile uint32_t tick_sel: 1; /*This bit is used to choose slow_clk or ref_tick for low speed timer. 1'b1:slow_clk 0:ref_tick*/ - volatile uint32_t param_update: 1; /*Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ - volatile uint32_t reserved27: 5; + uint32_t timer_lim: 5; /*This register controls the range of the counter in low speed timer. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/ + uint32_t div_num: 18; /*This register is used to configure parameter for divider in low speed timer the least significant eight bits represent the decimal part.*/ + uint32_t pause: 1; /*This bit is used to pause the counter in low speed timer.*/ + uint32_t rst: 1; /*This bit is used to reset low speed timer the counter will be 0 after reset.*/ + uint32_t tick_sel: 1; /*This bit is used to choose slow_clk or ref_tick for low speed timer. 1'b1:slow_clk 0:ref_tick*/ + uint32_t param_update: 1; /*Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.*/ + uint32_t reserved27: 5; }; - volatile uint32_t val; + uint32_t val; }conf; union { struct { - volatile uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in low speed timer.*/ - volatile uint32_t reserved20: 12; + uint32_t timer_cnt: 20; /*software can read this register to get the current counter value in low speed timer.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }value; }low_speed_timer[4]; union { struct { - volatile uint32_t hstimer0_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ - volatile uint32_t hstimer1_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ - volatile uint32_t hstimer2_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ - volatile uint32_t hstimer3_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ - volatile uint32_t lstimer0_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ - volatile uint32_t lstimer1_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ - volatile uint32_t lstimer2_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ - volatile uint32_t lstimer3_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ - volatile uint32_t duty_chng_end_hsch0_int_raw: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ - volatile uint32_t duty_chng_end_hsch1_int_raw: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ - volatile uint32_t duty_chng_end_hsch2_int_raw: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ - volatile uint32_t duty_chng_end_hsch3_int_raw: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ - volatile uint32_t duty_chng_end_hsch4_int_raw: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ - volatile uint32_t duty_chng_end_hsch5_int_raw: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ - volatile uint32_t duty_chng_end_hsch6_int_raw: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ - volatile uint32_t duty_chng_end_hsch7_int_raw: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ - volatile uint32_t duty_chng_end_lsch0_int_raw: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ - volatile uint32_t duty_chng_end_lsch1_int_raw: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ - volatile uint32_t duty_chng_end_lsch2_int_raw: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ - volatile uint32_t duty_chng_end_lsch3_int_raw: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ - volatile uint32_t duty_chng_end_lsch4_int_raw: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ - volatile uint32_t duty_chng_end_lsch5_int_raw: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ - volatile uint32_t duty_chng_end_lsch6_int_raw: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ - volatile uint32_t duty_chng_end_lsch7_int_raw: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ - volatile uint32_t reserved24: 8; + uint32_t hstimer0_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ + uint32_t hstimer1_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ + uint32_t hstimer2_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ + uint32_t hstimer3_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ + uint32_t lstimer0_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ + uint32_t lstimer1_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ + uint32_t lstimer2_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ + uint32_t lstimer3_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ + uint32_t duty_chng_end_hsch0_int_raw: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ + uint32_t duty_chng_end_hsch1_int_raw: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ + uint32_t duty_chng_end_hsch2_int_raw: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ + uint32_t duty_chng_end_hsch3_int_raw: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ + uint32_t duty_chng_end_hsch4_int_raw: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ + uint32_t duty_chng_end_hsch5_int_raw: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ + uint32_t duty_chng_end_hsch6_int_raw: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ + uint32_t duty_chng_end_hsch7_int_raw: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ + uint32_t duty_chng_end_lsch0_int_raw: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ + uint32_t duty_chng_end_lsch1_int_raw: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ + uint32_t duty_chng_end_lsch2_int_raw: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ + uint32_t duty_chng_end_lsch3_int_raw: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ + uint32_t duty_chng_end_lsch4_int_raw: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ + uint32_t duty_chng_end_lsch5_int_raw: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ + uint32_t duty_chng_end_lsch6_int_raw: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ + uint32_t duty_chng_end_lsch7_int_raw: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t hstimer0_ovf_int_st: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ - volatile uint32_t hstimer1_ovf_int_st: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ - volatile uint32_t hstimer2_ovf_int_st: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ - volatile uint32_t hstimer3_ovf_int_st: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ - volatile uint32_t lstimer0_ovf_int_st: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ - volatile uint32_t lstimer1_ovf_int_st: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ - volatile uint32_t lstimer2_ovf_int_st: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ - volatile uint32_t lstimer3_ovf_int_st: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ - volatile uint32_t duty_chng_end_hsch0_int_st: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch1_int_st: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch2_int_st: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch3_int_st: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch4_int_st: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch5_int_st: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch6_int_st: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ - volatile uint32_t duty_chng_end_hsch7_int_st: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch0_int_st: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch1_int_st: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch2_int_st: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch3_int_st: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch4_int_st: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch5_int_st: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch6_int_st: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ - volatile uint32_t duty_chng_end_lsch7_int_st: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ - volatile uint32_t reserved24: 8; + uint32_t hstimer0_ovf_int_st: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ + uint32_t hstimer1_ovf_int_st: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ + uint32_t hstimer2_ovf_int_st: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ + uint32_t hstimer3_ovf_int_st: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ + uint32_t lstimer0_ovf_int_st: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ + uint32_t lstimer1_ovf_int_st: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ + uint32_t lstimer2_ovf_int_st: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ + uint32_t lstimer3_ovf_int_st: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ + uint32_t duty_chng_end_hsch0_int_st: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_hsch1_int_st: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_hsch2_int_st: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_hsch3_int_st: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_hsch4_int_st: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_hsch5_int_st: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_hsch6_int_st: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_hsch7_int_st: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ + uint32_t duty_chng_end_lsch0_int_st: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_lsch1_int_st: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_lsch2_int_st: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_lsch3_int_st: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_lsch4_int_st: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_lsch5_int_st: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_lsch6_int_st: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_lsch7_int_st: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }int_st; union { struct { - volatile uint32_t hstimer0_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ - volatile uint32_t hstimer1_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ - volatile uint32_t hstimer2_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ - volatile uint32_t hstimer3_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ - volatile uint32_t lstimer0_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ - volatile uint32_t lstimer1_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ - volatile uint32_t lstimer2_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ - volatile uint32_t lstimer3_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ - volatile uint32_t duty_chng_end_hsch0_int_ena: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch1_int_ena: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch2_int_ena: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch3_int_ena: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch4_int_ena: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch5_int_ena: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch6_int_ena: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch7_int_ena: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch0_int_ena: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch1_int_ena: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch2_int_ena: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch3_int_ena: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch4_int_ena: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch5_int_ena: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch6_int_ena: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch7_int_ena: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ - volatile uint32_t reserved24: 8; + uint32_t hstimer0_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0_int_ena: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1_int_ena: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2_int_ena: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3_int_ena: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4_int_ena: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5_int_ena: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6_int_ena: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7_int_ena: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0_int_ena: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1_int_ena: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2_int_ena: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3_int_ena: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4_int_ena: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5_int_ena: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6_int_ena: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7_int_ena: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t hstimer0_ovf_int_clr: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ - volatile uint32_t hstimer1_ovf_int_clr: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ - volatile uint32_t hstimer2_ovf_int_clr: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ - volatile uint32_t hstimer3_ovf_int_clr: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ - volatile uint32_t lstimer0_ovf_int_clr: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ - volatile uint32_t lstimer1_ovf_int_clr: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ - volatile uint32_t lstimer2_ovf_int_clr: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ - volatile uint32_t lstimer3_ovf_int_clr: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ - volatile uint32_t duty_chng_end_hsch0_int_clr: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch1_int_clr: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch2_int_clr: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch3_int_clr: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch4_int_clr: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch5_int_clr: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch6_int_clr: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_hsch7_int_clr: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch0_int_clr: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch1_int_clr: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch2_int_clr: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch3_int_clr: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch4_int_clr: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch5_int_clr: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch6_int_clr: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ - volatile uint32_t duty_chng_end_lsch7_int_clr: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ - volatile uint32_t reserved24: 8; + uint32_t hstimer0_ovf_int_clr: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf_int_clr: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf_int_clr: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf_int_clr: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf_int_clr: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf_int_clr: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf_int_clr: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf_int_clr: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0_int_clr: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1_int_clr: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2_int_clr: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3_int_clr: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4_int_clr: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5_int_clr: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6_int_clr: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7_int_clr: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0_int_clr: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1_int_clr: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2_int_clr: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3_int_clr: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4_int_clr: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5_int_clr: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6_int_clr: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7_int_clr: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }int_clr; union { struct { - volatile uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ - volatile uint32_t reserved1: 31; + uint32_t apb_clk_sel: 1; /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz*/ + uint32_t reserved1: 31; }; - volatile uint32_t val; + uint32_t val; }conf; - volatile uint32_t reserved_194; - volatile uint32_t reserved_198; - volatile uint32_t reserved_19c; - volatile uint32_t reserved_1a0; - volatile uint32_t reserved_1a4; - volatile uint32_t reserved_1a8; - volatile uint32_t reserved_1ac; - volatile uint32_t reserved_1b0; - volatile uint32_t reserved_1b4; - volatile uint32_t reserved_1b8; - volatile uint32_t reserved_1bc; - volatile uint32_t reserved_1c0; - volatile uint32_t reserved_1c4; - volatile uint32_t reserved_1c8; - volatile uint32_t reserved_1cc; - volatile uint32_t reserved_1d0; - volatile uint32_t reserved_1d4; - volatile uint32_t reserved_1d8; - volatile uint32_t reserved_1dc; - volatile uint32_t reserved_1e0; - volatile uint32_t reserved_1e4; - volatile uint32_t reserved_1e8; - volatile uint32_t reserved_1ec; - volatile uint32_t reserved_1f0; - volatile uint32_t reserved_1f4; - volatile uint32_t reserved_1f8; - volatile uint32_t date; /*This register represents the version .*/ + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t date; /*This register represents the version .*/ } ledc_dev_t; -extern volatile ledc_dev_t LEDC; +extern ledc_dev_t LEDC; #endif /* _SOC_LEDC_STRUCT_H_ */ diff --git a/components/esp32/include/soc/pcnt_struct.h b/components/esp32/include/soc/pcnt_struct.h index bf9679399..1505cc692 100644 --- a/components/esp32/include/soc/pcnt_struct.h +++ b/components/esp32/include/soc/pcnt_struct.h @@ -13,149 +13,149 @@ // limitations under the License. #ifndef _SOC_PCNT_STRUCT_H_ #define _SOC_PCNT_STRUCT_H_ -typedef struct { +typedef volatile struct { struct{ union { struct { - volatile uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ - volatile uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ - volatile uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ - volatile uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ - volatile uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ - volatile uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ - volatile uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ - volatile uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ - volatile uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ - volatile uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ - volatile uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ - volatile uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ - volatile uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ - volatile uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ - volatile uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ + uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ + uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ + uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ + uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ + uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ + uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ + uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ + uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ + uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ + uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ }; - volatile uint32_t val; + uint32_t val; }conf0; union { struct { - volatile uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ - volatile uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ + uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ + uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ }; - volatile uint32_t val; + uint32_t val; }conf1; union { struct { - volatile uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ - volatile uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ + uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ + uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ }; - volatile uint32_t val; + uint32_t val; }conf2; }conf_unit[8]; union { struct { - volatile uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ - volatile uint32_t reserved16: 16; + uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ + uint32_t reserved16: 16; }; - volatile uint32_t val; + uint32_t val; }cnt_unit[8]; union { struct { - volatile uint32_t cnt_thr_event_u0_int_raw: 1; /*This is the interrupt raw bit for channel0 event.*/ - volatile uint32_t cnt_thr_event_u1_int_raw: 1; /*This is the interrupt raw bit for channel1 event.*/ - volatile uint32_t cnt_thr_event_u2_int_raw: 1; /*This is the interrupt raw bit for channel2 event.*/ - volatile uint32_t cnt_thr_event_u3_int_raw: 1; /*This is the interrupt raw bit for channel3 event.*/ - volatile uint32_t cnt_thr_event_u4_int_raw: 1; /*This is the interrupt raw bit for channel4 event.*/ - volatile uint32_t cnt_thr_event_u5_int_raw: 1; /*This is the interrupt raw bit for channel5 event.*/ - volatile uint32_t cnt_thr_event_u6_int_raw: 1; /*This is the interrupt raw bit for channel6 event.*/ - volatile uint32_t cnt_thr_event_u7_int_raw: 1; /*This is the interrupt raw bit for channel7 event.*/ - volatile uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0_int_raw: 1; /*This is the interrupt raw bit for channel0 event.*/ + uint32_t cnt_thr_event_u1_int_raw: 1; /*This is the interrupt raw bit for channel1 event.*/ + uint32_t cnt_thr_event_u2_int_raw: 1; /*This is the interrupt raw bit for channel2 event.*/ + uint32_t cnt_thr_event_u3_int_raw: 1; /*This is the interrupt raw bit for channel3 event.*/ + uint32_t cnt_thr_event_u4_int_raw: 1; /*This is the interrupt raw bit for channel4 event.*/ + uint32_t cnt_thr_event_u5_int_raw: 1; /*This is the interrupt raw bit for channel5 event.*/ + uint32_t cnt_thr_event_u6_int_raw: 1; /*This is the interrupt raw bit for channel6 event.*/ + uint32_t cnt_thr_event_u7_int_raw: 1; /*This is the interrupt raw bit for channel7 event.*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t cnt_thr_event_u0_int_st: 1; /*This is the interrupt status bit for channel0 event.*/ - volatile uint32_t cnt_thr_event_u1_int_st: 1; /*This is the interrupt status bit for channel1 event.*/ - volatile uint32_t cnt_thr_event_u2_int_st: 1; /*This is the interrupt status bit for channel2 event.*/ - volatile uint32_t cnt_thr_event_u3_int_st: 1; /*This is the interrupt status bit for channel3 event.*/ - volatile uint32_t cnt_thr_event_u4_int_st: 1; /*This is the interrupt status bit for channel4 event.*/ - volatile uint32_t cnt_thr_event_u5_int_st: 1; /*This is the interrupt status bit for channel5 event.*/ - volatile uint32_t cnt_thr_event_u6_int_st: 1; /*This is the interrupt status bit for channel6 event.*/ - volatile uint32_t cnt_thr_event_u7_int_st: 1; /*This is the interrupt status bit for channel7 event.*/ - volatile uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0_int_st: 1; /*This is the interrupt status bit for channel0 event.*/ + uint32_t cnt_thr_event_u1_int_st: 1; /*This is the interrupt status bit for channel1 event.*/ + uint32_t cnt_thr_event_u2_int_st: 1; /*This is the interrupt status bit for channel2 event.*/ + uint32_t cnt_thr_event_u3_int_st: 1; /*This is the interrupt status bit for channel3 event.*/ + uint32_t cnt_thr_event_u4_int_st: 1; /*This is the interrupt status bit for channel4 event.*/ + uint32_t cnt_thr_event_u5_int_st: 1; /*This is the interrupt status bit for channel5 event.*/ + uint32_t cnt_thr_event_u6_int_st: 1; /*This is the interrupt status bit for channel6 event.*/ + uint32_t cnt_thr_event_u7_int_st: 1; /*This is the interrupt status bit for channel7 event.*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }int_st; union { struct { - volatile uint32_t cnt_thr_event_u0_int_ena: 1; /*This is the interrupt enable bit for channel0 event.*/ - volatile uint32_t cnt_thr_event_u1_int_ena: 1; /*This is the interrupt enable bit for channel1 event.*/ - volatile uint32_t cnt_thr_event_u2_int_ena: 1; /*This is the interrupt enable bit for channel2 event.*/ - volatile uint32_t cnt_thr_event_u3_int_ena: 1; /*This is the interrupt enable bit for channel3 event.*/ - volatile uint32_t cnt_thr_event_u4_int_ena: 1; /*This is the interrupt enable bit for channel4 event.*/ - volatile uint32_t cnt_thr_event_u5_int_ena: 1; /*This is the interrupt enable bit for channel5 event.*/ - volatile uint32_t cnt_thr_event_u6_int_ena: 1; /*This is the interrupt enable bit for channel6 event.*/ - volatile uint32_t cnt_thr_event_u7_int_ena: 1; /*This is the interrupt enable bit for channel7 event.*/ - volatile uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0_int_ena: 1; /*This is the interrupt enable bit for channel0 event.*/ + uint32_t cnt_thr_event_u1_int_ena: 1; /*This is the interrupt enable bit for channel1 event.*/ + uint32_t cnt_thr_event_u2_int_ena: 1; /*This is the interrupt enable bit for channel2 event.*/ + uint32_t cnt_thr_event_u3_int_ena: 1; /*This is the interrupt enable bit for channel3 event.*/ + uint32_t cnt_thr_event_u4_int_ena: 1; /*This is the interrupt enable bit for channel4 event.*/ + uint32_t cnt_thr_event_u5_int_ena: 1; /*This is the interrupt enable bit for channel5 event.*/ + uint32_t cnt_thr_event_u6_int_ena: 1; /*This is the interrupt enable bit for channel6 event.*/ + uint32_t cnt_thr_event_u7_int_ena: 1; /*This is the interrupt enable bit for channel7 event.*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t cnt_thr_event_u0_int_clr: 1; /*Set this bit to clear channel0 event interrupt.*/ - volatile uint32_t cnt_thr_event_u1_int_clr: 1; /*Set this bit to clear channel1 event interrupt.*/ - volatile uint32_t cnt_thr_event_u2_int_clr: 1; /*Set this bit to clear channel2 event interrupt.*/ - volatile uint32_t cnt_thr_event_u3_int_clr: 1; /*Set this bit to clear channel3 event interrupt.*/ - volatile uint32_t cnt_thr_event_u4_int_clr: 1; /*Set this bit to clear channel4 event interrupt.*/ - volatile uint32_t cnt_thr_event_u5_int_clr: 1; /*Set this bit to clear channel5 event interrupt.*/ - volatile uint32_t cnt_thr_event_u6_int_clr: 1; /*Set this bit to clear channel6 event interrupt.*/ - volatile uint32_t cnt_thr_event_u7_int_clr: 1; /*Set this bit to clear channel7 event interrupt.*/ - volatile uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0_int_clr: 1; /*Set this bit to clear channel0 event interrupt.*/ + uint32_t cnt_thr_event_u1_int_clr: 1; /*Set this bit to clear channel1 event interrupt.*/ + uint32_t cnt_thr_event_u2_int_clr: 1; /*Set this bit to clear channel2 event interrupt.*/ + uint32_t cnt_thr_event_u3_int_clr: 1; /*Set this bit to clear channel3 event interrupt.*/ + uint32_t cnt_thr_event_u4_int_clr: 1; /*Set this bit to clear channel4 event interrupt.*/ + uint32_t cnt_thr_event_u5_int_clr: 1; /*Set this bit to clear channel5 event interrupt.*/ + uint32_t cnt_thr_event_u6_int_clr: 1; /*Set this bit to clear channel6 event interrupt.*/ + uint32_t cnt_thr_event_u7_int_clr: 1; /*Set this bit to clear channel7 event interrupt.*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }int_clr; - volatile uint32_t status_unit[8]; + uint32_t status_unit[8]; union { struct { - volatile uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ - volatile uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ - volatile uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ - volatile uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ - volatile uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ - volatile uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ - volatile uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ - volatile uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ - volatile uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ - volatile uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ - volatile uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ - volatile uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ - volatile uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ - volatile uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ - volatile uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ - volatile uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ - volatile uint32_t clk_en: 1; - volatile uint32_t reserved17: 15; + uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ + uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ + uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ + uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ + uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ + uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ + uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ + uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ + uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ + uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ + uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ + uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ + uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ + uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ + uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ + uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ + uint32_t clk_en: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }ctrl; - volatile uint32_t reserved_b4; - volatile uint32_t reserved_b8; - volatile uint32_t reserved_bc; - volatile uint32_t reserved_c0; - volatile uint32_t reserved_c4; - volatile uint32_t reserved_c8; - volatile uint32_t reserved_cc; - volatile uint32_t reserved_d0; - volatile uint32_t reserved_d4; - volatile uint32_t reserved_d8; - volatile uint32_t reserved_dc; - volatile uint32_t reserved_e0; - volatile uint32_t reserved_e4; - volatile uint32_t reserved_e8; - volatile uint32_t reserved_ec; - volatile uint32_t reserved_f0; - volatile uint32_t reserved_f4; - volatile uint32_t reserved_f8; - volatile uint32_t date; /**/ + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ } pcnt_dev_t; -extern volatile pcnt_dev_t PCNT; +extern pcnt_dev_t PCNT; #endif /* _SOC_PCNT_STRUCT_H_ */ diff --git a/components/esp32/include/soc/rmt_struct.h b/components/esp32/include/soc/rmt_struct.h index 7310e18d5..dc3148eaa 100644 --- a/components/esp32/include/soc/rmt_struct.h +++ b/components/esp32/include/soc/rmt_struct.h @@ -13,216 +13,216 @@ // limitations under the License. #ifndef _SOC_RMT_STRUCT_H_ #define _SOC_RMT_STRUCT_H_ -typedef struct { - volatile uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/ +typedef volatile struct { + uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/ struct{ union { struct { - volatile uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ - volatile uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/ - volatile uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/ - volatile uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/ - volatile uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ - volatile uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/ - volatile uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/ + uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/ + uint32_t idle_thres: 16; /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/ + uint32_t mem_size: 4; /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/ + uint32_t carrier_en: 1; /*This is the carrier modulation enable control bit for channel0-7.*/ + uint32_t carrier_out_lv: 1; /*This bit is used to configure the way carrier wave is modulated for channel0-7.1'b1:transmit on low output level 1'b0:transmit on high output level.*/ + uint32_t mem_pd: 1; /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/ + uint32_t clk_en: 1; /*This bit is used to control clock.when software configure RMT internal registers it controls the register clock.*/ }; - volatile uint32_t val; + uint32_t val; }conf0; union { struct { - volatile uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/ - volatile uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/ - volatile uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/ - volatile uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/ - volatile uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/ - volatile uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/ - volatile uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/ - volatile uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/ - volatile uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/ - volatile uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ - volatile uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ - volatile uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/ - volatile uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/ - volatile uint32_t reserved20: 12; + uint32_t tx_start: 1; /*Set this bit to start sending data for channel0-7.*/ + uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/ + uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/ + uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/ + uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/ + uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram*/ + uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/ + uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/ + uint32_t rx_filter_thres: 8; /*in receive mode channel0-7 ignore input pulse when the pulse width is smaller then this value.*/ + uint32_t ref_cnt_rst: 1; /*This bit is used to reset divider in channel0-7.*/ + uint32_t ref_always_on: 1; /*This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref*/ + uint32_t idle_out_lv: 1; /*This bit configures the output signal's level for channel0-7 in IDLE state.*/ + uint32_t idle_out_en: 1; /*This is the output enable control bit for channel0-7 in IDLE state.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }conf1; }conf_ch[8]; - volatile uint32_t status_ch[8]; /*The status for channel0-7*/ - volatile uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/ + uint32_t status_ch[8]; /*The status for channel0-7*/ + uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/ union { struct { - volatile uint32_t ch0_tx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ - volatile uint32_t ch0_rx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ - volatile uint32_t ch0_err_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ - volatile uint32_t ch1_tx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ - volatile uint32_t ch1_rx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ - volatile uint32_t ch1_err_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ - volatile uint32_t ch2_tx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ - volatile uint32_t ch2_rx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ - volatile uint32_t ch2_err_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ - volatile uint32_t ch3_tx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ - volatile uint32_t ch3_rx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ - volatile uint32_t ch3_err_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ - volatile uint32_t ch4_tx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ - volatile uint32_t ch4_rx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ - volatile uint32_t ch4_err_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ - volatile uint32_t ch5_tx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ - volatile uint32_t ch5_rx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ - volatile uint32_t ch5_err_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ - volatile uint32_t ch6_tx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ - volatile uint32_t ch6_rx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ - volatile uint32_t ch6_err_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ - volatile uint32_t ch7_tx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ - volatile uint32_t ch7_rx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ - volatile uint32_t ch7_err_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ - volatile uint32_t ch0_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch1_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch2_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch3_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch4_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch5_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch6_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ - volatile uint32_t ch7_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch0_tx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ + uint32_t ch0_rx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ + uint32_t ch0_err_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ + uint32_t ch1_tx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ + uint32_t ch1_rx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ + uint32_t ch1_err_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ + uint32_t ch2_tx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ + uint32_t ch2_rx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ + uint32_t ch2_err_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ + uint32_t ch3_tx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ + uint32_t ch3_rx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ + uint32_t ch3_err_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ + uint32_t ch4_tx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ + uint32_t ch4_rx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ + uint32_t ch4_err_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ + uint32_t ch5_tx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ + uint32_t ch5_rx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ + uint32_t ch5_err_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ + uint32_t ch6_tx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ + uint32_t ch6_rx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ + uint32_t ch6_err_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ + uint32_t ch7_tx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ + uint32_t ch7_rx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ + uint32_t ch7_err_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ + uint32_t ch0_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch1_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch2_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch3_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch4_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch5_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch6_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch7_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t ch0_tx_end_int_st: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ - volatile uint32_t ch0_rx_end_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ - volatile uint32_t ch0_err_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ - volatile uint32_t ch1_tx_end_int_st: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch1_rx_end_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch1_err_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ - volatile uint32_t ch2_tx_end_int_st: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch2_rx_end_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch2_err_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ - volatile uint32_t ch3_tx_end_int_st: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch3_rx_end_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch3_err_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ - volatile uint32_t ch4_tx_end_int_st: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch4_rx_end_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch4_err_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ - volatile uint32_t ch5_tx_end_int_st: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch5_rx_end_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch5_err_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ - volatile uint32_t ch6_tx_end_int_st: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch6_rx_end_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch6_err_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ - volatile uint32_t ch7_tx_end_int_st: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ - volatile uint32_t ch7_rx_end_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ - volatile uint32_t ch7_err_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ - volatile uint32_t ch0_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch1_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch2_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch3_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch4_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch5_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch6_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ - volatile uint32_t ch7_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch0_tx_end_int_st: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ + uint32_t ch0_rx_end_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ + uint32_t ch0_err_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ + uint32_t ch1_tx_end_int_st: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ + uint32_t ch1_rx_end_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ + uint32_t ch1_err_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ + uint32_t ch2_tx_end_int_st: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ + uint32_t ch2_rx_end_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ + uint32_t ch2_err_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ + uint32_t ch3_tx_end_int_st: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ + uint32_t ch3_rx_end_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ + uint32_t ch3_err_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ + uint32_t ch4_tx_end_int_st: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ + uint32_t ch4_rx_end_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ + uint32_t ch4_err_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ + uint32_t ch5_tx_end_int_st: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ + uint32_t ch5_rx_end_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ + uint32_t ch5_err_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ + uint32_t ch6_tx_end_int_st: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ + uint32_t ch6_rx_end_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ + uint32_t ch6_err_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ + uint32_t ch7_tx_end_int_st: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ + uint32_t ch7_rx_end_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ + uint32_t ch7_err_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ + uint32_t ch0_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch1_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch2_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch3_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch4_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch5_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch6_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch7_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ }; - volatile uint32_t val; + uint32_t val; }int_st; union { struct { - volatile uint32_t ch0_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ - volatile uint32_t ch0_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ - volatile uint32_t ch0_err_int_ena: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ - volatile uint32_t ch1_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ - volatile uint32_t ch1_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ - volatile uint32_t ch1_err_int_ena: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ - volatile uint32_t ch2_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ - volatile uint32_t ch2_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ - volatile uint32_t ch2_err_int_ena: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ - volatile uint32_t ch3_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ - volatile uint32_t ch3_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ - volatile uint32_t ch3_err_int_ena: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ - volatile uint32_t ch4_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ - volatile uint32_t ch4_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ - volatile uint32_t ch4_err_int_ena: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ - volatile uint32_t ch5_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ - volatile uint32_t ch5_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ - volatile uint32_t ch5_err_int_ena: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ - volatile uint32_t ch6_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ - volatile uint32_t ch6_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ - volatile uint32_t ch6_err_int_ena: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ - volatile uint32_t ch7_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ - volatile uint32_t ch7_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ - volatile uint32_t ch7_err_int_ena: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ - volatile uint32_t ch0_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ - volatile uint32_t ch1_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ - volatile uint32_t ch2_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ - volatile uint32_t ch3_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ - volatile uint32_t ch4_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ - volatile uint32_t ch5_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ - volatile uint32_t ch6_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ - volatile uint32_t ch7_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ + uint32_t ch0_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ + uint32_t ch0_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ + uint32_t ch0_err_int_ena: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ + uint32_t ch1_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ + uint32_t ch1_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ + uint32_t ch1_err_int_ena: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ + uint32_t ch2_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ + uint32_t ch2_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ + uint32_t ch2_err_int_ena: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ + uint32_t ch3_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ + uint32_t ch3_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ + uint32_t ch3_err_int_ena: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ + uint32_t ch4_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ + uint32_t ch4_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ + uint32_t ch4_err_int_ena: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ + uint32_t ch5_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ + uint32_t ch5_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ + uint32_t ch5_err_int_ena: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ + uint32_t ch6_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ + uint32_t ch6_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ + uint32_t ch6_err_int_ena: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ + uint32_t ch7_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ + uint32_t ch7_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ + uint32_t ch7_err_int_ena: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ + uint32_t ch0_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ + uint32_t ch1_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ + uint32_t ch2_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ + uint32_t ch3_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ + uint32_t ch4_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ + uint32_t ch5_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ + uint32_t ch6_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ + uint32_t ch7_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t ch0_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ - volatile uint32_t ch0_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ - volatile uint32_t ch0_err_int_clr: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ - volatile uint32_t ch1_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ - volatile uint32_t ch1_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ - volatile uint32_t ch1_err_int_clr: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ - volatile uint32_t ch2_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ - volatile uint32_t ch2_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ - volatile uint32_t ch2_err_int_clr: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ - volatile uint32_t ch3_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ - volatile uint32_t ch3_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ - volatile uint32_t ch3_err_int_clr: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ - volatile uint32_t ch4_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ - volatile uint32_t ch4_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ - volatile uint32_t ch4_err_int_clr: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ - volatile uint32_t ch5_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ - volatile uint32_t ch5_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ - volatile uint32_t ch5_err_int_clr: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ - volatile uint32_t ch6_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ - volatile uint32_t ch6_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ - volatile uint32_t ch6_err_int_clr: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ - volatile uint32_t ch7_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ - volatile uint32_t ch7_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ - volatile uint32_t ch7_err_int_clr: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ - volatile uint32_t ch0_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch1_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch2_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch3_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch4_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch5_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch6_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ - volatile uint32_t ch7_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ + uint32_t ch0_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ + uint32_t ch0_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ + uint32_t ch0_err_int_clr: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ + uint32_t ch1_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ + uint32_t ch1_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ + uint32_t ch1_err_int_clr: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ + uint32_t ch2_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ + uint32_t ch2_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ + uint32_t ch2_err_int_clr: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ + uint32_t ch3_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ + uint32_t ch3_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ + uint32_t ch3_err_int_clr: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ + uint32_t ch4_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ + uint32_t ch4_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ + uint32_t ch4_err_int_clr: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ + uint32_t ch5_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ + uint32_t ch5_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ + uint32_t ch5_err_int_clr: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ + uint32_t ch6_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ + uint32_t ch6_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ + uint32_t ch6_err_int_clr: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ + uint32_t ch7_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ + uint32_t ch7_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ + uint32_t ch7_err_int_clr: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ + uint32_t ch0_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ + uint32_t ch1_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ + uint32_t ch2_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ + uint32_t ch3_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ + uint32_t ch4_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ + uint32_t ch5_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ + uint32_t ch6_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ + uint32_t ch7_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ }; - volatile uint32_t val; + uint32_t val; }int_clr; union { struct { - volatile uint32_t carrier_low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ - volatile uint32_t carrier_high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + uint32_t carrier_low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ + uint32_t carrier_high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ }; - volatile uint32_t val; + uint32_t val; }carrier_duty_ch[8]; union { struct { - volatile uint32_t tx_lim: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ - volatile uint32_t reserved9: 23; + uint32_t tx_lim: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ + uint32_t reserved9: 23; }; - volatile uint32_t val; + uint32_t val; }tx_lim_ch[8]; union { struct { - volatile uint32_t apb_fifo_mask: 1; /*Set this bit to disable apb fifo access*/ - volatile uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ - volatile uint32_t reserved2: 30; + uint32_t apb_fifo_mask: 1; /*Set this bit to disable apb fifo access*/ + uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ + uint32_t reserved2: 30; }; - volatile uint32_t val; + uint32_t val; }apb_conf; - volatile uint32_t reserved_f4; - volatile uint32_t reserved_f8; - volatile uint32_t date; /*This is the version register.*/ + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /*This is the version register.*/ } rmt_dev_t; -extern volatile rmt_dev_t RMT; +extern rmt_dev_t RMT; #endif /* _SOC_RMT_STRUCT_H_ */ diff --git a/components/esp32/include/soc/spi_struct.h b/components/esp32/include/soc/spi_struct.h index e76590537..0eb64e91d 100644 --- a/components/esp32/include/soc/spi_struct.h +++ b/components/esp32/include/soc/spi_struct.h @@ -13,665 +13,665 @@ // limitations under the License. #ifndef _SOC_SPI_STRUCT_H_ #define _SOC_SPI_STRUCT_H_ -typedef struct { +typedef volatile struct { union { struct { - volatile uint32_t reserved0: 16; /*reserved*/ - volatile uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ - volatile uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ - volatile uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ - volatile uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ - volatile uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ - volatile uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t reserved0: 16; /*reserved*/ + uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ + uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ + uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ + uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ }; - volatile uint32_t val; + uint32_t val; }cmd; union { struct { - volatile uint32_t reserved : 8; - volatile uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/ + uint32_t reserved : 8; + uint32_t usr_addr_value:24; /*[31:8]:address to slave [7:0]:Reserved.*/ }; - volatile uint32_t val; + uint32_t val; }addr; union { struct { - volatile uint32_t reserved0: 10; /*reserved*/ - volatile uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ - volatile uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ - volatile uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ - volatile uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ - volatile uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ - volatile uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ - volatile uint32_t reserved16: 4; /*reserved*/ - volatile uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ - volatile uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ - volatile uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ - volatile uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ - volatile uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ - volatile uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ - volatile uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ - volatile uint32_t reserved27: 5; /*reserved*/ + uint32_t reserved0: 10; /*reserved*/ + uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ + uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ + uint32_t reserved16: 4; /*reserved*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ + uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ + uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ + uint32_t reserved27: 5; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }ctrl; union { struct { - volatile uint32_t reserved0: 16; /*reserved*/ - volatile uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ - volatile uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ + uint32_t reserved0: 16; /*reserved*/ + uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ + uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ }; - volatile uint32_t val; + uint32_t val; }ctrl1; union { struct { - volatile uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ - volatile uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ - volatile uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ + uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ + uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ + uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ }; - volatile uint32_t val; + uint32_t val; }rd_status; union { struct { - volatile uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ - volatile uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ - volatile uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ - volatile uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ - volatile uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ - volatile uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ - volatile uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ - volatile uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ - volatile uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ - volatile uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ + uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ + uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ + uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ + uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ + uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ + uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ + uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ + uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ }; - volatile uint32_t val; + uint32_t val; }ctrl2; union { struct { - volatile uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ - volatile uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ - volatile uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ - volatile uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ - volatile uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ + uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ + uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ + uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ + uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ + uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ }; - volatile uint32_t val; + uint32_t val; }clock; union { struct { - volatile uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ - volatile uint32_t reserved1: 3; /*reserved*/ - volatile uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ - volatile uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ - volatile uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ - volatile uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ - volatile uint32_t reserved8: 2; /*reserved*/ - volatile uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ - volatile uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ - volatile uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ - volatile uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ - volatile uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ - volatile uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ - volatile uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ - volatile uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ - volatile uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ - volatile uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ - volatile uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ - volatile uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ - volatile uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ - volatile uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ - volatile uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ - volatile uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ - volatile uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ - volatile uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ - volatile uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ - volatile uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ - volatile uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ - volatile uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ + uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ + uint32_t reserved1: 3; /*reserved*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ + uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ + uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ + uint32_t reserved8: 2; /*reserved*/ + uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ + uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ + uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ + uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ + uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ + uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ + uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ + uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ + uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ + uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ + uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ + uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ + uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ + uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ }; - volatile uint32_t val; + uint32_t val; }user; union { struct { - volatile uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ - volatile uint32_t reserved8: 18; /*reserved*/ - volatile uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t reserved8: 18; /*reserved*/ + uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ }; - volatile uint32_t val; + uint32_t val; }user1; union { struct { - volatile uint32_t usr_command_value: 16; /*The value of command.*/ - volatile uint32_t reserved16: 12; /*reserved*/ - volatile uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + uint32_t usr_command_value: 16; /*The value of command.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ }; - volatile uint32_t val; + uint32_t val; }user2; union { struct { - volatile uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ - volatile uint32_t reserved24: 8; /*reserved*/ + uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }mosi_dlen; union { struct { - volatile uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ - volatile uint32_t reserved24: 8; /*reserved*/ + uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }miso_dlen; - volatile uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ + uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ union { struct { - volatile uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ - volatile uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ - volatile uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ - volatile uint32_t reserved3: 2; /*reserved*/ - volatile uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ - volatile uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ - volatile uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ - volatile uint32_t reserved16: 13; /*reserved*/ - volatile uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ - volatile uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ - volatile uint32_t reserved31: 1; /*reserved*/ + uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ + uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ + uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ + uint32_t reserved3: 2; /*reserved*/ + uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ + uint32_t master_cs_pol: 5; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ + uint32_t master_ck_sel: 5; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ + uint32_t reserved16: 13; /*reserved*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + uint32_t reserved31: 1; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }pin; union { struct { - volatile uint32_t slv_rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ - volatile uint32_t slv_wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ - volatile uint32_t slv_rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ - volatile uint32_t slv_wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ - volatile uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ - volatile uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ - volatile uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ - volatile uint32_t reserved12: 5; /*reserved*/ - volatile uint32_t slv_last_command: 3; /*In the slave mode it is the value of command.*/ - volatile uint32_t slv_last_state: 3; /*In the slave mode it is the state of spi state machine.*/ - volatile uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ - volatile uint32_t slv_cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ - volatile uint32_t slv_wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ - volatile uint32_t slv_wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ - volatile uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ - volatile uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ + uint32_t slv_rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ + uint32_t slv_wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ + uint32_t slv_rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ + uint32_t slv_wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ + uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ + uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ + uint32_t reserved12: 5; /*reserved*/ + uint32_t slv_last_command: 3; /*In the slave mode it is the value of command.*/ + uint32_t slv_last_state: 3; /*In the slave mode it is the state of spi state machine.*/ + uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ + uint32_t slv_cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ + uint32_t slv_wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ + uint32_t slv_wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ + uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ + uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ }; - volatile uint32_t val; + uint32_t val; }slave; union { struct { - volatile uint32_t slv_rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ - volatile uint32_t slv_wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ - volatile uint32_t slv_rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ - volatile uint32_t slv_wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ - volatile uint32_t slv_wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ - volatile uint32_t slv_rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ - volatile uint32_t reserved16: 9; /*reserved*/ - volatile uint32_t slv_status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ - volatile uint32_t slv_status_fast_en: 1; /*In the slave mode enable fast read status.*/ - volatile uint32_t slv_status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ + uint32_t slv_rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ + uint32_t slv_wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ + uint32_t slv_rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ + uint32_t slv_wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ + uint32_t slv_wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t slv_rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t reserved16: 9; /*reserved*/ + uint32_t slv_status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ + uint32_t slv_status_fast_en: 1; /*In the slave mode enable fast read status.*/ + uint32_t slv_status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ }; - volatile uint32_t val; + uint32_t val; }slave1; union { struct { - volatile uint32_t slv_rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ - volatile uint32_t slv_wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ - volatile uint32_t slv_rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ - volatile uint32_t slv_wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ + uint32_t slv_rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ + uint32_t slv_wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ + uint32_t slv_rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ + uint32_t slv_wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ }; - volatile uint32_t val; + uint32_t val; }slave2; union { struct { - volatile uint32_t slv_rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ - volatile uint32_t slv_wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ - volatile uint32_t slv_rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ - volatile uint32_t slv_wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ + uint32_t slv_rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ + uint32_t slv_wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ + uint32_t slv_rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ + uint32_t slv_wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ }; - volatile uint32_t val; + uint32_t val; }slave3; union { struct { - volatile uint32_t slv_wrbuf_dbitlen:24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ - volatile uint32_t reserved24: 8; /*reserved*/ + uint32_t slv_wrbuf_dbitlen:24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }slv_wrbuf_dlen; union { struct { - volatile uint32_t slv_rdbuf_dbitlen:24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ - volatile uint32_t reserved24: 8; /*reserved*/ + uint32_t slv_rdbuf_dbitlen:24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }slv_rdbuf_dlen; union { struct { - volatile uint32_t cache_req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ - volatile uint32_t cache_usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ - volatile uint32_t cache_flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ - volatile uint32_t cache_flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ - volatile uint32_t reserved4: 28; /*reserved*/ + uint32_t cache_req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + uint32_t cache_usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + uint32_t cache_flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + uint32_t cache_flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ + uint32_t reserved4: 28; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }cache_fctrl; union { struct { - volatile uint32_t reserved0: 1; /*reserved*/ - volatile uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ - volatile uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ - volatile uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ - volatile uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ - volatile uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ - volatile uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ - volatile uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ - volatile uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ - volatile uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ - volatile uint32_t reserved29: 3; /*reserved*/ + uint32_t reserved0: 1; /*reserved*/ + uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ + uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ + uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ + uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ + uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ + uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ + uint32_t reserved29: 3; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }cache_sctrl; union { struct { - volatile uint32_t sram_dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ - volatile uint32_t sram_qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ - volatile uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ - volatile uint32_t sram_rstio: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ - volatile uint32_t reserved5: 27; /*reserved*/ + uint32_t sram_dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t sram_qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t sram_rstio: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ + uint32_t reserved5: 27; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }sram_cmd; union { struct { - volatile uint32_t cache_sram_usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ - volatile uint32_t reserved16: 12; /*reserved*/ - volatile uint32_t cache_sram_usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + uint32_t cache_sram_usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t cache_sram_usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ }; - volatile uint32_t val; + uint32_t val; }sram_drd_cmd; union { struct { - volatile uint32_t cache_sram_usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ - volatile uint32_t reserved16: 12; /*reserved*/ - volatile uint32_t cache_sram_usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + uint32_t cache_sram_usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t cache_sram_usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ }; - volatile uint32_t val; + uint32_t val; }sram_dwr_cmd; union { struct { - volatile uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ - volatile uint32_t reserved24: 8; /*reserved*/ + uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ + uint32_t reserved24: 8; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }slv_rd_bit; - volatile uint32_t reserved_68; - volatile uint32_t reserved_6c; - volatile uint32_t reserved_70; - volatile uint32_t reserved_74; - volatile uint32_t reserved_78; - volatile uint32_t reserved_7c; - volatile uint32_t data_buf[16]; /*data buffer*/ - volatile uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ - volatile uint32_t reserved_c4; - volatile uint32_t reserved_c8; - volatile uint32_t reserved_cc; - volatile uint32_t reserved_d0; - volatile uint32_t reserved_d4; - volatile uint32_t reserved_d8; - volatile uint32_t reserved_dc; - volatile uint32_t reserved_e0; - volatile uint32_t reserved_e4; - volatile uint32_t reserved_e8; - volatile uint32_t reserved_ec; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t data_buf[16]; /*data buffer*/ + uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; union { struct { - volatile uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ - volatile uint32_t reserved12: 4; /*reserved*/ - volatile uint32_t t_pp_shift: 4; /*page program delay time shift .*/ - volatile uint32_t reserved20:11; /*reserved*/ - volatile uint32_t t_pp_ena: 1; /*page program delay enable.*/ + uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ + uint32_t reserved12: 4; /*reserved*/ + uint32_t t_pp_shift: 4; /*page program delay time shift .*/ + uint32_t reserved20:11; /*reserved*/ + uint32_t t_pp_ena: 1; /*page program delay enable.*/ }; - volatile uint32_t val; + uint32_t val; }ext0; union { struct { - volatile uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ - volatile uint32_t reserved12: 4; /*reserved*/ - volatile uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ - volatile uint32_t reserved20: 11; /*reserved*/ - volatile uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ + uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ + uint32_t reserved12: 4; /*reserved*/ + uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ + uint32_t reserved20: 11; /*reserved*/ + uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ }; - volatile uint32_t val; + uint32_t val; }ext1; union { struct { - volatile uint32_t st: 3; /*The status of spi state machine .*/ - volatile uint32_t reserved3: 29; /*reserved*/ + uint32_t st: 3; /*The status of spi state machine .*/ + uint32_t reserved3: 29; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }ext2; union { struct { - volatile uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ - volatile uint32_t reserved2: 30; /*reserved*/ + uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ + uint32_t reserved2: 30; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }ext3; union { struct { - volatile uint32_t reserved0: 2; /*reserved*/ - volatile uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ - volatile uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ - volatile uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ - volatile uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ - volatile uint32_t in_loop_test: 1; /*Set bit to test in link.*/ - volatile uint32_t out_loop_test: 1; /*Set bit to test out link.*/ - volatile uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ - volatile uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ - volatile uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ - volatile uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ - volatile uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ - volatile uint32_t reserved13: 1; /*reserved*/ - volatile uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ - volatile uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ - volatile uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ - volatile uint32_t reserved17: 15; /*reserved*/ + uint32_t reserved0: 2; /*reserved*/ + uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ + uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ + uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ + uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ + uint32_t in_loop_test: 1; /*Set bit to test in link.*/ + uint32_t out_loop_test: 1; /*Set bit to test out link.*/ + uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ + uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ + uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ + uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ + uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ + uint32_t reserved13: 1; /*reserved*/ + uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ + uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ + uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ + uint32_t reserved17: 15; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_conf; union { struct { - volatile uint32_t outlink_addr: 20; /*The address of the first outlink descriptor.*/ - volatile uint32_t reserved20: 8; /*reserved*/ - volatile uint32_t outlink_stop: 1; /*Set the bit to stop to use outlink descriptor.*/ - volatile uint32_t outlink_start: 1; /*Set the bit to start to use outlink descriptor.*/ - volatile uint32_t outlink_restart: 1; /*Set the bit to mount on new outlink descriptors.*/ - volatile uint32_t reserved31: 1; /*reserved*/ + uint32_t outlink_addr: 20; /*The address of the first outlink descriptor.*/ + uint32_t reserved20: 8; /*reserved*/ + uint32_t outlink_stop: 1; /*Set the bit to stop to use outlink descriptor.*/ + uint32_t outlink_start: 1; /*Set the bit to start to use outlink descriptor.*/ + uint32_t outlink_restart: 1; /*Set the bit to mount on new outlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_out_link; union { struct { - volatile uint32_t inlink_addr: 20; /*The address of the first inlink descriptor.*/ - volatile uint32_t inlink_auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ - volatile uint32_t reserved21: 7; /*reserved*/ - volatile uint32_t inlink_stop: 1; /*Set the bit to stop to use inlink descriptor.*/ - volatile uint32_t inlink_start: 1; /*Set the bit to start to use inlink descriptor.*/ - volatile uint32_t inlink_restart: 1; /*Set the bit to mount on new inlink descriptors.*/ - volatile uint32_t reserved31: 1; /*reserved*/ + uint32_t inlink_addr: 20; /*The address of the first inlink descriptor.*/ + uint32_t inlink_auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ + uint32_t reserved21: 7; /*reserved*/ + uint32_t inlink_stop: 1; /*Set the bit to stop to use inlink descriptor.*/ + uint32_t inlink_start: 1; /*Set the bit to start to use inlink descriptor.*/ + uint32_t inlink_restart: 1; /*Set the bit to mount on new inlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_in_link; union { struct { - volatile uint32_t dma_rx_en: 1; /*spi dma read data status bit.*/ - volatile uint32_t dma_tx_en: 1; /*spi dma write data status bit.*/ - volatile uint32_t reserved2: 30; /*spi dma read data from memory count.*/ + uint32_t dma_rx_en: 1; /*spi dma read data status bit.*/ + uint32_t dma_tx_en: 1; /*spi dma write data status bit.*/ + uint32_t reserved2: 30; /*spi dma read data from memory count.*/ }; - volatile uint32_t val; + uint32_t val; }dma_status; union { struct { - volatile uint32_t inlink_dscr_empty_int_ena: 1; /*The enable bit for lack of enough inlink descriptors.*/ - volatile uint32_t outlink_dscr_error_int_ena: 1; /*The enable bit for outlink descriptor error.*/ - volatile uint32_t inlink_dscr_error_int_ena: 1; /*The enable bit for inlink descriptor error.*/ - volatile uint32_t in_done_int_ena: 1; /*The enable bit for completing usage of a inlink descriptor.*/ - volatile uint32_t in_err_eof_int_ena: 1; /*The enable bit for receiving error.*/ - volatile uint32_t in_suc_eof_int_ena: 1; /*The enable bit for completing receiving all the packets from host.*/ - volatile uint32_t out_done_int_ena: 1; /*The enable bit for completing usage of a outlink descriptor .*/ - volatile uint32_t out_eof_int_ena: 1; /*The enable bit for sending a packet to host done.*/ - volatile uint32_t out_total_eof_int_ena: 1; /*The enable bit for sending all the packets to host done.*/ - volatile uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty_int_ena: 1; /*The enable bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error_int_ena: 1; /*The enable bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error_int_ena: 1; /*The enable bit for inlink descriptor error.*/ + uint32_t in_done_int_ena: 1; /*The enable bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof_int_ena: 1; /*The enable bit for receiving error.*/ + uint32_t in_suc_eof_int_ena: 1; /*The enable bit for completing receiving all the packets from host.*/ + uint32_t out_done_int_ena: 1; /*The enable bit for completing usage of a outlink descriptor .*/ + uint32_t out_eof_int_ena: 1; /*The enable bit for sending a packet to host done.*/ + uint32_t out_total_eof_int_ena: 1; /*The enable bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_int_ena; union { struct { - volatile uint32_t inlink_dscr_empty_int_raw: 1; /*The raw bit for lack of enough inlink descriptors.*/ - volatile uint32_t outlink_dscr_error_int_raw: 1; /*The raw bit for outlink descriptor error.*/ - volatile uint32_t inlink_dscr_error_int_raw: 1; /*The raw bit for inlink descriptor error.*/ - volatile uint32_t in_done_int_raw: 1; /*The raw bit for completing usage of a inlink descriptor.*/ - volatile uint32_t in_err_eof_int_raw: 1; /*The raw bit for receiving error.*/ - volatile uint32_t in_suc_eof_int_raw: 1; /*The raw bit for completing receiving all the packets from host.*/ - volatile uint32_t out_done_int_raw: 1; /*The raw bit for completing usage of a outlink descriptor.*/ - volatile uint32_t out_eof_int_raw: 1; /*The raw bit for sending a packet to host done.*/ - volatile uint32_t out_total_eof_int_raw: 1; /*The raw bit for sending all the packets to host done.*/ - volatile uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty_int_raw: 1; /*The raw bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error_int_raw: 1; /*The raw bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error_int_raw: 1; /*The raw bit for inlink descriptor error.*/ + uint32_t in_done_int_raw: 1; /*The raw bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof_int_raw: 1; /*The raw bit for receiving error.*/ + uint32_t in_suc_eof_int_raw: 1; /*The raw bit for completing receiving all the packets from host.*/ + uint32_t out_done_int_raw: 1; /*The raw bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof_int_raw: 1; /*The raw bit for sending a packet to host done.*/ + uint32_t out_total_eof_int_raw: 1; /*The raw bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_int_raw; union { struct { - volatile uint32_t inlink_dscr_empty_int_st: 1; /*The status bit for lack of enough inlink descriptors.*/ - volatile uint32_t outlink_dscr_error_int_st: 1; /*The status bit for outlink descriptor error.*/ - volatile uint32_t inlink_dscr_error_int_st: 1; /*The status bit for inlink descriptor error.*/ - volatile uint32_t in_done_int_st: 1; /*The status bit for completing usage of a inlink descriptor.*/ - volatile uint32_t in_err_eof_int_st: 1; /*The status bit for receiving error.*/ - volatile uint32_t in_suc_eof_int_st: 1; /*The status bit for completing receiving all the packets from host.*/ - volatile uint32_t out_done_int_st: 1; /*The status bit for completing usage of a outlink descriptor.*/ - volatile uint32_t out_eof_int_st: 1; /*The status bit for sending a packet to host done.*/ - volatile uint32_t out_total_eof_int_st: 1; /*The status bit for sending all the packets to host done.*/ - volatile uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty_int_st: 1; /*The status bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error_int_st: 1; /*The status bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error_int_st: 1; /*The status bit for inlink descriptor error.*/ + uint32_t in_done_int_st: 1; /*The status bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof_int_st: 1; /*The status bit for receiving error.*/ + uint32_t in_suc_eof_int_st: 1; /*The status bit for completing receiving all the packets from host.*/ + uint32_t out_done_int_st: 1; /*The status bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof_int_st: 1; /*The status bit for sending a packet to host done.*/ + uint32_t out_total_eof_int_st: 1; /*The status bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_int_st; union { struct { - volatile uint32_t inlink_dscr_empty_int_clr: 1; /*The clear bit for lack of enough inlink descriptors.*/ - volatile uint32_t outlink_dscr_error_int_clr: 1; /*The clear bit for outlink descriptor error.*/ - volatile uint32_t inlink_dscr_error_int_clr: 1; /*The clear bit for inlink descriptor error.*/ - volatile uint32_t in_done_int_clr: 1; /*The clear bit for completing usage of a inlink descriptor.*/ - volatile uint32_t in_err_eof_int_clr: 1; /*The clear bit for receiving error.*/ - volatile uint32_t in_suc_eof_int_clr: 1; /*The clear bit for completing receiving all the packets from host.*/ - volatile uint32_t out_done_int_clr: 1; /*The clear bit for completing usage of a outlink descriptor.*/ - volatile uint32_t out_eof_int_clr: 1; /*The clear bit for sending a packet to host done.*/ - volatile uint32_t out_total_eof_int_clr: 1; /*The clear bit for sending all the packets to host done.*/ - volatile uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty_int_clr: 1; /*The clear bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error_int_clr: 1; /*The clear bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error_int_clr: 1; /*The clear bit for inlink descriptor error.*/ + uint32_t in_done_int_clr: 1; /*The clear bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof_int_clr: 1; /*The clear bit for receiving error.*/ + uint32_t in_suc_eof_int_clr: 1; /*The clear bit for completing receiving all the packets from host.*/ + uint32_t out_done_int_clr: 1; /*The clear bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof_int_clr: 1; /*The clear bit for sending a packet to host done.*/ + uint32_t out_total_eof_int_clr: 1; /*The clear bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }dma_int_clr; - volatile uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ - volatile uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ - volatile uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ - volatile uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ - volatile uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ - volatile uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ - volatile uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ - volatile uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ - volatile uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ - volatile uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ - volatile uint32_t dma_rx_status; /*spi dma read data from memory status.*/ - volatile uint32_t dma_tx_status; /*spi dma write data to memory status.*/ - volatile uint32_t reserved_150; - volatile uint32_t reserved_154; - volatile uint32_t reserved_158; - volatile uint32_t reserved_15c; - volatile uint32_t reserved_160; - volatile uint32_t reserved_164; - volatile uint32_t reserved_168; - volatile uint32_t reserved_16c; - volatile uint32_t reserved_170; - volatile uint32_t reserved_174; - volatile uint32_t reserved_178; - volatile uint32_t reserved_17c; - volatile uint32_t reserved_180; - volatile uint32_t reserved_184; - volatile uint32_t reserved_188; - volatile uint32_t reserved_18c; - volatile uint32_t reserved_190; - volatile uint32_t reserved_194; - volatile uint32_t reserved_198; - volatile uint32_t reserved_19c; - volatile uint32_t reserved_1a0; - volatile uint32_t reserved_1a4; - volatile uint32_t reserved_1a8; - volatile uint32_t reserved_1ac; - volatile uint32_t reserved_1b0; - volatile uint32_t reserved_1b4; - volatile uint32_t reserved_1b8; - volatile uint32_t reserved_1bc; - volatile uint32_t reserved_1c0; - volatile uint32_t reserved_1c4; - volatile uint32_t reserved_1c8; - volatile uint32_t reserved_1cc; - volatile uint32_t reserved_1d0; - volatile uint32_t reserved_1d4; - volatile uint32_t reserved_1d8; - volatile uint32_t reserved_1dc; - volatile uint32_t reserved_1e0; - volatile uint32_t reserved_1e4; - volatile uint32_t reserved_1e8; - volatile uint32_t reserved_1ec; - volatile uint32_t reserved_1f0; - volatile uint32_t reserved_1f4; - volatile uint32_t reserved_1f8; - volatile uint32_t reserved_1fc; - volatile uint32_t reserved_200; - volatile uint32_t reserved_204; - volatile uint32_t reserved_208; - volatile uint32_t reserved_20c; - volatile uint32_t reserved_210; - volatile uint32_t reserved_214; - volatile uint32_t reserved_218; - volatile uint32_t reserved_21c; - volatile uint32_t reserved_220; - volatile uint32_t reserved_224; - volatile uint32_t reserved_228; - volatile uint32_t reserved_22c; - volatile uint32_t reserved_230; - volatile uint32_t reserved_234; - volatile uint32_t reserved_238; - volatile uint32_t reserved_23c; - volatile uint32_t reserved_240; - volatile uint32_t reserved_244; - volatile uint32_t reserved_248; - volatile uint32_t reserved_24c; - volatile uint32_t reserved_250; - volatile uint32_t reserved_254; - volatile uint32_t reserved_258; - volatile uint32_t reserved_25c; - volatile uint32_t reserved_260; - volatile uint32_t reserved_264; - volatile uint32_t reserved_268; - volatile uint32_t reserved_26c; - volatile uint32_t reserved_270; - volatile uint32_t reserved_274; - volatile uint32_t reserved_278; - volatile uint32_t reserved_27c; - volatile uint32_t reserved_280; - volatile uint32_t reserved_284; - volatile uint32_t reserved_288; - volatile uint32_t reserved_28c; - volatile uint32_t reserved_290; - volatile uint32_t reserved_294; - volatile uint32_t reserved_298; - volatile uint32_t reserved_29c; - volatile uint32_t reserved_2a0; - volatile uint32_t reserved_2a4; - volatile uint32_t reserved_2a8; - volatile uint32_t reserved_2ac; - volatile uint32_t reserved_2b0; - volatile uint32_t reserved_2b4; - volatile uint32_t reserved_2b8; - volatile uint32_t reserved_2bc; - volatile uint32_t reserved_2c0; - volatile uint32_t reserved_2c4; - volatile uint32_t reserved_2c8; - volatile uint32_t reserved_2cc; - volatile uint32_t reserved_2d0; - volatile uint32_t reserved_2d4; - volatile uint32_t reserved_2d8; - volatile uint32_t reserved_2dc; - volatile uint32_t reserved_2e0; - volatile uint32_t reserved_2e4; - volatile uint32_t reserved_2e8; - volatile uint32_t reserved_2ec; - volatile uint32_t reserved_2f0; - volatile uint32_t reserved_2f4; - volatile uint32_t reserved_2f8; - volatile uint32_t reserved_2fc; - volatile uint32_t reserved_300; - volatile uint32_t reserved_304; - volatile uint32_t reserved_308; - volatile uint32_t reserved_30c; - volatile uint32_t reserved_310; - volatile uint32_t reserved_314; - volatile uint32_t reserved_318; - volatile uint32_t reserved_31c; - volatile uint32_t reserved_320; - volatile uint32_t reserved_324; - volatile uint32_t reserved_328; - volatile uint32_t reserved_32c; - volatile uint32_t reserved_330; - volatile uint32_t reserved_334; - volatile uint32_t reserved_338; - volatile uint32_t reserved_33c; - volatile uint32_t reserved_340; - volatile uint32_t reserved_344; - volatile uint32_t reserved_348; - volatile uint32_t reserved_34c; - volatile uint32_t reserved_350; - volatile uint32_t reserved_354; - volatile uint32_t reserved_358; - volatile uint32_t reserved_35c; - volatile uint32_t reserved_360; - volatile uint32_t reserved_364; - volatile uint32_t reserved_368; - volatile uint32_t reserved_36c; - volatile uint32_t reserved_370; - volatile uint32_t reserved_374; - volatile uint32_t reserved_378; - volatile uint32_t reserved_37c; - volatile uint32_t reserved_380; - volatile uint32_t reserved_384; - volatile uint32_t reserved_388; - volatile uint32_t reserved_38c; - volatile uint32_t reserved_390; - volatile uint32_t reserved_394; - volatile uint32_t reserved_398; - volatile uint32_t reserved_39c; - volatile uint32_t reserved_3a0; - volatile uint32_t reserved_3a4; - volatile uint32_t reserved_3a8; - volatile uint32_t reserved_3ac; - volatile uint32_t reserved_3b0; - volatile uint32_t reserved_3b4; - volatile uint32_t reserved_3b8; - volatile uint32_t reserved_3bc; - volatile uint32_t reserved_3c0; - volatile uint32_t reserved_3c4; - volatile uint32_t reserved_3c8; - volatile uint32_t reserved_3cc; - volatile uint32_t reserved_3d0; - volatile uint32_t reserved_3d4; - volatile uint32_t reserved_3d8; - volatile uint32_t reserved_3dc; - volatile uint32_t reserved_3e0; - volatile uint32_t reserved_3e4; - volatile uint32_t reserved_3e8; - volatile uint32_t reserved_3ec; - volatile uint32_t reserved_3f0; - volatile uint32_t reserved_3f4; - volatile uint32_t reserved_3f8; + uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ + uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ + uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ + uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ + uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ + uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ + uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ + uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ + uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ + uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ + uint32_t dma_rx_status; /*spi dma read data from memory status.*/ + uint32_t dma_tx_status; /*spi dma write data to memory status.*/ + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; union { struct { - volatile uint32_t date: 28; /*SPI register version.*/ - volatile uint32_t reserved28: 4; /*reserved*/ + uint32_t date: 28; /*SPI register version.*/ + uint32_t reserved28: 4; /*reserved*/ }; - volatile uint32_t val; + uint32_t val; }date; } spi_dev_t; -extern volatile spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ -extern volatile spi_dev_t SPI1; -extern volatile spi_dev_t SPI2; -extern volatile spi_dev_t SPI3; +extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ +extern spi_dev_t SPI1; +extern spi_dev_t SPI2; +extern spi_dev_t SPI3; #endif /* _SOC_SPI_STRUCT_H_ */ diff --git a/components/esp32/include/soc/timer_group_struct.h b/components/esp32/include/soc/timer_group_struct.h index b385f04f7..2160dfeea 100644 --- a/components/esp32/include/soc/timer_group_struct.h +++ b/components/esp32/include/soc/timer_group_struct.h @@ -13,183 +13,183 @@ // limitations under the License. #ifndef _SOC_TIMG_STRUCT_H_ #define _SOC_TIMG_STRUCT_H_ -typedef struct { +typedef volatile struct { struct{ union { struct { - volatile uint32_t reserved0: 10; - volatile uint32_t alarm_en: 1; /*When set alarm is enabled*/ - volatile uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ - volatile uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ - volatile uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ - volatile uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ - volatile uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ - volatile uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ + uint32_t reserved0: 10; + uint32_t alarm_en: 1; /*When set alarm is enabled*/ + uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ + uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ + uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ + uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ + uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ }; - volatile uint32_t val; + uint32_t val; }config; - volatile uint32_t timer_cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ - volatile uint32_t timer_cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ - volatile uint32_t timer_update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ - volatile uint32_t timer_alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ - volatile uint32_t timer_alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ - volatile uint32_t timer_load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ - volatile uint32_t timer_load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ - volatile uint32_t timer_reload; /*Write any value will trigger timer 0 time-base counter reload*/ + uint32_t timer_cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t timer_cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t timer_update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t timer_alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t timer_alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t timer_load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t timer_load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t timer_reload; /*Write any value will trigger timer 0 time-base counter reload*/ }hw_timer[2]; union { struct { - volatile uint32_t reserved0: 14; - volatile uint32_t wdt_flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ - volatile uint32_t wdt_sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ - volatile uint32_t wdt_cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ - volatile uint32_t wdt_level_int_en: 1; /*When set level type interrupt generation is enabled*/ - volatile uint32_t wdt_edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ - volatile uint32_t wdt_stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - volatile uint32_t wdt_stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - volatile uint32_t wdt_stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - volatile uint32_t wdt_stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - volatile uint32_t wdt_en: 1; /*When set SWDT is enabled*/ + uint32_t reserved0: 14; + uint32_t wdt_flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ + uint32_t wdt_sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t wdt_cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t wdt_level_int_en: 1; /*When set level type interrupt generation is enabled*/ + uint32_t wdt_edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ + uint32_t wdt_stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t wdt_stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t wdt_stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t wdt_stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t wdt_en: 1; /*When set SWDT is enabled*/ }; - volatile uint32_t val; + uint32_t val; }wdt_config0; union { struct { - volatile uint32_t reserved0: 16; - volatile uint32_t wdt_clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ + uint32_t reserved0: 16; + uint32_t wdt_clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ }; - volatile uint32_t val; + uint32_t val; }wdt_config1; - volatile uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ - volatile uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ - volatile uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ - volatile uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ - volatile uint32_t wdt_feed; /*Write any value will feed SWDT*/ - volatile uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ + uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ + uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ + uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ + uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ + uint32_t wdt_feed; /*Write any value will feed SWDT*/ + uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ union { struct { - volatile uint32_t reserved0: 12; - volatile uint32_t rtc_cali_start_cycling: 1; - volatile uint32_t rtc_cali_clk_sel: 2; - volatile uint32_t rtc_cali_rdy: 1; - volatile uint32_t rtc_cali_max: 15; - volatile uint32_t rtc_cali_start: 1; + uint32_t reserved0: 12; + uint32_t rtc_cali_start_cycling: 1; + uint32_t rtc_cali_clk_sel: 2; + uint32_t rtc_cali_rdy: 1; + uint32_t rtc_cali_max: 15; + uint32_t rtc_cali_start: 1; }; - volatile uint32_t val; + uint32_t val; }rtc_cali_cfg; union { struct { - volatile uint32_t reserved0: 7; - volatile uint32_t rtc_cali_value:25; + uint32_t reserved0: 7; + uint32_t rtc_cali_value:25; }; - volatile uint32_t val; + uint32_t val; }rtc_cali_cfg1; union { struct { - volatile uint32_t reserved0: 7; - volatile uint32_t lact_rtc_only: 1; - volatile uint32_t lact_cpst_en: 1; - volatile uint32_t lact_lac_en: 1; - volatile uint32_t lact_alarm_en: 1; - volatile uint32_t lact_level_int_en: 1; - volatile uint32_t lact_edge_int_en: 1; - volatile uint32_t lact_divider: 16; - volatile uint32_t lact_autoreload: 1; - volatile uint32_t lact_increase: 1; - volatile uint32_t lact_en: 1; + uint32_t reserved0: 7; + uint32_t lact_rtc_only: 1; + uint32_t lact_cpst_en: 1; + uint32_t lact_lac_en: 1; + uint32_t lact_alarm_en: 1; + uint32_t lact_level_int_en: 1; + uint32_t lact_edge_int_en: 1; + uint32_t lact_divider: 16; + uint32_t lact_autoreload: 1; + uint32_t lact_increase: 1; + uint32_t lact_en: 1; }; - volatile uint32_t val; + uint32_t val; }lactconfig; union { struct { - volatile uint32_t reserved0: 6; - volatile uint32_t lact_rtc_step_len:26; + uint32_t reserved0: 6; + uint32_t lact_rtc_step_len:26; }; - volatile uint32_t val; + uint32_t val; }lactrtc; - volatile uint32_t lactlo; /**/ - volatile uint32_t lacthi; /**/ - volatile uint32_t lactupdate; /**/ - volatile uint32_t lactalarmlo; /**/ - volatile uint32_t lactalarmhi; /**/ - volatile uint32_t lactloadlo; /**/ - volatile uint32_t lactloadhi; /**/ - volatile uint32_t lactload; /**/ + uint32_t lactlo; /**/ + uint32_t lacthi; /**/ + uint32_t lactupdate; /**/ + uint32_t lactalarmlo; /**/ + uint32_t lactalarmhi; /**/ + uint32_t lactloadlo; /**/ + uint32_t lactloadhi; /**/ + uint32_t lactload; /**/ union { struct { - volatile uint32_t t0_int_ena: 1; /*interrupt when timer0 alarm*/ - volatile uint32_t t1_int_ena: 1; /*interrupt when timer1 alarm*/ - volatile uint32_t wdt_int_ena: 1; /*Interrupt when an interrupt stage timeout*/ - volatile uint32_t lact_int_ena: 1; - volatile uint32_t reserved4: 28; + uint32_t t0_int_ena: 1; /*interrupt when timer0 alarm*/ + uint32_t t1_int_ena: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt_int_ena: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact_int_ena: 1; + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }int_ena_timers; union { struct { - volatile uint32_t t0_int_raw: 1; /*interrupt when timer0 alarm*/ - volatile uint32_t t1_int_raw: 1; /*interrupt when timer1 alarm*/ - volatile uint32_t wdt_int_raw: 1; /*Interrupt when an interrupt stage timeout*/ - volatile uint32_t lact_int_raw: 1; - volatile uint32_t reserved4: 28; + uint32_t t0_int_raw: 1; /*interrupt when timer0 alarm*/ + uint32_t t1_int_raw: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt_int_raw: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact_int_raw: 1; + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }int_raw_timers; union { struct { - volatile uint32_t t0_int_st: 1; /*interrupt when timer0 alarm*/ - volatile uint32_t t1_int_st: 1; /*interrupt when timer1 alarm*/ - volatile uint32_t wdt_int_st: 1; /*Interrupt when an interrupt stage timeout*/ - volatile uint32_t lact_int_st: 1; - volatile uint32_t reserved4: 28; + uint32_t t0_int_st: 1; /*interrupt when timer0 alarm*/ + uint32_t t1_int_st: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt_int_st: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact_int_st: 1; + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }int_st_timers; union { struct { - volatile uint32_t t0_int_clr: 1; /*interrupt when timer0 alarm*/ - volatile uint32_t t1_int_clr: 1; /*interrupt when timer1 alarm*/ - volatile uint32_t wdt_int_clr: 1; /*Interrupt when an interrupt stage timeout*/ - volatile uint32_t lact_int_clr: 1; - volatile uint32_t reserved4: 28; + uint32_t t0_int_clr: 1; /*interrupt when timer0 alarm*/ + uint32_t t1_int_clr: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt_int_clr: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact_int_clr: 1; + uint32_t reserved4: 28; }; - volatile uint32_t val; + uint32_t val; }int_clr_timers; - volatile uint32_t reserved_a8; - volatile uint32_t reserved_ac; - volatile uint32_t reserved_b0; - volatile uint32_t reserved_b4; - volatile uint32_t reserved_b8; - volatile uint32_t reserved_bc; - volatile uint32_t reserved_c0; - volatile uint32_t reserved_c4; - volatile uint32_t reserved_c8; - volatile uint32_t reserved_cc; - volatile uint32_t reserved_d0; - volatile uint32_t reserved_d4; - volatile uint32_t reserved_d8; - volatile uint32_t reserved_dc; - volatile uint32_t reserved_e0; - volatile uint32_t reserved_e4; - volatile uint32_t reserved_e8; - volatile uint32_t reserved_ec; - volatile uint32_t reserved_f0; - volatile uint32_t reserved_f4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; union { struct { - volatile uint32_t date:28; /*Version of this regfile*/ - volatile uint32_t reserved28: 4; + uint32_t date:28; /*Version of this regfile*/ + uint32_t reserved28: 4; }; - volatile uint32_t val; + uint32_t val; }timg_date; union { struct { - volatile uint32_t reserved0: 31; - volatile uint32_t clk_en: 1; /*Force clock enable for this regfile*/ + uint32_t reserved0: 31; + uint32_t clk_en: 1; /*Force clock enable for this regfile*/ }; - volatile uint32_t val; + uint32_t val; }clk; } timg_dev_t; -extern volatile timg_dev_t TIMERG0; -extern volatile timg_dev_t TIMERG1; +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; #endif /* _SOC_TIMG_STRUCT_H_ */ diff --git a/components/esp32/include/soc/uart_struct.h b/components/esp32/include/soc/uart_struct.h index cd756bec3..9874a6af6 100644 --- a/components/esp32/include/soc/uart_struct.h +++ b/components/esp32/include/soc/uart_struct.h @@ -13,353 +13,353 @@ // limitations under the License. #ifndef _SOC_UART_STRUCT_H_ #define _SOC_UART_STRUCT_H_ -typedef struct { +typedef volatile struct { union { struct { - volatile uint32_t fifo_rw_byte: 8; /*This register stores one byte data read by rx fifo.*/ - volatile uint32_t reserved8: 24; + uint32_t fifo_rw_byte: 8; /*This register stores one byte data read by rx fifo.*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }fifo; union { struct { - volatile uint32_t rxfifo_full_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ - volatile uint32_t txfifo_empty_int_raw: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ - volatile uint32_t parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ - volatile uint32_t frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ - volatile uint32_t rxfifo_ovf_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ - volatile uint32_t dsr_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ - volatile uint32_t cts_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ - volatile uint32_t brk_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ - volatile uint32_t rxfifo_tout_int_raw: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - volatile uint32_t sw_xon_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ - volatile uint32_t sw_xoff_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ - volatile uint32_t glitch_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ - volatile uint32_t tx_brk_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ - volatile uint32_t tx_brk_idle_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ - volatile uint32_t tx_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ - volatile uint32_t rs485_parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ - volatile uint32_t rs485_frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ - volatile uint32_t rs485_clash_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ - volatile uint32_t at_cmd_char_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ - volatile uint32_t reserved19: 13; + uint32_t rxfifo_full_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t txfifo_empty_int_raw: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ + uint32_t parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ + uint32_t frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ + uint32_t rxfifo_ovf_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ + uint32_t dsr_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ + uint32_t cts_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ + uint32_t brk_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ + uint32_t rxfifo_tout_int_raw: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + uint32_t sw_xon_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xoff_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ + uint32_t glitch_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ + uint32_t tx_brk_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ + uint32_t tx_brk_idle_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ + uint32_t tx_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ + uint32_t rs485_parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ + uint32_t rs485_frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ + uint32_t rs485_clash_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ + uint32_t at_cmd_char_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ + uint32_t reserved19: 13; }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t rxfifo_full_int_st: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ - volatile uint32_t txfifo_empty_int_st: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ - volatile uint32_t parity_err_int_st: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ - volatile uint32_t frm_err_int_st: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ - volatile uint32_t rxfifo_ovf_int_st: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ - volatile uint32_t dsr_chg_int_st: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ - volatile uint32_t cts_chg_int_st: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ - volatile uint32_t brk_det_int_st: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ - volatile uint32_t rxfifo_tout_int_st: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ - volatile uint32_t sw_xon_int_st: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ - volatile uint32_t sw_xoff_int_st: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ - volatile uint32_t glitch_det_int_st: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ - volatile uint32_t tx_brk_done_int_st: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - volatile uint32_t tx_brk_idle_done_int_st: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ - volatile uint32_t tx_done_int_st: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ - volatile uint32_t rs485_parity_err_int_st: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ - volatile uint32_t rs485_frm_err_int_st: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ - volatile uint32_t rs485_clash_int_st: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ - volatile uint32_t at_cmd_char_det_int_st: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ - volatile uint32_t reserved19: 13; + uint32_t rxfifo_full_int_st: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + uint32_t txfifo_empty_int_st: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + uint32_t parity_err_int_st: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + uint32_t frm_err_int_st: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ + uint32_t rxfifo_ovf_int_st: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + uint32_t dsr_chg_int_st: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + uint32_t cts_chg_int_st: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + uint32_t brk_det_int_st: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + uint32_t rxfifo_tout_int_st: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + uint32_t sw_xon_int_st: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + uint32_t sw_xoff_int_st: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + uint32_t glitch_det_int_st: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + uint32_t tx_brk_done_int_st: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done_int_st: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_done_int_st: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + uint32_t rs485_parity_err_int_st: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + uint32_t rs485_frm_err_int_st: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + uint32_t rs485_clash_int_st: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + uint32_t at_cmd_char_det_int_st: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + uint32_t reserved19: 13; }; - volatile uint32_t val; + uint32_t val; }int_st; union { struct { - volatile uint32_t rxfifo_full_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - volatile uint32_t txfifo_empty_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - volatile uint32_t parity_err_int_ena: 1; /*This is the enable bit for parity_err_int_st register.*/ - volatile uint32_t frm_err_int_ena: 1; /*This is the enable bit for frm_err_int_st register.*/ - volatile uint32_t rxfifo_ovf_int_ena: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ - volatile uint32_t dsr_chg_int_ena: 1; /*This is the enable bit for dsr_chg_int_st register.*/ - volatile uint32_t cts_chg_int_ena: 1; /*This is the enable bit for cts_chg_int_st register.*/ - volatile uint32_t brk_det_int_ena: 1; /*This is the enable bit for brk_det_int_st register.*/ - volatile uint32_t rxfifo_tout_int_ena: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ - volatile uint32_t sw_xon_int_ena: 1; /*This is the enable bit for sw_xon_int_st register.*/ - volatile uint32_t sw_xoff_int_ena: 1; /*This is the enable bit for sw_xoff_int_st register.*/ - volatile uint32_t glitch_det_int_ena: 1; /*This is the enable bit for glitch_det_int_st register.*/ - volatile uint32_t tx_brk_done_int_ena: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ - volatile uint32_t tx_brk_idle_done_int_ena: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ - volatile uint32_t tx_done_int_ena: 1; /*This is the enable bit for tx_done_int_st register.*/ - volatile uint32_t rs485_parity_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - volatile uint32_t rs485_frm_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - volatile uint32_t rs485_clash_int_ena: 1; /*This is the enable bit for rs485_clash_int_st register.*/ - volatile uint32_t at_cmd_char_det_int_ena: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ - volatile uint32_t reserved19: 13; + uint32_t rxfifo_full_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t txfifo_empty_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t parity_err_int_ena: 1; /*This is the enable bit for parity_err_int_st register.*/ + uint32_t frm_err_int_ena: 1; /*This is the enable bit for frm_err_int_st register.*/ + uint32_t rxfifo_ovf_int_ena: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + uint32_t dsr_chg_int_ena: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + uint32_t cts_chg_int_ena: 1; /*This is the enable bit for cts_chg_int_st register.*/ + uint32_t brk_det_int_ena: 1; /*This is the enable bit for brk_det_int_st register.*/ + uint32_t rxfifo_tout_int_ena: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + uint32_t sw_xon_int_ena: 1; /*This is the enable bit for sw_xon_int_st register.*/ + uint32_t sw_xoff_int_ena: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + uint32_t glitch_det_int_ena: 1; /*This is the enable bit for glitch_det_int_st register.*/ + uint32_t tx_brk_done_int_ena: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + uint32_t tx_brk_idle_done_int_ena: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + uint32_t tx_done_int_ena: 1; /*This is the enable bit for tx_done_int_st register.*/ + uint32_t rs485_parity_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_frm_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_clash_int_ena: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + uint32_t at_cmd_char_det_int_ena: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + uint32_t reserved19: 13; }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t rxfifo_full_int_clr: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ - volatile uint32_t txfifo_empty_int_clr: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ - volatile uint32_t parity_err_int_clr: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ - volatile uint32_t frm_err_int_clr: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ - volatile uint32_t rxfifo_ovf_int_clr: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ - volatile uint32_t dsr_chg_int_clr: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ - volatile uint32_t cts_chg_int_clr: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ - volatile uint32_t brk_det_int_clr: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ - volatile uint32_t rxfifo_tout_int_clr: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ - volatile uint32_t sw_xon_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - volatile uint32_t sw_xoff_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - volatile uint32_t glitch_det_int_clr: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ - volatile uint32_t tx_brk_done_int_clr: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ - volatile uint32_t tx_brk_idle_done_int_clr: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ - volatile uint32_t tx_done_int_clr: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ - volatile uint32_t rs485_parity_err_int_clr: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ - volatile uint32_t rs485_frm_err_int_clr: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ - volatile uint32_t rs485_clash_int_clr: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ - volatile uint32_t at_cmd_char_det_int_clr: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ - volatile uint32_t reserved19: 13; + uint32_t rxfifo_full_int_clr: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + uint32_t txfifo_empty_int_clr: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + uint32_t parity_err_int_clr: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + uint32_t frm_err_int_clr: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + uint32_t rxfifo_ovf_int_clr: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + uint32_t dsr_chg_int_clr: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + uint32_t cts_chg_int_clr: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + uint32_t brk_det_int_clr: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + uint32_t rxfifo_tout_int_clr: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + uint32_t sw_xon_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t sw_xoff_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t glitch_det_int_clr: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + uint32_t tx_brk_done_int_clr: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + uint32_t tx_brk_idle_done_int_clr: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + uint32_t tx_done_int_clr: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + uint32_t rs485_parity_err_int_clr: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + uint32_t rs485_frm_err_int_clr: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + uint32_t rs485_clash_int_clr: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + uint32_t at_cmd_char_det_int_clr: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + uint32_t reserved19: 13; }; - volatile uint32_t val; + uint32_t val; }int_clr; union { struct { - volatile uint32_t clkdiv: 20; /*The register value is the integer part of the frequency divider's factor.*/ - volatile uint32_t clkdiv_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ - volatile uint32_t reserved24: 8; + uint32_t clkdiv: 20; /*The register value is the integer part of the frequency divider's factor.*/ + uint32_t clkdiv_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }clk_div; union { struct { - volatile uint32_t auto_baud_en: 1; /*This is the enable bit for detecting baudrate.*/ - volatile uint32_t reserved1: 7; - volatile uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ - volatile uint32_t reserved16: 16; + uint32_t auto_baud_en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t reserved1: 7; + uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ + uint32_t reserved16: 16; }; - volatile uint32_t val; + uint32_t val; }auto_baud; union { struct { - volatile uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ - volatile uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ - volatile uint32_t reserved12: 1; - volatile uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ - volatile uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ - volatile uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ - volatile uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ - volatile uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ - volatile uint32_t reserved28: 1; - volatile uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ - volatile uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ - volatile uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ + uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ + uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ + uint32_t reserved12: 1; + uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ + uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ + uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ + uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ + uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ + uint32_t reserved28: 1; + uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ + uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ + uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ }; - volatile uint32_t val; + uint32_t val; }status; union { struct { - volatile uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ - volatile uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ - volatile uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ - volatile uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ - volatile uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ - volatile uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ - volatile uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ - volatile uint32_t irda_dplx: 1; /*Set this bit to enable irda loopback mode.*/ - volatile uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ - volatile uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ - volatile uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ - volatile uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ - volatile uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ - volatile uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ - volatile uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ - volatile uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ - volatile uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ - volatile uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ - volatile uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ - volatile uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ - volatile uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ - volatile uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ - volatile uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ - volatile uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ - volatile uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ - volatile uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ - volatile uint32_t reserved28: 4; + uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ + uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ + uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ + uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ + uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ + uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ + uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ + uint32_t irda_dplx: 1; /*Set this bit to enable irda loopback mode.*/ + uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ + uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ + uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ + uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ + uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ + uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ + uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ + uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ + uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ + uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ + uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ + uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ + uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ + uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ + uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ + uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ + uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ + uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ + uint32_t reserved28: 4; }; - volatile uint32_t val; + uint32_t val; }conf0; union { struct { - volatile uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ - volatile uint32_t reserved7: 1; - volatile uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ - volatile uint32_t reserved15: 1; - volatile uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ - volatile uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ - volatile uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ - volatile uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ + uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ + uint32_t reserved7: 1; + uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ + uint32_t reserved15: 1; + uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ + uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ + uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ }; - volatile uint32_t val; + uint32_t val; }conf1; union { struct { - volatile uint32_t lowpulse_min_cnt:20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ - volatile uint32_t reserved20: 12; + uint32_t lowpulse_min_cnt:20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }lowpulse; union { struct { - volatile uint32_t highpulse_min_cnt:20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ - volatile uint32_t reserved20: 12; + uint32_t highpulse_min_cnt:20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }highpulse; union { struct { - volatile uint32_t rxd_edge_cnt:10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ - volatile uint32_t reserved10: 22; + uint32_t rxd_edge_cnt:10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }rxd_cnt; union { struct { - volatile uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ - volatile uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ - volatile uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ - volatile uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ - volatile uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ - volatile uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ - volatile uint32_t reserved6: 26; + uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ + uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ + uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ + uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ + uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ + uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ + uint32_t reserved6: 26; }; - volatile uint32_t val; + uint32_t val; }flow_conf; union { struct { - volatile uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ - volatile uint32_t reserved10: 22; + uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }sleep_conf; union { struct { - volatile uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ - volatile uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ - volatile uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ - volatile uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ + uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ + uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ + uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ + uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ }; - volatile uint32_t val; + uint32_t val; }swfc_conf; union { struct { - volatile uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ - volatile uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ - volatile uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ - volatile uint32_t reserved28: 4; + uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ + uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ + uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ + uint32_t reserved28: 4; }; - volatile uint32_t val; + uint32_t val; }idle_conf; union { struct { - volatile uint32_t rs485_en: 1; /*Set this bit to choose rs485 mode.*/ - volatile uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - volatile uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - volatile uint32_t rs485tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ - volatile uint32_t rs485rxby_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ - volatile uint32_t rs485_rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ - volatile uint32_t rs485_tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ - volatile uint32_t reserved10: 22; + uint32_t rs485_en: 1; /*Set this bit to choose rs485 mode.*/ + uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ + uint32_t rs485tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ + uint32_t rs485rxby_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ + uint32_t rs485_rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + uint32_t rs485_tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t reserved10: 22; }; - volatile uint32_t val; + uint32_t val; }rs485_conf; union { struct { - volatile uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ - volatile uint32_t reserved24: 8; + uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }at_cmd_precnt; union { struct { - volatile uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ - volatile uint32_t reserved24: 8; + uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }at_cmd_postcnt; union { struct { - volatile uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ - volatile uint32_t reserved24: 8; + uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }at_cmd_gaptout; union { struct { - volatile uint32_t at_cmd_char: 8; /*This register is used to configure the content of at_cmd char.*/ - volatile uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ - volatile uint32_t reserved16: 16; + uint32_t at_cmd_char: 8; /*This register is used to configure the content of at_cmd char.*/ + uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ + uint32_t reserved16: 16; }; - volatile uint32_t val; + uint32_t val; }at_cmd_char; union { struct { - volatile uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ - volatile uint32_t reserved1: 1; - volatile uint32_t reserved2: 1; - volatile uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ - volatile uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ - volatile uint32_t reserved11: 4; - volatile uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ - volatile uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ - volatile uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ - volatile uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ - volatile uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ - volatile uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ - volatile uint32_t reserved31: 1; + uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ + uint32_t reserved1: 1; + uint32_t reserved2: 1; + uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ + uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ + uint32_t reserved11: 4; + uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ + uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ + uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ + uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ + uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ + uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ + uint32_t reserved31: 1; }; - volatile uint32_t val; + uint32_t val; }mem_conf; union { struct { - volatile uint32_t mem_tx_status:24; - volatile uint32_t reserved24: 8; + uint32_t mem_tx_status:24; + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }mem_tx_status; union { struct { - volatile uint32_t mem_rx_status:24; - volatile uint32_t reserved24: 8; + uint32_t mem_rx_status:24; + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }mem_rx_status; union { struct { - volatile uint32_t rx_mem_cnt: 3; /*refer to the rxfifo_cnt's description.*/ - volatile uint32_t tx_mem_cnt: 3; /*refer to the txfifo_cnt's description.*/ - volatile uint32_t reserved6: 26; + uint32_t rx_mem_cnt: 3; /*refer to the rxfifo_cnt's description.*/ + uint32_t tx_mem_cnt: 3; /*refer to the txfifo_cnt's description.*/ + uint32_t reserved6: 26; }; - volatile uint32_t val; + uint32_t val; }mem_cnt_status; union { struct { - volatile uint32_t posedge_min_cnt:20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ - volatile uint32_t reserved20: 12; + uint32_t posedge_min_cnt:20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }pospulse; union { struct { - volatile uint32_t negedge_min_cnt:20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ - volatile uint32_t reserved20: 12; + uint32_t negedge_min_cnt:20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; - volatile uint32_t val; + uint32_t val; }negpulse; - volatile uint32_t reserved_70; - volatile uint32_t reserved_74; - volatile uint32_t date; /**/ - volatile uint32_t id; /**/ + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t date; /**/ + uint32_t id; /**/ } uart_dev_t; -extern volatile uart_dev_t UART0; -extern volatile uart_dev_t UART1; -extern volatile uart_dev_t UART2; +extern uart_dev_t UART0; +extern uart_dev_t UART1; +extern uart_dev_t UART2; #endif /* _SOC_UART_STRUCT_H_ */ diff --git a/components/esp32/include/soc/uhci_struct.h b/components/esp32/include/soc/uhci_struct.h index 323d3beac..5a78990f2 100644 --- a/components/esp32/include/soc/uhci_struct.h +++ b/components/esp32/include/soc/uhci_struct.h @@ -13,325 +13,325 @@ // limitations under the License. #ifndef _SOC_UHCI_STRUCT_H_ #define _SOC_UHCI_STRUCT_H_ -typedef struct { +typedef volatile struct { union { struct { - volatile uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ - volatile uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ - volatile uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ - volatile uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ - volatile uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ - volatile uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ - volatile uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ - volatile uint32_t out_no_restart_clr: 1; /*don't use*/ - volatile uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ - volatile uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ - volatile uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ - volatile uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ - volatile uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ - volatile uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ - volatile uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ - volatile uint32_t mem_trans_en: 1; - volatile uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ - volatile uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ - volatile uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ - volatile uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ - volatile uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ - volatile uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ - volatile uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ - volatile uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ - volatile uint32_t reserved24: 8; + uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/ + uint32_t out_rst: 1; /*Set this bit to reset out link operations.*/ + uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset dma ahb fifo.*/ + uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/ + uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/ + uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out links.*/ + uint32_t out_auto_wrback: 1; /*when in link's length is 0 go on to use the next in link automatically.*/ + uint32_t out_no_restart_clr: 1; /*don't use*/ + uint32_t out_eof_mode: 1; /*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/ + uint32_t uart0_ce: 1; /*Set this bit to use UART to transmit or receive data.*/ + uint32_t uart1_ce: 1; /*Set this bit to use UART1 to transmit or receive data.*/ + uint32_t uart2_ce: 1; /*Set this bit to use UART2 to transmit or receive data.*/ + uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/ + uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/ + uint32_t out_data_burst_en: 1; /*Set this bit to enable DMA burst MODE*/ + uint32_t mem_trans_en: 1; + uint32_t seper_en: 1; /*Set this bit to use special char to separate the data frame.*/ + uint32_t head_en: 1; /*Set this bit to enable to use head packet before the data frame.*/ + uint32_t crc_rec_en: 1; /*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/ + uint32_t uart_idle_eof_en: 1; /*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/ + uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/ + uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/ + uint32_t clk_en: 1; /*Set this bit to enable clock-gating for read or write registers.*/ + uint32_t uart_rx_brk_eof_en: 1; /*Set this bit to enable to use brk char as the end of a data frame.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }conf0; union { struct { - volatile uint32_t rx_start_int_raw: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ - volatile uint32_t tx_start_int_raw: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ - volatile uint32_t rx_hung_int_raw: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ - volatile uint32_t tx_hung_int_raw: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ - volatile uint32_t in_done_int_raw: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ - volatile uint32_t in_suc_eof_int_raw: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ - volatile uint32_t in_err_eof_int_raw: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ - volatile uint32_t out_done_int_raw: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ - volatile uint32_t out_eof_int_raw: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ - volatile uint32_t in_dscr_err_int_raw: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ - volatile uint32_t out_dscr_err_int_raw: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ - volatile uint32_t in_dscr_empty_int_raw: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ - volatile uint32_t outlink_eof_err_int_raw: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ - volatile uint32_t out_total_eof_int_raw: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ - volatile uint32_t send_s_q_int_raw: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ - volatile uint32_t send_a_q_int_raw: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ - volatile uint32_t dma_infifo_full_wm_int_raw: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_start_int_raw: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ + uint32_t tx_start_int_raw: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ + uint32_t rx_hung_int_raw: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ + uint32_t tx_hung_int_raw: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ + uint32_t in_done_int_raw: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ + uint32_t in_suc_eof_int_raw: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ + uint32_t in_err_eof_int_raw: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ + uint32_t out_done_int_raw: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ + uint32_t out_eof_int_raw: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ + uint32_t in_dscr_err_int_raw: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t out_dscr_err_int_raw: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ + uint32_t in_dscr_empty_int_raw: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t outlink_eof_err_int_raw: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ + uint32_t out_total_eof_int_raw: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ + uint32_t send_s_q_int_raw: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t send_a_q_int_raw: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t dma_infifo_full_wm_int_raw: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_raw; union { struct { - volatile uint32_t rx_start_int_st: 1; - volatile uint32_t tx_start_int_st: 1; - volatile uint32_t rx_hung_int_st: 1; - volatile uint32_t tx_hung_int_st: 1; - volatile uint32_t in_done_int_st: 1; - volatile uint32_t in_suc_eof_int_st: 1; - volatile uint32_t in_err_eof_int_st: 1; - volatile uint32_t out_done_int_st: 1; - volatile uint32_t out_eof_int_st: 1; - volatile uint32_t in_dscr_err_int_st: 1; - volatile uint32_t out_dscr_err_int_st: 1; - volatile uint32_t in_dscr_empty_int_st: 1; - volatile uint32_t outlink_eof_err_int_st: 1; - volatile uint32_t out_total_eof_int_st: 1; - volatile uint32_t send_s_q_int_st: 1; - volatile uint32_t send_a_q_int_st: 1; - volatile uint32_t dma_infifo_full_wm_int_st: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_start_int_st: 1; + uint32_t tx_start_int_st: 1; + uint32_t rx_hung_int_st: 1; + uint32_t tx_hung_int_st: 1; + uint32_t in_done_int_st: 1; + uint32_t in_suc_eof_int_st: 1; + uint32_t in_err_eof_int_st: 1; + uint32_t out_done_int_st: 1; + uint32_t out_eof_int_st: 1; + uint32_t in_dscr_err_int_st: 1; + uint32_t out_dscr_err_int_st: 1; + uint32_t in_dscr_empty_int_st: 1; + uint32_t outlink_eof_err_int_st: 1; + uint32_t out_total_eof_int_st: 1; + uint32_t send_s_q_int_st: 1; + uint32_t send_a_q_int_st: 1; + uint32_t dma_infifo_full_wm_int_st: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_st; union { struct { - volatile uint32_t rx_start_int_ena: 1; - volatile uint32_t tx_start_int_ena: 1; - volatile uint32_t rx_hung_int_ena: 1; - volatile uint32_t tx_hung_int_ena: 1; - volatile uint32_t in_done_int_ena: 1; - volatile uint32_t in_suc_eof_int_ena: 1; - volatile uint32_t in_err_eof_int_ena: 1; - volatile uint32_t out_done_int_ena: 1; - volatile uint32_t out_eof_int_ena: 1; - volatile uint32_t in_dscr_err_int_ena: 1; - volatile uint32_t out_dscr_err_int_ena: 1; - volatile uint32_t in_dscr_empty_int_ena: 1; - volatile uint32_t outlink_eof_err_int_ena: 1; - volatile uint32_t out_total_eof_int_ena: 1; - volatile uint32_t send_s_q_int_ena: 1; - volatile uint32_t send_a_q_int_ena: 1; - volatile uint32_t dma_infifo_full_wm_int_ena: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_start_int_ena: 1; + uint32_t tx_start_int_ena: 1; + uint32_t rx_hung_int_ena: 1; + uint32_t tx_hung_int_ena: 1; + uint32_t in_done_int_ena: 1; + uint32_t in_suc_eof_int_ena: 1; + uint32_t in_err_eof_int_ena: 1; + uint32_t out_done_int_ena: 1; + uint32_t out_eof_int_ena: 1; + uint32_t in_dscr_err_int_ena: 1; + uint32_t out_dscr_err_int_ena: 1; + uint32_t in_dscr_empty_int_ena: 1; + uint32_t outlink_eof_err_int_ena: 1; + uint32_t out_total_eof_int_ena: 1; + uint32_t send_s_q_int_ena: 1; + uint32_t send_a_q_int_ena: 1; + uint32_t dma_infifo_full_wm_int_ena: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_ena; union { struct { - volatile uint32_t rx_start_int_clr: 1; - volatile uint32_t tx_start_int_clr: 1; - volatile uint32_t rx_hung_int_clr: 1; - volatile uint32_t tx_hung_int_clr: 1; - volatile uint32_t in_done_int_clr: 1; - volatile uint32_t in_suc_eof_int_clr: 1; - volatile uint32_t in_err_eof_int_clr: 1; - volatile uint32_t out_done_int_clr: 1; - volatile uint32_t out_eof_int_clr: 1; - volatile uint32_t in_dscr_err_int_clr: 1; - volatile uint32_t out_dscr_err_int_clr: 1; - volatile uint32_t in_dscr_empty_int_clr: 1; - volatile uint32_t outlink_eof_err_int_clr: 1; - volatile uint32_t out_total_eof_int_clr: 1; - volatile uint32_t send_s_q_int_clr: 1; - volatile uint32_t send_a_q_int_clr: 1; - volatile uint32_t dma_infifo_full_wm_int_clr: 1; - volatile uint32_t reserved17: 15; + uint32_t rx_start_int_clr: 1; + uint32_t tx_start_int_clr: 1; + uint32_t rx_hung_int_clr: 1; + uint32_t tx_hung_int_clr: 1; + uint32_t in_done_int_clr: 1; + uint32_t in_suc_eof_int_clr: 1; + uint32_t in_err_eof_int_clr: 1; + uint32_t out_done_int_clr: 1; + uint32_t out_eof_int_clr: 1; + uint32_t in_dscr_err_int_clr: 1; + uint32_t out_dscr_err_int_clr: 1; + uint32_t in_dscr_empty_int_clr: 1; + uint32_t outlink_eof_err_int_clr: 1; + uint32_t out_total_eof_int_clr: 1; + uint32_t send_s_q_int_clr: 1; + uint32_t send_a_q_int_clr: 1; + uint32_t dma_infifo_full_wm_int_clr: 1; + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }int_clr; union { struct { - volatile uint32_t out_full: 1; /*1:DMA out link descriptor's fifo is full.*/ - volatile uint32_t out_empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ - volatile uint32_t reserved2: 30; + uint32_t out_full: 1; /*1:DMA out link descriptor's fifo is full.*/ + uint32_t out_empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ + uint32_t reserved2: 30; }; - volatile uint32_t val; + uint32_t val; }dma_out_status; union { struct { - volatile uint32_t outfifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ - volatile uint32_t reserved9: 7; - volatile uint32_t outfifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ - volatile uint32_t reserved17: 15; + uint32_t outfifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ + uint32_t reserved9: 7; + uint32_t outfifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }dma_out_push; union { struct { - volatile uint32_t in_full: 1; - volatile uint32_t in_empty: 1; - volatile uint32_t reserved2: 2; - volatile uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ - volatile uint32_t reserved7: 25; + uint32_t in_full: 1; + uint32_t in_empty: 1; + uint32_t reserved2: 2; + uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ + uint32_t reserved7: 25; }; - volatile uint32_t val; + uint32_t val; }dma_in_status; union { struct { - volatile uint32_t infifo_rdata:12; /*This register stores the data pop from in link descriptor's fifo.*/ - volatile uint32_t reserved12: 4; - volatile uint32_t infifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ - volatile uint32_t reserved17: 15; + uint32_t infifo_rdata:12; /*This register stores the data pop from in link descriptor's fifo.*/ + uint32_t reserved12: 4; + uint32_t infifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ + uint32_t reserved17: 15; }; - volatile uint32_t val; + uint32_t val; }dma_in_pop; union { struct { - volatile uint32_t outlink_addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ - volatile uint32_t reserved20: 8; - volatile uint32_t outlink_stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ - volatile uint32_t outlink_start: 1; /*Set this bit to start dealing with the out link descriptors.*/ - volatile uint32_t outlink_restart: 1; /*Set this bit to mount on new out link descriptors*/ - volatile uint32_t outlink_park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ + uint32_t outlink_addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ + uint32_t reserved20: 8; + uint32_t outlink_stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ + uint32_t outlink_start: 1; /*Set this bit to start dealing with the out link descriptors.*/ + uint32_t outlink_restart: 1; /*Set this bit to mount on new out link descriptors*/ + uint32_t outlink_park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ }; - volatile uint32_t val; + uint32_t val; }dma_out_link; union { struct { - volatile uint32_t inlink_addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ - volatile uint32_t inlink_auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ - volatile uint32_t reserved21: 7; - volatile uint32_t inlink_stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ - volatile uint32_t inlink_start: 1; /*Set this bit to start dealing with the in link descriptors.*/ - volatile uint32_t inlink_restart: 1; /*Set this bit to mount on new in link descriptors*/ - volatile uint32_t inlink_park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ + uint32_t inlink_addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ + uint32_t inlink_auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ + uint32_t reserved21: 7; + uint32_t inlink_stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ + uint32_t inlink_start: 1; /*Set this bit to start dealing with the in link descriptors.*/ + uint32_t inlink_restart: 1; /*Set this bit to mount on new in link descriptors*/ + uint32_t inlink_park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ }; - volatile uint32_t val; + uint32_t val; }dma_in_link; union { struct { - volatile uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ - volatile uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ - volatile uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ - volatile uint32_t save_head: 1; /*Set this bit to save packet header .*/ - volatile uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ - volatile uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ - volatile uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ - volatile uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ - volatile uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ - volatile uint32_t dma_infifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ - volatile uint32_t reserved21: 11; + uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ + uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ + uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ + uint32_t save_head: 1; /*Set this bit to save packet header .*/ + uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ + uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ + uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ + uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ + uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ + uint32_t dma_infifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ + uint32_t reserved21: 11; }; - volatile uint32_t val; + uint32_t val; }conf1; - volatile uint32_t state0; /**/ - volatile uint32_t state1; /**/ - volatile uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ - volatile uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ - volatile uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ - volatile uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ + uint32_t state0; /**/ + uint32_t state1; /**/ + uint32_t dma_out_eof_des_addr; /*This register stores the address of out link description when eof bit in this descriptor is 1.*/ + uint32_t dma_in_suc_eof_des_addr; /*This register stores the address of in link descriptor when eof bit in this descriptor is 1.*/ + uint32_t dma_in_err_eof_des_addr; /*This register stores the address of in link descriptor when there are some errors in this descriptor.*/ + uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ union { struct { - volatile uint32_t ahb_testmode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ - volatile uint32_t reserved3: 1; - volatile uint32_t ahb_testaddr: 2; /*The two bits represent ahb bus address bit[20:19]*/ - volatile uint32_t reserved6: 26; + uint32_t ahb_testmode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ + uint32_t reserved3: 1; + uint32_t ahb_testaddr: 2; /*The two bits represent ahb bus address bit[20:19]*/ + uint32_t reserved6: 26; }; - volatile uint32_t val; + uint32_t val; }ahb_test; - volatile uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ - volatile uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ - volatile uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ - volatile uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ - volatile uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ - volatile uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ + uint32_t dma_in_dscr; /*The content of current in link descriptor's third dword*/ + uint32_t dma_in_dscr_bf0; /*The content of current in link descriptor's first dword*/ + uint32_t dma_in_dscr_bf1; /*The content of current in link descriptor's second dword*/ + uint32_t dma_out_dscr; /*The content of current out link descriptor's third dword*/ + uint32_t dma_out_dscr_bf0; /*The content of current out link descriptor's first dword*/ + uint32_t dma_out_dscr_bf1; /*The content of current out link descriptor's second dword*/ union { struct { - volatile uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ - volatile uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ - volatile uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ - volatile uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ - volatile uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ - volatile uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ - volatile uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ - volatile uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ - volatile uint32_t reserved8: 24; + uint32_t tx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char decode when DMA receives data.*/ + uint32_t tx_db_esc_en: 1; /*Set this bit to enable 0xdb char decode when DMA receives data.*/ + uint32_t tx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 decode when DMA receives data.*/ + uint32_t tx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 decode when DMA receives data.*/ + uint32_t rx_c0_esc_en: 1; /*Set this bit to enable 0xc0 char replace when DMA sends data.*/ + uint32_t rx_db_esc_en: 1; /*Set this bit to enable 0xdb char replace when DMA sends data.*/ + uint32_t rx_11_esc_en: 1; /*Set this bit to enable flow control char 0x11 replace when DMA sends data.*/ + uint32_t rx_13_esc_en: 1; /*Set this bit to enable flow control char 0x13 replace when DMA sends data.*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }escape_conf; union { struct { - volatile uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ - volatile uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ - volatile uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ - volatile uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ - volatile uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ - volatile uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ - volatile uint32_t reserved24: 8; + uint32_t txfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/ + uint32_t txfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/ + uint32_t txfifo_timeout_ena: 1; /*The enable bit for tx fifo receive data timeout*/ + uint32_t rxfifo_timeout: 8; /*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/ + uint32_t rxfifo_timeout_shift: 3; /*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/ + uint32_t rxfifo_timeout_ena: 1; /*This is the enable bit for DMA send data timeout*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }hung_conf; - volatile uint32_t ack_num; /**/ - volatile uint32_t rx_head; /*This register stores the packet header received by DMA*/ + uint32_t ack_num; /**/ + uint32_t rx_head; /*This register stores the packet header received by DMA*/ union { struct { - volatile uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ - volatile uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ - volatile uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ - volatile uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ - volatile uint32_t reserved8: 24; + uint32_t single_send_num: 3; /*The bits are used to choose which short packet*/ + uint32_t single_send_en: 1; /*Set this bit to enable send a short packet*/ + uint32_t always_send_num: 3; /*The bits are used to choose which short packet*/ + uint32_t always_send_en: 1; /*Set this bit to enable continuously send the same short packet*/ + uint32_t reserved8: 24; }; - volatile uint32_t val; + uint32_t val; }quick_sent; struct{ - volatile uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ + uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ }q_data[7]; union { struct { - volatile uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ - volatile uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ - volatile uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ - volatile uint32_t reserved24: 8; + uint32_t seper_char: 8; /*This register stores the separator char separator char is used to separate the data frame.*/ + uint32_t seper_esc_char0: 8; /*This register stores the first char used to replace separator char in data.*/ + uint32_t seper_esc_char1: 8; /*This register stores the second char used to replace separator char in data . 0xdc 0xdb replace 0xc0 by default.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }esc_conf0; union { struct { - volatile uint32_t esc_seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ - volatile uint32_t esc_seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ - volatile uint32_t esc_seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ - volatile uint32_t reserved24: 8; + uint32_t esc_seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ + uint32_t esc_seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ + uint32_t esc_seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }esc_conf1; union { struct { - volatile uint32_t esc_seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ - volatile uint32_t esc_seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ - volatile uint32_t esc_seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ - volatile uint32_t reserved24: 8; + uint32_t esc_seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ + uint32_t esc_seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ + uint32_t esc_seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }esc_conf2; union { struct { - volatile uint32_t esc_seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ - volatile uint32_t esc_seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ - volatile uint32_t esc_seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ - volatile uint32_t reserved24: 8; + uint32_t esc_seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ + uint32_t esc_seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ + uint32_t esc_seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ + uint32_t reserved24: 8; }; - volatile uint32_t val; + uint32_t val; }esc_conf3; union { struct { - volatile uint32_t pkt_thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ - volatile uint32_t reserved13:19; + uint32_t pkt_thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ + uint32_t reserved13:19; }; - volatile uint32_t val; + uint32_t val; }pkt_thres; - volatile uint32_t reserved_c4; - volatile uint32_t reserved_c8; - volatile uint32_t reserved_cc; - volatile uint32_t reserved_d0; - volatile uint32_t reserved_d4; - volatile uint32_t reserved_d8; - volatile uint32_t reserved_dc; - volatile uint32_t reserved_e0; - volatile uint32_t reserved_e4; - volatile uint32_t reserved_e8; - volatile uint32_t reserved_ec; - volatile uint32_t reserved_f0; - volatile uint32_t reserved_f4; - volatile uint32_t reserved_f8; - volatile uint32_t date; /*version information*/ + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /*version information*/ } uhci_dev_t; -extern volatile uhci_dev_t UHCI0; -extern volatile uhci_dev_t UHCI1; +extern uhci_dev_t UHCI0; +extern uhci_dev_t UHCI1; #endif /* _SOC_UHCI_STRUCT_H_ */ From 4c74ec9415bdcbc704064a9fef832c256b110ab5 Mon Sep 17 00:00:00 2001 From: liuzhifu Date: Sun, 18 Sep 2016 15:35:42 +0800 Subject: [PATCH 43/57] freertos: fix memory debug macro issue Define configENABLE_MEMORY_DEBUG according to CONFIG_ENABLE_MEMORY_DEBUG --- components/freertos/include/freertos/FreeRTOSConfig.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/components/freertos/include/freertos/FreeRTOSConfig.h b/components/freertos/include/freertos/FreeRTOSConfig.h index 95bf1e103..663f015ac 100644 --- a/components/freertos/include/freertos/FreeRTOSConfig.h +++ b/components/freertos/include/freertos/FreeRTOSConfig.h @@ -222,7 +222,9 @@ #define INCLUDE_vTaskDelay 1 #define INCLUDE_uxTaskGetStackHighWaterMark 1 -#ifndef configENABLE_MEMORY_DEBUG +#if CONFIG_ENABLE_MEMORY_DEBUG +#define configENABLE_MEMORY_DEBUG 1 +#else #define configENABLE_MEMORY_DEBUG 0 #endif From 4d4c6a36942a0c730940a15091fd91cd7a580010 Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Sun, 18 Sep 2016 16:43:48 +0800 Subject: [PATCH 44/57] Enable SO_REUSEADDR in LWIP --- components/lwip/include/lwip/port/lwipopts.h | 2 +- components/mbedtls/port/net.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/lwip/include/lwip/port/lwipopts.h b/components/lwip/include/lwip/port/lwipopts.h index 65b3889f0..99520f1cd 100755 --- a/components/lwip/include/lwip/port/lwipopts.h +++ b/components/lwip/include/lwip/port/lwipopts.h @@ -405,7 +405,7 @@ extern unsigned char misc_prof_get_tcp_snd_buf(void); /** * SO_REUSE==1: Enable SO_REUSEADDR option. */ -#define SO_REUSE 0 +#define SO_REUSE 1 /* ---------------------------------------- diff --git a/components/mbedtls/port/net.c b/components/mbedtls/port/net.c index 482a11f97..45aa4b2de 100644 --- a/components/mbedtls/port/net.c +++ b/components/mbedtls/port/net.c @@ -147,7 +147,7 @@ int mbedtls_net_bind( mbedtls_net_context *ctx, const char *bind_ip, const char /*SO_REUSEADDR option dafault is disable in source code(lwip)*/ #if SO_REUSE - n = 1; + int n = 1; if ( setsockopt( ctx->fd, SOL_SOCKET, SO_REUSEADDR, (const char *) &n, sizeof( n ) ) != 0 ) { close( ctx->fd ); From 94bcb14bcce4014e57521af936cb920ae80fdd4c Mon Sep 17 00:00:00 2001 From: Wangjialin Date: Sun, 18 Sep 2016 19:05:37 +0800 Subject: [PATCH 45/57] remove prefix and postfix --- components/esp32/include/soc/gpio_sd_struct.h | 10 +- components/esp32/include/soc/gpio_struct.h | 90 +++--- components/esp32/include/soc/i2c_struct.h | 174 ++++++------ components/esp32/include/soc/i2s_struct.h | 260 ++++++++--------- components/esp32/include/soc/ledc_struct.h | 199 +++++++------ components/esp32/include/soc/pcnt_struct.h | 72 ++--- components/esp32/include/soc/rmt_struct.h | 264 +++++++++--------- components/esp32/include/soc/spi_struct.h | 220 +++++++-------- .../esp32/include/soc/timer_group_struct.h | 120 ++++---- components/esp32/include/soc/uart_struct.h | 214 +++++++------- components/esp32/include/soc/uhci_struct.h | 250 ++++++++--------- 11 files changed, 936 insertions(+), 937 deletions(-) diff --git a/components/esp32/include/soc/gpio_sd_struct.h b/components/esp32/include/soc/gpio_sd_struct.h index d06ad2e9a..a4ca24fc3 100644 --- a/components/esp32/include/soc/gpio_sd_struct.h +++ b/components/esp32/include/soc/gpio_sd_struct.h @@ -16,33 +16,33 @@ typedef volatile struct { union { struct { - uint32_t sd_in: 8; + uint32_t duty: 8; uint32_t prescale: 8; uint32_t reserved16: 16; }; uint32_t val; - }sigmadelta[8]; + }channel[8]; union { struct { uint32_t reserved0: 31; uint32_t clk_en: 1; }; uint32_t val; - }sigmadelta_cg; + }cg; union { struct { uint32_t reserved0: 31; uint32_t spi_swap: 1; }; uint32_t val; - }sigmadelta_misc; + }misc; union { struct { uint32_t date: 28; uint32_t reserved28: 4; }; uint32_t val; - }sigmadelta_version; + }version; } gpio_sd_dev_t; extern gpio_sd_dev_t SIGMADELTA; #endif /* _SOC_GPIO_SD_STRUCT_H_ */ diff --git a/components/esp32/include/soc/gpio_struct.h b/components/esp32/include/soc/gpio_struct.h index 080d638e9..649a17ff0 100644 --- a/components/esp32/include/soc/gpio_struct.h +++ b/components/esp32/include/soc/gpio_struct.h @@ -20,28 +20,28 @@ typedef volatile struct { uint32_t out_w1tc; /*GPIO0~31 output value write 1 to clear*/ union { struct { - uint32_t out_data: 8; /*GPIO32~39 output value*/ + uint32_t data: 8; /*GPIO32~39 output value*/ uint32_t reserved8: 24; }; uint32_t val; }out1; union { struct { - uint32_t out_data: 8; /*GPIO32~39 output value write 1 to set*/ + uint32_t data: 8; /*GPIO32~39 output value write 1 to set*/ uint32_t reserved8: 24; }; uint32_t val; }out1_w1ts; union { struct { - uint32_t out_data: 8; /*GPIO32~39 output value write 1 to clear*/ + uint32_t data: 8; /*GPIO32~39 output value write 1 to clear*/ uint32_t reserved8: 24; }; uint32_t val; }out1_w1tc; union { struct { - uint32_t sdio_sel: 8; /*SDIO PADS on/off control from outside*/ + uint32_t sel: 8; /*SDIO PADS on/off control from outside*/ uint32_t reserved8: 24; }; uint32_t val; @@ -51,21 +51,21 @@ typedef volatile struct { uint32_t enable_w1tc; /*GPIO0~31 output enable write 1 to clear*/ union { struct { - uint32_t enable_data: 8; /*GPIO32~39 output enable*/ + uint32_t data: 8; /*GPIO32~39 output enable*/ uint32_t reserved8: 24; }; uint32_t val; }enable1; union { struct { - uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to set*/ + uint32_t data: 8; /*GPIO32~39 output enable write 1 to set*/ uint32_t reserved8: 24; }; uint32_t val; }enable1_w1ts; union { struct { - uint32_t enable_data: 8; /*GPIO32~39 output enable write 1 to clear*/ + uint32_t data: 8; /*GPIO32~39 output enable write 1 to clear*/ uint32_t reserved8: 24; }; uint32_t val; @@ -80,8 +80,8 @@ typedef volatile struct { uint32_t in; /*GPIO0~31 input value*/ union { struct { - uint32_t in_data: 8; /*GPIO32~39 input value*/ - uint32_t reserved8: 24; + uint32_t data: 8; /*GPIO32~39 input value*/ + uint32_t reserved8: 24; }; uint32_t val; }in1; @@ -90,22 +90,22 @@ typedef volatile struct { uint32_t status_w1tc; /*GPIO0~31 interrupt status write 1 to clear*/ union { struct { - uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status*/ - uint32_t reserved8: 24; + uint32_t intr_st: 8; /*GPIO32~39 interrupt status*/ + uint32_t reserved8: 24; }; uint32_t val; }status1; union { struct { - uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to set*/ - uint32_t reserved8: 24; + uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to set*/ + uint32_t reserved8: 24; }; uint32_t val; }status1_w1ts; union { struct { - uint32_t status_interrupt: 8; /*GPIO32~39 interrupt status write 1 to clear*/ - uint32_t reserved8: 24; + uint32_t intr_st: 8; /*GPIO32~39 interrupt status write 1 to clear*/ + uint32_t reserved8: 24; }; uint32_t val; }status1_w1tc; @@ -117,85 +117,85 @@ typedef volatile struct { uint32_t cpusdio_int; /*SDIO's extent GPIO0~31 interrupt*/ union { struct { - uint32_t appcpu_int: 8; /*GPIO32~39 APP CPU interrupt status*/ + uint32_t intr: 8; /*GPIO32~39 APP CPU interrupt status*/ uint32_t reserved8: 24; }; uint32_t val; }acpu_int1; union { struct { - uint32_t appcpu_nmi_int: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ - uint32_t reserved8: 24; + uint32_t intr: 8; /*GPIO32~39 APP CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; }; uint32_t val; }acpu_nmi_int1; union { struct { - uint32_t procpu_int: 8; /*GPIO32~39 PRO CPU interrupt status*/ + uint32_t intr: 8; /*GPIO32~39 PRO CPU interrupt status*/ uint32_t reserved8: 24; }; uint32_t val; }pcpu_int1; union { struct { - uint32_t procpu_nmi_int: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ - uint32_t reserved8: 24; + uint32_t intr: 8; /*GPIO32~39 PRO CPU non-maskable interrupt status*/ + uint32_t reserved8: 24; }; uint32_t val; }pcpu_nmi_int1; union { struct { - uint32_t sdio_int: 8; /*SDIO's extent GPIO32~39 interrupt*/ + uint32_t intr: 8; /*SDIO's extent GPIO32~39 interrupt*/ uint32_t reserved8: 24; }; uint32_t val; }cpusdio_int1; union { struct { - uint32_t reserved0: 2; - uint32_t pin_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ - uint32_t reserved3: 4; - uint32_t pin_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ - uint32_t pin_wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ - uint32_t pin_config: 2; /*NA*/ - uint32_t pin_int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ - uint32_t reserved18: 14; + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*GPIO wake up enable only available in light sleep*/ + uint32_t config: 2; /*NA*/ + uint32_t int_ena: 5; /*bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable*/ + uint32_t reserved18: 14; }; uint32_t val; }pin[40]; union { struct { - uint32_t cali_rtc_max:10; + uint32_t rtc_max: 10; uint32_t reserved10: 21; - uint32_t cali_start: 1; + uint32_t start: 1; }; uint32_t val; }cali_conf; union { struct { - uint32_t cali_value_sync2:20; - uint32_t reserved20: 10; - uint32_t cali_rdy_real: 1; - uint32_t cali_rdy_sync2: 1; + uint32_t value_sync2: 20; + uint32_t reserved20: 10; + uint32_t rdy_real: 1; + uint32_t rdy_sync2: 1; }; uint32_t val; }cali_data; union { struct { - uint32_t func_in_sel: 6; /*select one of the 256 inputs*/ - uint32_t func_in_inv_sel: 1; /*revert the value of the input if you want to revert please set the value to 1*/ - uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ - uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ + uint32_t func_sel: 6; /*select one of the 256 inputs*/ + uint32_t sig_in_inv: 1; /*revert the value of the input if you want to revert please set the value to 1*/ + uint32_t sig_in_sel: 1; /*if the slow signal bypass the io matrix or not if you want setting the value to 1*/ + uint32_t reserved8: 24; /*The 256 registers below are selection control for 256 input signals connected to GPIO matrix's 40 GPIO input if GPIO_FUNCx_IN_SEL is set to n(0<=n<40): it means GPIOn input is used for input signal x if GPIO_FUNCx_IN_SEL is set to 0x38: the input signal x is set to 1 if GPIO_FUNCx_IN_SEL is set to 0x30: the input signal x is set to 0*/ }; uint32_t val; }func_in_sel_cfg[256]; union { struct { - uint32_t func_out_sel: 9; /*select one of the 256 output to 40 GPIO*/ - uint32_t func_out_inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ - uint32_t func_oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ - uint32_t func_oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ - uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ + uint32_t func_sel: 9; /*select one of the 256 output to 40 GPIO*/ + uint32_t inv_sel: 1; /*invert the output value if you want to revert the output value setting the value to 1*/ + uint32_t oen_sel: 1; /*weather using the logical oen signal or not using the value setting by the register*/ + uint32_t oen_inv_sel: 1; /*invert the output enable value if you want to revert the output enable value setting the value to 1*/ + uint32_t reserved12: 20; /*The 40 registers below are selection control for 40 GPIO output if GPIO_FUNCx_OUT_SEL is set to n(0<=n<256): it means GPIOn input is used for output signal x if GPIO_FUNCx_OUT_INV_SEL is set to 1 the output signal x is set to ~value. if GPIO_FUNC0_OUT_SEL is 256 or GPIO_FUNC0_OEN_SEL is 1 using GPIO_ENABLE_DATA[x] for the enable value else using the signal enable*/ }; uint32_t val; }func_out_sel_cfg[40]; diff --git a/components/esp32/include/soc/i2c_struct.h b/components/esp32/include/soc/i2c_struct.h index 99c0e9743..d6917e7fd 100644 --- a/components/esp32/include/soc/i2c_struct.h +++ b/components/esp32/include/soc/i2c_struct.h @@ -58,29 +58,29 @@ typedef volatile struct { }status_reg; union { struct { - uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/ + uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/ uint32_t reserved20:12; }; uint32_t val; }timeout; union { struct { - uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ - uint32_t reserved15: 16; - uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/ + uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/ + uint32_t reserved15: 16; + uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/ }; uint32_t val; }slave_addr; union { struct { - uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ - uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ - uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ - uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ + uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/ + uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/ + uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/ uint32_t reserved20: 12; }; uint32_t val; - }rx_fifo_st; + }fifo_st; union { struct { uint32_t rx_fifo_full_thrhd: 5; @@ -97,150 +97,150 @@ typedef volatile struct { }fifo_conf; union { struct { - uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ + uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/ uint32_t reserved8: 24; }; uint32_t val; }fifo_data; union { struct { - uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ - uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ - uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ - uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ - uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ - uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ - uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ - uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ - uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ - uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ - uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ - uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ - uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ - uint32_t reserved13: 19; + uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/ + uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/ + uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/ + uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/ + uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/ + uint32_t reserved13: 19; }; uint32_t val; }int_raw; union { struct { - uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ - uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ - uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ - uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/ - uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ - uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ - uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ - uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ - uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/ - uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/ - uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/ - uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ - uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ - uint32_t reserved13: 19; + uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/ + uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/ + uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; }; uint32_t val; }int_clr; union { struct { - uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ - uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ - uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ - uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/ - uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ - uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/ - uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/ - uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/ - uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/ - uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/ - uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/ - uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/ - uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/ - uint32_t reserved13: 19; + uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; }; uint32_t val; }int_ena; union { struct { - uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ - uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ - uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ - uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/ - uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ - uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ - uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ - uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ - uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/ - uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/ - uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/ - uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ - uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ - uint32_t reserved13: 19; + uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/ + uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/ + uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/ + uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/ + uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/ + uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/ + uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/ + uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/ + uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/ + uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/ + uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/ + uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/ + uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/ + uint32_t reserved13: 19; }; uint32_t val; }int_status; union { struct { - uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ - uint32_t reserved10: 22; + uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/ + uint32_t reserved10: 22; }; uint32_t val; }sda_hold; union { struct { - uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ - uint32_t reserved10: 22; + uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/ + uint32_t reserved10: 22; }; uint32_t val; }sda_sample; union { struct { - uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/ - uint32_t reserved14: 18; + uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/ + uint32_t reserved14: 18; }; uint32_t val; }scl_high_period; uint32_t reserved_3c; union { struct { - uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ - uint32_t reserved10: 22; + uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/ + uint32_t reserved10: 22; }; uint32_t val; }scl_start_hold; union { struct { - uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ - uint32_t reserved10: 22; + uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/ + uint32_t reserved10: 22; }; uint32_t val; }scl_rstart_setup; union { struct { - uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ - uint32_t reserved14: 18; + uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/ + uint32_t reserved14: 18; }; uint32_t val; }scl_stop_hold; union { struct { - uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ - uint32_t reserved10: 22; + uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/ + uint32_t reserved10: 22; }; uint32_t val; }scl_stop_setup; union { struct { - uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ - uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/ - uint32_t reserved4: 28; + uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t en: 1; /*This is the filter enable bit for SCL.*/ + uint32_t reserved4: 28; }; uint32_t val; }scl_filter_cfg; union { struct { - uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ - uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/ - uint32_t reserved4: 28; + uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/ + uint32_t en: 1; /*This is the filter enable bit for SDA.*/ + uint32_t reserved4: 28; }; uint32_t val; }sda_filter_cfg; @@ -252,7 +252,7 @@ typedef volatile struct { uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ uint32_t reserved14: 17; - uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ + uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/ }; uint32_t val; }command[16]; diff --git a/components/esp32/include/soc/i2s_struct.h b/components/esp32/include/soc/i2s_struct.h index 0bf990cd6..e565c6b76 100644 --- a/components/esp32/include/soc/i2s_struct.h +++ b/components/esp32/include/soc/i2s_struct.h @@ -43,93 +43,93 @@ typedef volatile struct { }conf; union { struct { - uint32_t rx_take_data_int_raw: 1; - uint32_t tx_put_data_int_raw: 1; - uint32_t rx_wfull_int_raw: 1; - uint32_t rx_rempty_int_raw: 1; - uint32_t tx_wfull_int_raw: 1; - uint32_t tx_rempty_int_raw: 1; - uint32_t rx_hung_int_raw: 1; - uint32_t tx_hung_int_raw: 1; - uint32_t in_done_int_raw: 1; - uint32_t in_suc_eof_int_raw: 1; - uint32_t in_err_eof_int_raw: 1; - uint32_t out_done_int_raw: 1; - uint32_t out_eof_int_raw: 1; - uint32_t in_dscr_err_int_raw: 1; - uint32_t out_dscr_err_int_raw: 1; - uint32_t in_dscr_empty_int_raw: 1; - uint32_t out_total_eof_int_raw: 1; - uint32_t reserved17: 15; + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_raw; union { struct { - uint32_t rx_take_data_int_st: 1; - uint32_t tx_put_data_int_st: 1; - uint32_t rx_wfull_int_st: 1; - uint32_t rx_rempty_int_st: 1; - uint32_t tx_wfull_int_st: 1; - uint32_t tx_rempty_int_st: 1; - uint32_t rx_hung_int_st: 1; - uint32_t tx_hung_int_st: 1; - uint32_t in_done_int_st: 1; - uint32_t in_suc_eof_int_st: 1; - uint32_t in_err_eof_int_st: 1; - uint32_t out_done_int_st: 1; - uint32_t out_eof_int_st: 1; - uint32_t in_dscr_err_int_st: 1; - uint32_t out_dscr_err_int_st: 1; - uint32_t in_dscr_empty_int_st: 1; - uint32_t out_total_eof_int_st: 1; - uint32_t reserved17: 15; + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_st; union { struct { - uint32_t rx_take_data_int_ena: 1; - uint32_t tx_put_data_int_ena: 1; - uint32_t rx_wfull_int_ena: 1; - uint32_t rx_rempty_int_ena: 1; - uint32_t tx_wfull_int_ena: 1; - uint32_t tx_rempty_int_ena: 1; - uint32_t rx_hung_int_ena: 1; - uint32_t tx_hung_int_ena: 1; - uint32_t in_done_int_ena: 1; - uint32_t in_suc_eof_int_ena: 1; - uint32_t in_err_eof_int_ena: 1; - uint32_t out_done_int_ena: 1; - uint32_t out_eof_int_ena: 1; - uint32_t in_dscr_err_int_ena: 1; - uint32_t out_dscr_err_int_ena: 1; - uint32_t in_dscr_empty_int_ena: 1; - uint32_t out_total_eof_int_ena: 1; - uint32_t reserved17: 15; + uint32_t rx_take_data: 1; + uint32_t tx_put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_ena; union { struct { - uint32_t take_data_int_clr: 1; - uint32_t put_data_int_clr: 1; - uint32_t rx_wfull_int_clr: 1; - uint32_t rx_rempty_int_clr: 1; - uint32_t tx_wfull_int_clr: 1; - uint32_t tx_rempty_int_clr: 1; - uint32_t rx_hung_int_clr: 1; - uint32_t tx_hung_int_clr: 1; - uint32_t in_done_int_clr: 1; - uint32_t in_suc_eof_int_clr: 1; - uint32_t in_err_eof_int_clr: 1; - uint32_t out_done_int_clr: 1; - uint32_t out_eof_int_clr: 1; - uint32_t in_dscr_err_int_clr: 1; - uint32_t out_dscr_err_int_clr: 1; - uint32_t in_dscr_empty_int_clr: 1; - uint32_t out_total_eof_int_clr: 1; - uint32_t reserved17: 15; + uint32_t take_data: 1; + uint32_t put_data: 1; + uint32_t rx_wfull: 1; + uint32_t rx_rempty: 1; + uint32_t tx_wfull: 1; + uint32_t tx_rempty: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t out_total_eof: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_clr; @@ -178,23 +178,23 @@ typedef volatile struct { }conf_chan; union { struct { - uint32_t outlink_addr: 20; - uint32_t reserved20: 8; - uint32_t outlink_stop: 1; - uint32_t outlink_start: 1; - uint32_t outlink_restart: 1; - uint32_t outlink_park: 1; + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; }; uint32_t val; }out_link; union { struct { - uint32_t inlink_addr: 20; - uint32_t reserved20: 8; - uint32_t inlink_stop: 1; - uint32_t inlink_start: 1; - uint32_t inlink_restart: 1; - uint32_t inlink_park: 1; + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; }; uint32_t val; }in_link; @@ -203,10 +203,10 @@ typedef volatile struct { uint32_t out_eof_bfr_des_addr; union { struct { - uint32_t ahb_testmode: 3; - uint32_t reserved3: 1; - uint32_t ahb_testaddr: 2; - uint32_t reserved6: 26; + uint32_t mode: 3; + uint32_t reserved3: 1; + uint32_t addr: 2; + uint32_t reserved6: 26; }; uint32_t val; }ahb_test; @@ -238,19 +238,19 @@ typedef volatile struct { }lc_conf; union { struct { - uint32_t out_fifo_wdata: 9; - uint32_t reserved9: 7; - uint32_t out_fifo_push: 1; - uint32_t reserved17: 15; + uint32_t wdata: 9; + uint32_t reserved9: 7; + uint32_t push: 1; + uint32_t reserved17: 15; }; uint32_t val; }out_fifo_push; union { struct { - uint32_t in_fifo_rdata:12; - uint32_t reserved12: 4; - uint32_t in_fifo_pop: 1; - uint32_t reserved17: 15; + uint32_t rdata: 12; + uint32_t reserved12: 4; + uint32_t pop: 1; + uint32_t reserved17: 15; }; uint32_t val; }in_fifo_pop; @@ -258,10 +258,10 @@ typedef volatile struct { uint32_t lc_state1; union { struct { - uint32_t lc_fifo_timeout: 8; - uint32_t lc_fifo_timeout_shift: 3; - uint32_t lc_fifo_timeout_ena: 1; - uint32_t reserved12: 20; + uint32_t fifo_timeout: 8; + uint32_t fifo_timeout_shift: 3; + uint32_t fifo_timeout_ena: 1; + uint32_t reserved12: 20; }; uint32_t val; }lc_hung_conf; @@ -269,15 +269,15 @@ typedef volatile struct { uint32_t reserved_7c; union { struct { - uint32_t cvsd_y_max:16; - uint32_t cvsd_y_min:16; + uint32_t y_max:16; + uint32_t y_min:16; }; uint32_t val; }cvsd_conf0; union { struct { - uint32_t cvsd_sigma_max:16; - uint32_t cvsd_sigma_min:16; + uint32_t sigma_max:16; + uint32_t sigma_min:16; }; uint32_t val; }cvsd_conf1; @@ -323,23 +323,23 @@ typedef volatile struct { }plc_conf2; union { struct { - uint32_t esco_en: 1; - uint32_t esco_chan_mod: 1; - uint32_t esco_cvsd_dec_pack_err: 1; - uint32_t esco_cvsd_pack_len_8k: 5; - uint32_t esco_cvsd_inf_en: 1; - uint32_t cvsd_dec_start: 1; - uint32_t cvsd_dec_reset: 1; - uint32_t plc_en: 1; - uint32_t plc2dma_en: 1; - uint32_t reserved13: 19; + uint32_t en: 1; + uint32_t chan_mod: 1; + uint32_t cvsd_dec_pack_err: 1; + uint32_t cvsd_pack_len_8k: 5; + uint32_t cvsd_inf_en: 1; + uint32_t cvsd_dec_start: 1; + uint32_t cvsd_dec_reset: 1; + uint32_t plc_en: 1; + uint32_t plc2dma_en: 1; + uint32_t reserved13: 19; }; uint32_t val; }esco_conf0; union { struct { - uint32_t sco_with_en: 1; - uint32_t sco_no_en: 1; + uint32_t with_en: 1; + uint32_t no_en: 1; uint32_t cvsd_enc_start: 1; uint32_t cvsd_enc_reset: 1; uint32_t reserved4: 28; @@ -388,7 +388,7 @@ typedef volatile struct { uint32_t clkm_div_b: 6; uint32_t clkm_div_a: 6; uint32_t clk_en: 1; - uint32_t clka_ena: 1; + uint32_t clka_en: 1; uint32_t reserved22: 10; }; uint32_t val; @@ -405,19 +405,19 @@ typedef volatile struct { }sample_rate_conf; union { struct { - uint32_t tx_pdm_en: 1; - uint32_t rx_pdm_en: 1; - uint32_t pcm2pdm_conv_en: 1; - uint32_t pdm2pcm_conv_en: 1; - uint32_t tx_pdm_sinc_osr2: 4; - uint32_t tx_pdm_prescale: 8; - uint32_t tx_pdm_hp_in_shift: 2; - uint32_t tx_pdm_lp_in_shift: 2; - uint32_t tx_pdm_sinc_in_shift: 2; - uint32_t tx_pdm_sigmadelta_in_shift: 2; - uint32_t rx_pdm_sinc_dsr_16_en: 1; - uint32_t tx_pdm_hp_bypass: 1; - uint32_t reserved26: 6; + uint32_t tx_pdm_en: 1; + uint32_t rx_pdm_en: 1; + uint32_t pcm2pdm_conv_en: 1; + uint32_t pdm2pcm_conv_en: 1; + uint32_t tx_sinc_osr2: 4; + uint32_t tx_prescale: 8; + uint32_t tx_hp_in_shift: 2; + uint32_t tx_lp_in_shift: 2; + uint32_t tx_sinc_in_shift: 2; + uint32_t tx_sigmadelta_in_shift: 2; + uint32_t rx_sinc_dsr_16_en: 1; + uint32_t txhp_bypass: 1; + uint32_t reserved26: 6; }; uint32_t val; }pdm_conf; diff --git a/components/esp32/include/soc/ledc_struct.h b/components/esp32/include/soc/ledc_struct.h index 2eb316b95..26ddf6867 100644 --- a/components/esp32/include/soc/ledc_struct.h +++ b/components/esp32/include/soc/ledc_struct.h @@ -143,121 +143,120 @@ typedef volatile struct { }low_speed_timer[4]; union { struct { - uint32_t hstimer0_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ - uint32_t hstimer1_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ - uint32_t hstimer2_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ - uint32_t hstimer3_ovf_int_raw: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ - uint32_t lstimer0_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ - uint32_t lstimer1_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ - uint32_t lstimer2_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ - uint32_t lstimer3_ovf_int_raw: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ - uint32_t duty_chng_end_hsch0_int_raw: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ - uint32_t duty_chng_end_hsch1_int_raw: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ - uint32_t duty_chng_end_hsch2_int_raw: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ - uint32_t duty_chng_end_hsch3_int_raw: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ - uint32_t duty_chng_end_hsch4_int_raw: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ - uint32_t duty_chng_end_hsch5_int_raw: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ - uint32_t duty_chng_end_hsch6_int_raw: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ - uint32_t duty_chng_end_hsch7_int_raw: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ - uint32_t duty_chng_end_lsch0_int_raw: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ - uint32_t duty_chng_end_lsch1_int_raw: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ - uint32_t duty_chng_end_lsch2_int_raw: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ - uint32_t duty_chng_end_lsch3_int_raw: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ - uint32_t duty_chng_end_lsch4_int_raw: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ - uint32_t duty_chng_end_lsch5_int_raw: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ - uint32_t duty_chng_end_lsch6_int_raw: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ - uint32_t duty_chng_end_lsch7_int_raw: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ - uint32_t reserved24: 8; + uint32_t hstimer0_ovf: 1; /*The interrupt raw bit for high speed channel0 counter overflow.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt raw bit for high speed channel3 counter overflow.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt raw bit for low speed channel0 counter overflow.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt raw bit for low speed channel1 counter overflow.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt raw bit for low speed channel2 counter overflow.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt raw bit for low speed channel3 counter overflow.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt raw bit for high speed channel 0 duty change done.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt raw bit for high speed channel 1 duty change done.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt raw bit for high speed channel 4 duty change done.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt raw bit for high speed channel 5 duty change done.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt raw bit for high speed channel 6 duty change done.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt raw bit for high speed channel 7 duty change done.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt raw bit for low speed channel 0 duty change done.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt raw bit for low speed channel 1 duty change done.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt raw bit for low speed channel 2 duty change done.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt raw bit for low speed channel 5 duty change done.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt raw bit for low speed channel 6 duty change done.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt raw bit for low speed channel 7 duty change done.*/ + uint32_t reserved24: 8; }; uint32_t val; }int_raw; union { struct { - uint32_t hstimer0_ovf_int_st: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ - uint32_t hstimer1_ovf_int_st: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ - uint32_t hstimer2_ovf_int_st: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ - uint32_t hstimer3_ovf_int_st: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ - uint32_t lstimer0_ovf_int_st: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ - uint32_t lstimer1_ovf_int_st: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ - uint32_t lstimer2_ovf_int_st: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ - uint32_t lstimer3_ovf_int_st: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ - uint32_t duty_chng_end_hsch0_int_st: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ - uint32_t duty_chng_end_hsch1_int_st: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ - uint32_t duty_chng_end_hsch2_int_st: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ - uint32_t duty_chng_end_hsch3_int_st: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ - uint32_t duty_chng_end_hsch4_int_st: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ - uint32_t duty_chng_end_hsch5_int_st: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ - uint32_t duty_chng_end_hsch6_int_st: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ - uint32_t duty_chng_end_hsch7_int_st: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ - uint32_t duty_chng_end_lsch0_int_st: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ - uint32_t duty_chng_end_lsch1_int_st: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ - uint32_t duty_chng_end_lsch2_int_st: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ - uint32_t duty_chng_end_lsch3_int_st: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ - uint32_t duty_chng_end_lsch4_int_st: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ - uint32_t duty_chng_end_lsch5_int_st: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ - uint32_t duty_chng_end_lsch6_int_st: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ - uint32_t duty_chng_end_lsch7_int_st: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ - uint32_t reserved24: 8; + uint32_t hstimer0_ovf: 1; /*The interrupt status bit for high speed channel0 counter overflow event.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt status bit for high speed channel1 counter overflow event.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.* uint32_t duty_chng_end_hsch0: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt status bit for high speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt status bit for high speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt status bit for high speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt status bit for high speed channel 7 duty change done event.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt status bit for low speed channel 0 duty change done event.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt status bit for low speed channel 1 duty change done event.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt status bit for low speed channel 4 duty change done event.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt status bit for low speed channel 5 duty change done event.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt status bit for low speed channel 6 duty change done event.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt status bit for low speed channel 7 duty change done event*/ + uint32_t reserved24: 8; }; uint32_t val; }int_st; union { struct { - uint32_t hstimer0_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ - uint32_t hstimer1_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ - uint32_t hstimer2_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ - uint32_t hstimer3_ovf_int_ena: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ - uint32_t lstimer0_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ - uint32_t lstimer1_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ - uint32_t lstimer2_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ - uint32_t lstimer3_ovf_int_ena: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ - uint32_t duty_chng_end_hsch0_int_ena: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch1_int_ena: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch2_int_ena: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch3_int_ena: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch4_int_ena: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch5_int_ena: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch6_int_ena: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch7_int_ena: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch0_int_ena: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch1_int_ena: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch2_int_ena: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch3_int_ena: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch4_int_ena: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch5_int_ena: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch6_int_ena: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch7_int_ena: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ - uint32_t reserved24: 8; + uint32_t hstimer0_ovf: 1; /*The interrupt enable bit for high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf: 1; /*The interrupt enable bit for high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf: 1; /*The interrupt enable bit for low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf: 1; /*The interrupt enable bit for low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf: 1; /*The interrupt enable bit for low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt enable bit for low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0: 1; /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3: 1; /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4: 1; /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5: 1; /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6: 1; /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7: 1; /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0: 1; /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3: 1; /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4: 1; /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5: 1; /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6: 1; /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7: 1; /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; }; uint32_t val; }int_ena; union { struct { - uint32_t hstimer0_ovf_int_clr: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ - uint32_t hstimer1_ovf_int_clr: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ - uint32_t hstimer2_ovf_int_clr: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ - uint32_t hstimer3_ovf_int_clr: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ - uint32_t lstimer0_ovf_int_clr: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ - uint32_t lstimer1_ovf_int_clr: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ - uint32_t lstimer2_ovf_int_clr: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ - uint32_t lstimer3_ovf_int_clr: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ - uint32_t duty_chng_end_hsch0_int_clr: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch1_int_clr: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch2_int_clr: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch3_int_clr: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch4_int_clr: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch5_int_clr: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch6_int_clr: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_hsch7_int_clr: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch0_int_clr: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch1_int_clr: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch2_int_clr: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch3_int_clr: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch4_int_clr: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch5_int_clr: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch6_int_clr: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ - uint32_t duty_chng_end_lsch7_int_clr: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ - uint32_t reserved24: 8; + uint32_t hstimer0_ovf: 1; /*Set this bit to clear high speed channel0 counter overflow interrupt.*/ + uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/ + uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/ + uint32_t hstimer3_ovf: 1; /*Set this bit to clear high speed channel3 counter overflow interrupt.*/ + uint32_t lstimer0_ovf: 1; /*Set this bit to clear low speed channel0 counter overflow interrupt.*/ + uint32_t lstimer1_ovf: 1; /*Set this bit to clear low speed channel1 counter overflow interrupt.*/ + uint32_t lstimer2_ovf: 1; /*Set this bit to clear low speed channel2 counter overflow interrupt.*/ + uint32_t lstimer3_ovf: 1; /*Set this bit to clear low speed channel3 counter overflow interrupt.*/ + uint32_t duty_chng_end_hsch0: 1; /*Set this bit to clear high speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch3: 1; /*Set this bit to clear high speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch4: 1; /*Set this bit to clear high speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch5: 1; /*Set this bit to clear high speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch6: 1; /*Set this bit to clear high speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_hsch7: 1; /*Set this bit to clear high speed channel 7 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch0: 1; /*Set this bit to clear low speed channel 0 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch3: 1; /*Set this bit to clear low speed channel 3 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch4: 1; /*Set this bit to clear low speed channel 4 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch5: 1; /*Set this bit to clear low speed channel 5 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch6: 1; /*Set this bit to clear low speed channel 6 duty change done interrupt.*/ + uint32_t duty_chng_end_lsch7: 1; /*Set this bit to clear low speed channel 7 duty change done interrupt.*/ + uint32_t reserved24: 8; }; uint32_t val; }int_clr; diff --git a/components/esp32/include/soc/pcnt_struct.h b/components/esp32/include/soc/pcnt_struct.h index 1505cc692..5cd1f9313 100644 --- a/components/esp32/include/soc/pcnt_struct.h +++ b/components/esp32/include/soc/pcnt_struct.h @@ -59,57 +59,57 @@ typedef volatile struct { }cnt_unit[8]; union { struct { - uint32_t cnt_thr_event_u0_int_raw: 1; /*This is the interrupt raw bit for channel0 event.*/ - uint32_t cnt_thr_event_u1_int_raw: 1; /*This is the interrupt raw bit for channel1 event.*/ - uint32_t cnt_thr_event_u2_int_raw: 1; /*This is the interrupt raw bit for channel2 event.*/ - uint32_t cnt_thr_event_u3_int_raw: 1; /*This is the interrupt raw bit for channel3 event.*/ - uint32_t cnt_thr_event_u4_int_raw: 1; /*This is the interrupt raw bit for channel4 event.*/ - uint32_t cnt_thr_event_u5_int_raw: 1; /*This is the interrupt raw bit for channel5 event.*/ - uint32_t cnt_thr_event_u6_int_raw: 1; /*This is the interrupt raw bit for channel6 event.*/ - uint32_t cnt_thr_event_u7_int_raw: 1; /*This is the interrupt raw bit for channel7 event.*/ - uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/ + uint32_t reserved8: 24; }; uint32_t val; }int_raw; union { struct { - uint32_t cnt_thr_event_u0_int_st: 1; /*This is the interrupt status bit for channel0 event.*/ - uint32_t cnt_thr_event_u1_int_st: 1; /*This is the interrupt status bit for channel1 event.*/ - uint32_t cnt_thr_event_u2_int_st: 1; /*This is the interrupt status bit for channel2 event.*/ - uint32_t cnt_thr_event_u3_int_st: 1; /*This is the interrupt status bit for channel3 event.*/ - uint32_t cnt_thr_event_u4_int_st: 1; /*This is the interrupt status bit for channel4 event.*/ - uint32_t cnt_thr_event_u5_int_st: 1; /*This is the interrupt status bit for channel5 event.*/ - uint32_t cnt_thr_event_u6_int_st: 1; /*This is the interrupt status bit for channel6 event.*/ - uint32_t cnt_thr_event_u7_int_st: 1; /*This is the interrupt status bit for channel7 event.*/ - uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/ + uint32_t reserved8: 24; }; uint32_t val; }int_st; union { struct { - uint32_t cnt_thr_event_u0_int_ena: 1; /*This is the interrupt enable bit for channel0 event.*/ - uint32_t cnt_thr_event_u1_int_ena: 1; /*This is the interrupt enable bit for channel1 event.*/ - uint32_t cnt_thr_event_u2_int_ena: 1; /*This is the interrupt enable bit for channel2 event.*/ - uint32_t cnt_thr_event_u3_int_ena: 1; /*This is the interrupt enable bit for channel3 event.*/ - uint32_t cnt_thr_event_u4_int_ena: 1; /*This is the interrupt enable bit for channel4 event.*/ - uint32_t cnt_thr_event_u5_int_ena: 1; /*This is the interrupt enable bit for channel5 event.*/ - uint32_t cnt_thr_event_u6_int_ena: 1; /*This is the interrupt enable bit for channel6 event.*/ - uint32_t cnt_thr_event_u7_int_ena: 1; /*This is the interrupt enable bit for channel7 event.*/ - uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/ + uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ + uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ + uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ + uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/ + uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/ + uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/ + uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/ + uint32_t reserved8: 24; }; uint32_t val; }int_ena; union { struct { - uint32_t cnt_thr_event_u0_int_clr: 1; /*Set this bit to clear channel0 event interrupt.*/ - uint32_t cnt_thr_event_u1_int_clr: 1; /*Set this bit to clear channel1 event interrupt.*/ - uint32_t cnt_thr_event_u2_int_clr: 1; /*Set this bit to clear channel2 event interrupt.*/ - uint32_t cnt_thr_event_u3_int_clr: 1; /*Set this bit to clear channel3 event interrupt.*/ - uint32_t cnt_thr_event_u4_int_clr: 1; /*Set this bit to clear channel4 event interrupt.*/ - uint32_t cnt_thr_event_u5_int_clr: 1; /*Set this bit to clear channel5 event interrupt.*/ - uint32_t cnt_thr_event_u6_int_clr: 1; /*Set this bit to clear channel6 event interrupt.*/ - uint32_t cnt_thr_event_u7_int_clr: 1; /*Set this bit to clear channel7 event interrupt.*/ - uint32_t reserved8: 24; + uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/ + uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ + uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ + uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ + uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/ + uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/ + uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/ + uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/ + uint32_t reserved8: 24; }; uint32_t val; }int_clr; diff --git a/components/esp32/include/soc/rmt_struct.h b/components/esp32/include/soc/rmt_struct.h index dc3148eaa..6523e2191 100644 --- a/components/esp32/include/soc/rmt_struct.h +++ b/components/esp32/include/soc/rmt_struct.h @@ -52,169 +52,169 @@ typedef volatile struct { uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/ union { struct { - uint32_t ch0_tx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ - uint32_t ch0_rx_end_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ - uint32_t ch0_err_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ - uint32_t ch1_tx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ - uint32_t ch1_rx_end_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ - uint32_t ch1_err_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ - uint32_t ch2_tx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ - uint32_t ch2_rx_end_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ - uint32_t ch2_err_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ - uint32_t ch3_tx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ - uint32_t ch3_rx_end_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ - uint32_t ch3_err_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ - uint32_t ch4_tx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ - uint32_t ch4_rx_end_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ - uint32_t ch4_err_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ - uint32_t ch5_tx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ - uint32_t ch5_rx_end_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ - uint32_t ch5_err_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ - uint32_t ch6_tx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ - uint32_t ch6_rx_end_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ - uint32_t ch6_err_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ - uint32_t ch7_tx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ - uint32_t ch7_rx_end_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ - uint32_t ch7_err_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ - uint32_t ch0_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch1_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch2_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch3_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch4_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch5_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch6_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ - uint32_t ch7_tx_thr_event_int_raw: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/ + uint32_t ch0_rx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/ + uint32_t ch0_err: 1; /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/ + uint32_t ch1_tx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/ + uint32_t ch1_rx_end: 1; /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/ + uint32_t ch1_err: 1; /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/ + uint32_t ch2_tx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/ + uint32_t ch2_rx_end: 1; /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/ + uint32_t ch2_err: 1; /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/ + uint32_t ch3_tx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/ + uint32_t ch3_rx_end: 1; /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/ + uint32_t ch3_err: 1; /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/ + uint32_t ch4_tx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/ + uint32_t ch4_rx_end: 1; /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/ + uint32_t ch4_err: 1; /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/ + uint32_t ch5_tx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/ + uint32_t ch5_rx_end: 1; /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/ + uint32_t ch5_err: 1; /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/ + uint32_t ch6_tx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/ + uint32_t ch6_rx_end: 1; /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/ + uint32_t ch6_err: 1; /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/ + uint32_t ch7_tx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/ + uint32_t ch7_rx_end: 1; /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/ + uint32_t ch7_err: 1; /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/ + uint32_t ch0_tx_thr_event: 1; /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0 have send data more than reg_rmt_tx_lim_ch0 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch1_tx_thr_event: 1; /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1 have send data more than reg_rmt_tx_lim_ch1 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch2_tx_thr_event: 1; /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2 have send data more than reg_rmt_tx_lim_ch2 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch3_tx_thr_event: 1; /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3 have send data more than reg_rmt_tx_lim_ch3 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch4_tx_thr_event: 1; /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4 have send data more than reg_rmt_tx_lim_ch4 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch5_tx_thr_event: 1; /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5 have send data more than reg_rmt_tx_lim_ch5 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch6_tx_thr_event: 1; /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6 have send data more than reg_rmt_tx_lim_ch6 after detecting this interrupt software can updata the old data with new data.*/ + uint32_t ch7_tx_thr_event: 1; /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7 have send data more than reg_rmt_tx_lim_ch7 after detecting this interrupt software can updata the old data with new data.*/ }; uint32_t val; }int_raw; union { struct { - uint32_t ch0_tx_end_int_st: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ - uint32_t ch0_rx_end_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ - uint32_t ch0_err_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ - uint32_t ch1_tx_end_int_st: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ - uint32_t ch1_rx_end_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ - uint32_t ch1_err_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ - uint32_t ch2_tx_end_int_st: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ - uint32_t ch2_rx_end_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ - uint32_t ch2_err_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ - uint32_t ch3_tx_end_int_st: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ - uint32_t ch3_rx_end_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ - uint32_t ch3_err_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ - uint32_t ch4_tx_end_int_st: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ - uint32_t ch4_rx_end_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ - uint32_t ch4_err_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ - uint32_t ch5_tx_end_int_st: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ - uint32_t ch5_rx_end_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ - uint32_t ch5_err_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ - uint32_t ch6_tx_end_int_st: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ - uint32_t ch6_rx_end_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ - uint32_t ch6_err_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ - uint32_t ch7_tx_end_int_st: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ - uint32_t ch7_rx_end_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ - uint32_t ch7_err_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ - uint32_t ch0_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch1_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch2_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch3_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch4_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch5_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch6_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ - uint32_t ch7_tx_thr_event_int_st: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch0_tx_end: 1; /*The interrupt state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/ + uint32_t ch0_rx_end: 1; /*The interrupt state bit for channel 0's rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.*/ + uint32_t ch0_err: 1; /*The interrupt state bit for channel 0's rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.*/ + uint32_t ch1_tx_end: 1; /*The interrupt state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/ + uint32_t ch1_rx_end: 1; /*The interrupt state bit for channel 1's rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.*/ + uint32_t ch1_err: 1; /*The interrupt state bit for channel 1's rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.*/ + uint32_t ch2_tx_end: 1; /*The interrupt state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/ + uint32_t ch2_rx_end: 1; /*The interrupt state bit for channel 2's rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.*/ + uint32_t ch2_err: 1; /*The interrupt state bit for channel 2's rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.*/ + uint32_t ch3_tx_end: 1; /*The interrupt state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/ + uint32_t ch3_rx_end: 1; /*The interrupt state bit for channel 3's rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.*/ + uint32_t ch3_err: 1; /*The interrupt state bit for channel 3's rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.*/ + uint32_t ch4_tx_end: 1; /*The interrupt state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/ + uint32_t ch4_rx_end: 1; /*The interrupt state bit for channel 4's rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.*/ + uint32_t ch4_err: 1; /*The interrupt state bit for channel 4's rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.*/ + uint32_t ch5_tx_end: 1; /*The interrupt state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/ + uint32_t ch5_rx_end: 1; /*The interrupt state bit for channel 5's rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.*/ + uint32_t ch5_err: 1; /*The interrupt state bit for channel 5's rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.*/ + uint32_t ch6_tx_end: 1; /*The interrupt state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/ + uint32_t ch6_rx_end: 1; /*The interrupt state bit for channel 6's rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.*/ + uint32_t ch6_err: 1; /*The interrupt state bit for channel 6's rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.*/ + uint32_t ch7_tx_end: 1; /*The interrupt state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/ + uint32_t ch7_rx_end: 1; /*The interrupt state bit for channel 7's rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.*/ + uint32_t ch7_err: 1; /*The interrupt state bit for channel 7's rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.*/ + uint32_t ch0_tx_thr_event: 1; /*The interrupt state bit for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch1_tx_thr_event: 1; /*The interrupt state bit for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch2_tx_thr_event: 1; /*The interrupt state bit for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch3_tx_thr_event: 1; /*The interrupt state bit for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch4_tx_thr_event: 1; /*The interrupt state bit for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch5_tx_thr_event: 1; /*The interrupt state bit for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch6_tx_thr_event: 1; /*The interrupt state bit for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/ + uint32_t ch7_tx_thr_event: 1; /*The interrupt state bit for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/ }; uint32_t val; }int_st; union { struct { - uint32_t ch0_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ - uint32_t ch0_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ - uint32_t ch0_err_int_ena: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ - uint32_t ch1_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ - uint32_t ch1_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ - uint32_t ch1_err_int_ena: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ - uint32_t ch2_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ - uint32_t ch2_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ - uint32_t ch2_err_int_ena: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ - uint32_t ch3_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ - uint32_t ch3_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ - uint32_t ch3_err_int_ena: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ - uint32_t ch4_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ - uint32_t ch4_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ - uint32_t ch4_err_int_ena: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ - uint32_t ch5_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ - uint32_t ch5_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ - uint32_t ch5_err_int_ena: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ - uint32_t ch6_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ - uint32_t ch6_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ - uint32_t ch6_err_int_ena: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ - uint32_t ch7_tx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ - uint32_t ch7_rx_end_int_ena: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ - uint32_t ch7_err_int_ena: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ - uint32_t ch0_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ - uint32_t ch1_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ - uint32_t ch2_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ - uint32_t ch3_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ - uint32_t ch4_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ - uint32_t ch5_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ - uint32_t ch6_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ - uint32_t ch7_tx_thr_event_int_ena: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ + uint32_t ch0_tx_end: 1; /*Set this bit to enable rmt_ch0_tx_end_int_st.*/ + uint32_t ch0_rx_end: 1; /*Set this bit to enable rmt_ch0_rx_end_int_st.*/ + uint32_t ch0_err: 1; /*Set this bit to enable rmt_ch0_err_int_st.*/ + uint32_t ch1_tx_end: 1; /*Set this bit to enable rmt_ch1_tx_end_int_st.*/ + uint32_t ch1_rx_end: 1; /*Set this bit to enable rmt_ch1_rx_end_int_st.*/ + uint32_t ch1_err: 1; /*Set this bit to enable rmt_ch1_err_int_st.*/ + uint32_t ch2_tx_end: 1; /*Set this bit to enable rmt_ch2_tx_end_int_st.*/ + uint32_t ch2_rx_end: 1; /*Set this bit to enable rmt_ch2_rx_end_int_st.*/ + uint32_t ch2_err: 1; /*Set this bit to enable rmt_ch2_err_int_st.*/ + uint32_t ch3_tx_end: 1; /*Set this bit to enable rmt_ch3_tx_end_int_st.*/ + uint32_t ch3_rx_end: 1; /*Set this bit to enable rmt_ch3_rx_end_int_st.*/ + uint32_t ch3_err: 1; /*Set this bit to enable rmt_ch3_err_int_st.*/ + uint32_t ch4_tx_end: 1; /*Set this bit to enable rmt_ch4_tx_end_int_st.*/ + uint32_t ch4_rx_end: 1; /*Set this bit to enable rmt_ch4_rx_end_int_st.*/ + uint32_t ch4_err: 1; /*Set this bit to enable rmt_ch4_err_int_st.*/ + uint32_t ch5_tx_end: 1; /*Set this bit to enable rmt_ch5_tx_end_int_st.*/ + uint32_t ch5_rx_end: 1; /*Set this bit to enable rmt_ch5_rx_end_int_st.*/ + uint32_t ch5_err: 1; /*Set this bit to enable rmt_ch5_err_int_st.*/ + uint32_t ch6_tx_end: 1; /*Set this bit to enable rmt_ch6_tx_end_int_st.*/ + uint32_t ch6_rx_end: 1; /*Set this bit to enable rmt_ch6_rx_end_int_st.*/ + uint32_t ch6_err: 1; /*Set this bit to enable rmt_ch6_err_int_st.*/ + uint32_t ch7_tx_end: 1; /*Set this bit to enable rmt_ch7_tx_end_int_st.*/ + uint32_t ch7_rx_end: 1; /*Set this bit to enable rmt_ch7_rx_end_int_st.*/ + uint32_t ch7_err: 1; /*Set this bit to enable rmt_ch7_err_int_st.*/ + uint32_t ch0_tx_thr_event: 1; /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/ + uint32_t ch1_tx_thr_event: 1; /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/ + uint32_t ch2_tx_thr_event: 1; /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/ + uint32_t ch3_tx_thr_event: 1; /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/ + uint32_t ch4_tx_thr_event: 1; /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/ + uint32_t ch5_tx_thr_event: 1; /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/ + uint32_t ch6_tx_thr_event: 1; /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/ + uint32_t ch7_tx_thr_event: 1; /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/ }; uint32_t val; }int_ena; union { struct { - uint32_t ch0_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ - uint32_t ch0_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ - uint32_t ch0_err_int_clr: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ - uint32_t ch1_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ - uint32_t ch1_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ - uint32_t ch1_err_int_clr: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ - uint32_t ch2_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ - uint32_t ch2_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ - uint32_t ch2_err_int_clr: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ - uint32_t ch3_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ - uint32_t ch3_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ - uint32_t ch3_err_int_clr: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ - uint32_t ch4_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ - uint32_t ch4_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ - uint32_t ch4_err_int_clr: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ - uint32_t ch5_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ - uint32_t ch5_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ - uint32_t ch5_err_int_clr: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ - uint32_t ch6_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ - uint32_t ch6_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ - uint32_t ch6_err_int_clr: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ - uint32_t ch7_tx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ - uint32_t ch7_rx_end_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ - uint32_t ch7_err_int_clr: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ - uint32_t ch0_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ - uint32_t ch1_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ - uint32_t ch2_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ - uint32_t ch3_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ - uint32_t ch4_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ - uint32_t ch5_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ - uint32_t ch6_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ - uint32_t ch7_tx_thr_event_int_clr: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ + uint32_t ch0_tx_end: 1; /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/ + uint32_t ch0_rx_end: 1; /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/ + uint32_t ch0_err: 1; /*Set this bit to clear the rmt_ch0_err_int_raw.*/ + uint32_t ch1_tx_end: 1; /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/ + uint32_t ch1_rx_end: 1; /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/ + uint32_t ch1_err: 1; /*Set this bit to clear the rmt_ch1_err_int_raw.*/ + uint32_t ch2_tx_end: 1; /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/ + uint32_t ch2_rx_end: 1; /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/ + uint32_t ch2_err: 1; /*Set this bit to clear the rmt_ch2_err_int_raw.*/ + uint32_t ch3_tx_end: 1; /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/ + uint32_t ch3_rx_end: 1; /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/ + uint32_t ch3_err: 1; /*Set this bit to clear the rmt_ch3_err_int_raw.*/ + uint32_t ch4_tx_end: 1; /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/ + uint32_t ch4_rx_end: 1; /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/ + uint32_t ch4_err: 1; /*Set this bit to clear the rmt_ch4_err_int_raw.*/ + uint32_t ch5_tx_end: 1; /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/ + uint32_t ch5_rx_end: 1; /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/ + uint32_t ch5_err: 1; /*Set this bit to clear the rmt_ch5_err_int_raw.*/ + uint32_t ch6_tx_end: 1; /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/ + uint32_t ch6_rx_end: 1; /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/ + uint32_t ch6_err: 1; /*Set this bit to clear the rmt_ch6_err_int_raw.*/ + uint32_t ch7_tx_end: 1; /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/ + uint32_t ch7_rx_end: 1; /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/ + uint32_t ch7_err: 1; /*Set this bit to clear the rmt_ch7_err_int_raw.*/ + uint32_t ch0_tx_thr_event: 1; /*Set this bit to clear the rmt_ch0_tx_thr_event_int_raw interrupt.*/ + uint32_t ch1_tx_thr_event: 1; /*Set this bit to clear the rmt_ch1_tx_thr_event_int_raw interrupt.*/ + uint32_t ch2_tx_thr_event: 1; /*Set this bit to clear the rmt_ch2_tx_thr_event_int_raw interrupt.*/ + uint32_t ch3_tx_thr_event: 1; /*Set this bit to clear the rmt_ch3_tx_thr_event_int_raw interrupt.*/ + uint32_t ch4_tx_thr_event: 1; /*Set this bit to clear the rmt_ch4_tx_thr_event_int_raw interrupt.*/ + uint32_t ch5_tx_thr_event: 1; /*Set this bit to clear the rmt_ch5_tx_thr_event_int_raw interrupt.*/ + uint32_t ch6_tx_thr_event: 1; /*Set this bit to clear the rmt_ch6_tx_thr_event_int_raw interrupt.*/ + uint32_t ch7_tx_thr_event: 1; /*Set this bit to clear the rmt_ch7_tx_thr_event_int_raw interrupt.*/ }; uint32_t val; }int_clr; union { struct { - uint32_t carrier_low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ - uint32_t carrier_high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ + uint32_t low: 16; /*This register is used to configure carrier wave's low level value for channel0-7.*/ + uint32_t high:16; /*This register is used to configure carrier wave's high level value for channel0-7.*/ }; uint32_t val; }carrier_duty_ch[8]; union { struct { - uint32_t tx_lim: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ + uint32_t limit: 9; /*When channel0-7 sends more than reg_rmt_tx_lim_ch0 data then channel0-7 produce the relative interrupt.*/ uint32_t reserved9: 23; }; uint32_t val; }tx_lim_ch[8]; union { struct { - uint32_t apb_fifo_mask: 1; /*Set this bit to disable apb fifo access*/ + uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/ uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/ uint32_t reserved2: 30; }; diff --git a/components/esp32/include/soc/spi_struct.h b/components/esp32/include/soc/spi_struct.h index 0eb64e91d..31b86308b 100644 --- a/components/esp32/include/soc/spi_struct.h +++ b/components/esp32/include/soc/spi_struct.h @@ -188,79 +188,79 @@ typedef volatile struct { }pin; union { struct { - uint32_t slv_rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ - uint32_t slv_wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ - uint32_t slv_rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ - uint32_t slv_wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ - uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ - uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ - uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ - uint32_t reserved12: 5; /*reserved*/ - uint32_t slv_last_command: 3; /*In the slave mode it is the value of command.*/ - uint32_t slv_last_state: 3; /*In the slave mode it is the state of spi state machine.*/ - uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ - uint32_t slv_cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ - uint32_t slv_wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ - uint32_t slv_wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ - uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ - uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ + uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ + uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ + uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ + uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ + uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ + uint32_t int_en: 5; /*Interrupt enable bits for the below 5 sources*/ + uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ + uint32_t reserved12: 5; /*reserved*/ + uint32_t last_command: 3; /*In the slave mode it is the value of command.*/ + uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/ + uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ + uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ + uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ + uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ + uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ + uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ }; uint32_t val; }slave; union { struct { - uint32_t slv_rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ - uint32_t slv_wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ - uint32_t slv_rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ - uint32_t slv_wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ - uint32_t slv_wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ - uint32_t slv_rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ - uint32_t reserved16: 9; /*reserved*/ - uint32_t slv_status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ - uint32_t slv_status_fast_en: 1; /*In the slave mode enable fast read status.*/ - uint32_t slv_status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ + uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ + uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ + uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ + uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ + uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ + uint32_t reserved16: 9; /*reserved*/ + uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ + uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/ + uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ }; uint32_t val; }slave1; union { struct { - uint32_t slv_rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ - uint32_t slv_wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ - uint32_t slv_rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ - uint32_t slv_wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ + uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ + uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ + uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ + uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ }; uint32_t val; }slave2; union { struct { - uint32_t slv_rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ - uint32_t slv_wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ - uint32_t slv_rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ - uint32_t slv_wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ + uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ + uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ + uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ + uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ }; uint32_t val; }slave3; union { struct { - uint32_t slv_wrbuf_dbitlen:24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ - uint32_t reserved24: 8; /*reserved*/ + uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ }; uint32_t val; }slv_wrbuf_dlen; union { struct { - uint32_t slv_rdbuf_dbitlen:24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ - uint32_t reserved24: 8; /*reserved*/ + uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ + uint32_t reserved24: 8; /*reserved*/ }; uint32_t val; }slv_rdbuf_dlen; union { struct { - uint32_t cache_req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ - uint32_t cache_usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ - uint32_t cache_flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ - uint32_t cache_flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ - uint32_t reserved4: 28; /*reserved*/ + uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ + uint32_t reserved4: 28; /*reserved*/ }; uint32_t val; }cache_fctrl; @@ -282,27 +282,27 @@ typedef volatile struct { }cache_sctrl; union { struct { - uint32_t sram_dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ - uint32_t sram_qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ - uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ - uint32_t sram_rstio: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ - uint32_t reserved5: 27; /*reserved*/ + uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ + uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ + uint32_t reserved5:27; /*reserved*/ }; uint32_t val; }sram_cmd; union { struct { - uint32_t cache_sram_usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ - uint32_t reserved16: 12; /*reserved*/ - uint32_t cache_sram_usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ }; uint32_t val; }sram_drd_cmd; union { struct { - uint32_t cache_sram_usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ - uint32_t reserved16: 12; /*reserved*/ - uint32_t cache_sram_usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ + uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ }; uint32_t val; }sram_dwr_cmd; @@ -390,92 +390,92 @@ typedef volatile struct { }dma_conf; union { struct { - uint32_t outlink_addr: 20; /*The address of the first outlink descriptor.*/ - uint32_t reserved20: 8; /*reserved*/ - uint32_t outlink_stop: 1; /*Set the bit to stop to use outlink descriptor.*/ - uint32_t outlink_start: 1; /*Set the bit to start to use outlink descriptor.*/ - uint32_t outlink_restart: 1; /*Set the bit to mount on new outlink descriptors.*/ - uint32_t reserved31: 1; /*reserved*/ + uint32_t addr: 20; /*The address of the first outlink descriptor.*/ + uint32_t reserved20: 8; /*reserved*/ + uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/ + uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/ + uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ }; uint32_t val; }dma_out_link; union { struct { - uint32_t inlink_addr: 20; /*The address of the first inlink descriptor.*/ - uint32_t inlink_auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ - uint32_t reserved21: 7; /*reserved*/ - uint32_t inlink_stop: 1; /*Set the bit to stop to use inlink descriptor.*/ - uint32_t inlink_start: 1; /*Set the bit to start to use inlink descriptor.*/ - uint32_t inlink_restart: 1; /*Set the bit to mount on new inlink descriptors.*/ - uint32_t reserved31: 1; /*reserved*/ + uint32_t addr: 20; /*The address of the first inlink descriptor.*/ + uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ + uint32_t reserved21: 7; /*reserved*/ + uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/ + uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/ + uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/ + uint32_t reserved31: 1; /*reserved*/ }; uint32_t val; }dma_in_link; union { struct { - uint32_t dma_rx_en: 1; /*spi dma read data status bit.*/ - uint32_t dma_tx_en: 1; /*spi dma write data status bit.*/ + uint32_t rx_en: 1; /*spi dma read data status bit.*/ + uint32_t tx_en: 1; /*spi dma write data status bit.*/ uint32_t reserved2: 30; /*spi dma read data from memory count.*/ }; uint32_t val; }dma_status; union { - struct { - uint32_t inlink_dscr_empty_int_ena: 1; /*The enable bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error_int_ena: 1; /*The enable bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error_int_ena: 1; /*The enable bit for inlink descriptor error.*/ - uint32_t in_done_int_ena: 1; /*The enable bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof_int_ena: 1; /*The enable bit for receiving error.*/ - uint32_t in_suc_eof_int_ena: 1; /*The enable bit for completing receiving all the packets from host.*/ - uint32_t out_done_int_ena: 1; /*The enable bit for completing usage of a outlink descriptor .*/ - uint32_t out_eof_int_ena: 1; /*The enable bit for sending a packet to host done.*/ - uint32_t out_total_eof_int_ena: 1; /*The enable bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ + struct {_int_clr + uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/ + uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; uint32_t val; }dma_int_ena; union { struct { - uint32_t inlink_dscr_empty_int_raw: 1; /*The raw bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error_int_raw: 1; /*The raw bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error_int_raw: 1; /*The raw bit for inlink descriptor error.*/ - uint32_t in_done_int_raw: 1; /*The raw bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof_int_raw: 1; /*The raw bit for receiving error.*/ - uint32_t in_suc_eof_int_raw: 1; /*The raw bit for completing receiving all the packets from host.*/ - uint32_t out_done_int_raw: 1; /*The raw bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof_int_raw: 1; /*The raw bit for sending a packet to host done.*/ - uint32_t out_total_eof_int_raw: 1; /*The raw bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; uint32_t val; }dma_int_raw; union { struct { - uint32_t inlink_dscr_empty_int_st: 1; /*The status bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error_int_st: 1; /*The status bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error_int_st: 1; /*The status bit for inlink descriptor error.*/ - uint32_t in_done_int_st: 1; /*The status bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof_int_st: 1; /*The status bit for receiving error.*/ - uint32_t in_suc_eof_int_st: 1; /*The status bit for completing receiving all the packets from host.*/ - uint32_t out_done_int_st: 1; /*The status bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof_int_st: 1; /*The status bit for sending a packet to host done.*/ - uint32_t out_total_eof_int_st: 1; /*The status bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The status bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; uint32_t val; }dma_int_st; union { struct { - uint32_t inlink_dscr_empty_int_clr: 1; /*The clear bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error_int_clr: 1; /*The clear bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error_int_clr: 1; /*The clear bit for inlink descriptor error.*/ - uint32_t in_done_int_clr: 1; /*The clear bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof_int_clr: 1; /*The clear bit for receiving error.*/ - uint32_t in_suc_eof_int_clr: 1; /*The clear bit for completing receiving all the packets from host.*/ - uint32_t out_done_int_clr: 1; /*The clear bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof_int_clr: 1; /*The clear bit for sending a packet to host done.*/ - uint32_t out_total_eof_int_clr: 1; /*The clear bit for sending all the packets to host done.*/ - uint32_t reserved9: 23; /*reserved*/ + uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/ + uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/ + uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/ + uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/ + uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/ + uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/ + uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/ + uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/ + uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/ + uint32_t reserved9: 23; /*reserved*/ }; uint32_t val; }dma_int_clr; diff --git a/components/esp32/include/soc/timer_group_struct.h b/components/esp32/include/soc/timer_group_struct.h index 2160dfeea..8f25ce9b6 100644 --- a/components/esp32/include/soc/timer_group_struct.h +++ b/components/esp32/include/soc/timer_group_struct.h @@ -28,35 +28,35 @@ typedef volatile struct { }; uint32_t val; }config; - uint32_t timer_cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ - uint32_t timer_cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ - uint32_t timer_update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ - uint32_t timer_alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ - uint32_t timer_alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ - uint32_t timer_load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ - uint32_t timer_load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ - uint32_t timer_reload; /*Write any value will trigger timer 0 time-base counter reload*/ + uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ + uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ + uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ + uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ + uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ + uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ + uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ }hw_timer[2]; union { struct { - uint32_t reserved0: 14; - uint32_t wdt_flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ - uint32_t wdt_sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ - uint32_t wdt_cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ - uint32_t wdt_level_int_en: 1; /*When set level type interrupt generation is enabled*/ - uint32_t wdt_edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ - uint32_t wdt_stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - uint32_t wdt_stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - uint32_t wdt_stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - uint32_t wdt_stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ - uint32_t wdt_en: 1; /*When set SWDT is enabled*/ + uint32_t reserved0: 14; + uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ + uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ + uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/ + uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ + uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ + uint32_t en: 1; /*When set SWDT is enabled*/ }; uint32_t val; }wdt_config0; union { struct { uint32_t reserved0: 16; - uint32_t wdt_clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ + uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ }; uint32_t val; }wdt_config1; @@ -69,41 +69,41 @@ typedef volatile struct { union { struct { uint32_t reserved0: 12; - uint32_t rtc_cali_start_cycling: 1; - uint32_t rtc_cali_clk_sel: 2; - uint32_t rtc_cali_rdy: 1; - uint32_t rtc_cali_max: 15; - uint32_t rtc_cali_start: 1; + uint32_t start_cycling: 1; + uint32_t clk_sel: 2; + uint32_t rdy: 1; + uint32_t max: 15; + uint32_t start: 1; }; uint32_t val; }rtc_cali_cfg; union { struct { uint32_t reserved0: 7; - uint32_t rtc_cali_value:25; + uint32_t value:25; }; uint32_t val; }rtc_cali_cfg1; union { struct { uint32_t reserved0: 7; - uint32_t lact_rtc_only: 1; - uint32_t lact_cpst_en: 1; - uint32_t lact_lac_en: 1; - uint32_t lact_alarm_en: 1; - uint32_t lact_level_int_en: 1; - uint32_t lact_edge_int_en: 1; - uint32_t lact_divider: 16; - uint32_t lact_autoreload: 1; - uint32_t lact_increase: 1; - uint32_t lact_en: 1; + uint32_t rtc_only: 1; + uint32_t cpst_en: 1; + uint32_t lac_en: 1; + uint32_t alarm_en: 1; + uint32_t level_int_en: 1; + uint32_t edge_int_en: 1; + uint32_t divider: 16; + uint32_t autoreload: 1; + uint32_t increase: 1; + uint32_t en: 1; }; uint32_t val; }lactconfig; union { struct { uint32_t reserved0: 6; - uint32_t lact_rtc_step_len:26; + uint32_t step_len:26; }; uint32_t val; }lactrtc; @@ -117,41 +117,41 @@ typedef volatile struct { uint32_t lactload; /**/ union { struct { - uint32_t t0_int_ena: 1; /*interrupt when timer0 alarm*/ - uint32_t t1_int_ena: 1; /*interrupt when timer1 alarm*/ - uint32_t wdt_int_ena: 1; /*Interrupt when an interrupt stage timeout*/ - uint32_t lact_int_ena: 1; - uint32_t reserved4: 28; + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; }; uint32_t val; - }int_ena_timers; + }int_ena; union { struct { - uint32_t t0_int_raw: 1; /*interrupt when timer0 alarm*/ - uint32_t t1_int_raw: 1; /*interrupt when timer1 alarm*/ - uint32_t wdt_int_raw: 1; /*Interrupt when an interrupt stage timeout*/ - uint32_t lact_int_raw: 1; - uint32_t reserved4: 28; + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4:28; }; uint32_t val; - }int_raw_timers; + }int_raw; union { struct { - uint32_t t0_int_st: 1; /*interrupt when timer0 alarm*/ - uint32_t t1_int_st: 1; /*interrupt when timer1 alarm*/ - uint32_t wdt_int_st: 1; /*Interrupt when an interrupt stage timeout*/ - uint32_t lact_int_st: 1; - uint32_t reserved4: 28; + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; }; uint32_t val; }int_st_timers; union { struct { - uint32_t t0_int_clr: 1; /*interrupt when timer0 alarm*/ - uint32_t t1_int_clr: 1; /*interrupt when timer1 alarm*/ - uint32_t wdt_int_clr: 1; /*Interrupt when an interrupt stage timeout*/ - uint32_t lact_int_clr: 1; - uint32_t reserved4: 28; + uint32_t t0: 1; /*interrupt when timer0 alarm*/ + uint32_t t1: 1; /*interrupt when timer1 alarm*/ + uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ + uint32_t lact: 1; + uint32_t reserved4: 28; }; uint32_t val; }int_clr_timers; @@ -185,7 +185,7 @@ typedef volatile struct { union { struct { uint32_t reserved0: 31; - uint32_t clk_en: 1; /*Force clock enable for this regfile*/ + uint32_t en: 1; /*Force clock enable for this regfile*/ }; uint32_t val; }clk; diff --git a/components/esp32/include/soc/uart_struct.h b/components/esp32/include/soc/uart_struct.h index 9874a6af6..54baf4f0e 100644 --- a/components/esp32/include/soc/uart_struct.h +++ b/components/esp32/include/soc/uart_struct.h @@ -16,122 +16,122 @@ typedef volatile struct { union { struct { - uint32_t fifo_rw_byte: 8; /*This register stores one byte data read by rx fifo.*/ - uint32_t reserved8: 24; + uint32_t rw_byte: 8; /*This register stores one byte data read by rx fifo.*/ + uint32_t reserved8: 24; }; uint32_t val; }fifo; union { struct { - uint32_t rxfifo_full_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ - uint32_t txfifo_empty_int_raw: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ - uint32_t parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ - uint32_t frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ - uint32_t rxfifo_ovf_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ - uint32_t dsr_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ - uint32_t cts_chg_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ - uint32_t brk_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ - uint32_t rxfifo_tout_int_raw: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ - uint32_t sw_xon_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ - uint32_t sw_xoff_int_raw: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ - uint32_t glitch_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ - uint32_t tx_brk_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ - uint32_t tx_brk_idle_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ - uint32_t tx_done_int_raw: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ - uint32_t rs485_parity_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ - uint32_t rs485_frm_err_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ - uint32_t rs485_clash_int_raw: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ - uint32_t at_cmd_char_det_int_raw: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ + uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ + uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ + uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ + uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ + uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ + uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ + uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ + uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ + uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ + uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ + uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ + uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ + uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ + uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ + uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ + uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ + uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ + uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ + uint32_t reserved19: 13; }; uint32_t val; }int_raw; union { struct { - uint32_t rxfifo_full_int_st: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ - uint32_t txfifo_empty_int_st: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ - uint32_t parity_err_int_st: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ - uint32_t frm_err_int_st: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ - uint32_t rxfifo_ovf_int_st: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ - uint32_t dsr_chg_int_st: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ - uint32_t cts_chg_int_st: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ - uint32_t brk_det_int_st: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ - uint32_t rxfifo_tout_int_st: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ - uint32_t sw_xon_int_st: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ - uint32_t sw_xoff_int_st: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ - uint32_t glitch_det_int_st: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ - uint32_t tx_brk_done_int_st: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ - uint32_t tx_brk_idle_done_int_st: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ - uint32_t tx_done_int_st: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ - uint32_t rs485_parity_err_int_st: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ - uint32_t rs485_frm_err_int_st: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ - uint32_t rs485_clash_int_st: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ - uint32_t at_cmd_char_det_int_st: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ + uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ + uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ + uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ + uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ + uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ + uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ + uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ + uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ + uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ + uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ + uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ + uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ + uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ + uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ + uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ + uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ + uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ + uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ + uint32_t reserved19: 13; }; uint32_t val; }int_st; union { struct { - uint32_t rxfifo_full_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t txfifo_empty_int_ena: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ - uint32_t parity_err_int_ena: 1; /*This is the enable bit for parity_err_int_st register.*/ - uint32_t frm_err_int_ena: 1; /*This is the enable bit for frm_err_int_st register.*/ - uint32_t rxfifo_ovf_int_ena: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ - uint32_t dsr_chg_int_ena: 1; /*This is the enable bit for dsr_chg_int_st register.*/ - uint32_t cts_chg_int_ena: 1; /*This is the enable bit for cts_chg_int_st register.*/ - uint32_t brk_det_int_ena: 1; /*This is the enable bit for brk_det_int_st register.*/ - uint32_t rxfifo_tout_int_ena: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ - uint32_t sw_xon_int_ena: 1; /*This is the enable bit for sw_xon_int_st register.*/ - uint32_t sw_xoff_int_ena: 1; /*This is the enable bit for sw_xoff_int_st register.*/ - uint32_t glitch_det_int_ena: 1; /*This is the enable bit for glitch_det_int_st register.*/ - uint32_t tx_brk_done_int_ena: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ - uint32_t tx_brk_idle_done_int_ena: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ - uint32_t tx_done_int_ena: 1; /*This is the enable bit for tx_done_int_st register.*/ - uint32_t rs485_parity_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_frm_err_int_ena: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ - uint32_t rs485_clash_int_ena: 1; /*This is the enable bit for rs485_clash_int_st register.*/ - uint32_t at_cmd_char_det_int_ena: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ + uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ + uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ + uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ + uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ + uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ + uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ + uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ + uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ + uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ + uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ + uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ + uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ + uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ + uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ + uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ + uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ + uint32_t reserved19: 13; }; uint32_t val; }int_ena; union { struct { - uint32_t rxfifo_full_int_clr: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ - uint32_t txfifo_empty_int_clr: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ - uint32_t parity_err_int_clr: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ - uint32_t frm_err_int_clr: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ - uint32_t rxfifo_ovf_int_clr: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ - uint32_t dsr_chg_int_clr: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ - uint32_t cts_chg_int_clr: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ - uint32_t brk_det_int_clr: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ - uint32_t rxfifo_tout_int_clr: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ - uint32_t sw_xon_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t sw_xoff_int_clr: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ - uint32_t glitch_det_int_clr: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ - uint32_t tx_brk_done_int_clr: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ - uint32_t tx_brk_idle_done_int_clr: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ - uint32_t tx_done_int_clr: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ - uint32_t rs485_parity_err_int_clr: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ - uint32_t rs485_frm_err_int_clr: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ - uint32_t rs485_clash_int_clr: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ - uint32_t at_cmd_char_det_int_clr: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ - uint32_t reserved19: 13; + uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ + uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ + uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ + uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ + uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ + uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ + uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ + uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ + uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ + uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ + uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ + uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ + uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ + uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + uint32_t reserved19: 13; }; uint32_t val; }int_clr; union { struct { - uint32_t clkdiv: 20; /*The register value is the integer part of the frequency divider's factor.*/ - uint32_t clkdiv_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ + uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/ + uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ uint32_t reserved24: 8; }; uint32_t val; }clk_div; union { struct { - uint32_t auto_baud_en: 1; /*This is the enable bit for detecting baudrate.*/ + uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/ uint32_t reserved1: 7; uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ uint32_t reserved16: 16; @@ -164,7 +164,7 @@ typedef volatile struct { uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ - uint32_t irda_dplx: 1; /*Set this bit to enable irda loopback mode.*/ + uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/ uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ @@ -202,21 +202,21 @@ typedef volatile struct { }conf1; union { struct { - uint32_t lowpulse_min_cnt:20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; uint32_t val; }lowpulse; union { struct { - uint32_t highpulse_min_cnt:20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; uint32_t val; }highpulse; union { struct { - uint32_t rxd_edge_cnt:10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ + uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ uint32_t reserved10: 22; }; uint32_t val; @@ -260,13 +260,13 @@ typedef volatile struct { }idle_conf; union { struct { - uint32_t rs485_en: 1; /*Set this bit to choose rs485 mode.*/ + uint32_t en: 1; /*Set this bit to choose rs485 mode.*/ uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ - uint32_t rs485tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ - uint32_t rs485rxby_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ - uint32_t rs485_rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ - uint32_t rs485_tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ + uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ + uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ + uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ + uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ uint32_t reserved10: 22; }; uint32_t val; @@ -294,7 +294,7 @@ typedef volatile struct { }at_cmd_gaptout; union { struct { - uint32_t at_cmd_char: 8; /*This register is used to configure the content of at_cmd char.*/ + uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ uint32_t reserved16: 16; }; @@ -320,44 +320,44 @@ typedef volatile struct { }mem_conf; union { struct { - uint32_t mem_tx_status:24; + uint32_t status:24; uint32_t reserved24: 8; }; uint32_t val; }mem_tx_status; union { struct { - uint32_t mem_rx_status:24; + uint32_t status:24; uint32_t reserved24: 8; }; uint32_t val; }mem_rx_status; union { struct { - uint32_t rx_mem_cnt: 3; /*refer to the rxfifo_cnt's description.*/ - uint32_t tx_mem_cnt: 3; /*refer to the txfifo_cnt's description.*/ + uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/ + uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/ uint32_t reserved6: 26; }; uint32_t val; }mem_cnt_status; union { struct { - uint32_t posedge_min_cnt:20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; uint32_t val; }pospulse; union { struct { - uint32_t negedge_min_cnt:20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ - uint32_t reserved20: 12; + uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ + uint32_t reserved20: 12; }; uint32_t val; }negpulse; uint32_t reserved_70; uint32_t reserved_74; - uint32_t date; /**/ - uint32_t id; /**/ + uint32_t date; /**/ + uint32_t id; /**/ } uart_dev_t; extern uart_dev_t UART0; extern uart_dev_t UART1; diff --git a/components/esp32/include/soc/uhci_struct.h b/components/esp32/include/soc/uhci_struct.h index 5a78990f2..58e18d0ea 100644 --- a/components/esp32/include/soc/uhci_struct.h +++ b/components/esp32/include/soc/uhci_struct.h @@ -46,168 +46,168 @@ typedef volatile struct { }conf0; union { struct { - uint32_t rx_start_int_raw: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ - uint32_t tx_start_int_raw: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ - uint32_t rx_hung_int_raw: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ - uint32_t tx_hung_int_raw: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ - uint32_t in_done_int_raw: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ - uint32_t in_suc_eof_int_raw: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ - uint32_t in_err_eof_int_raw: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ - uint32_t out_done_int_raw: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ - uint32_t out_eof_int_raw: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ - uint32_t in_dscr_err_int_raw: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ - uint32_t out_dscr_err_int_raw: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ - uint32_t in_dscr_empty_int_raw: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ - uint32_t outlink_eof_err_int_raw: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ - uint32_t out_total_eof_int_raw: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ - uint32_t send_s_q_int_raw: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ - uint32_t send_a_q_int_raw: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ - uint32_t dma_infifo_full_wm_int_raw: 1; - uint32_t reserved17: 15; + uint32_t rx_start: 1; /*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/ + uint32_t tx_start: 1; /*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/ + uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/ + uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/ + uint32_t in_done: 1; /*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/ + uint32_t in_suc_eof: 1; /*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/ + uint32_t in_err_eof: 1; /*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/ + uint32_t out_done: 1; /*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/ + uint32_t out_eof: 1; /*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/ + uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/ + uint32_t in_dscr_empty: 1; /*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/ + uint32_t outlink_eof_err: 1; /*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/ + uint32_t out_total_eof: 1; /*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/ + uint32_t send_s_q: 1; /*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t send_a_q: 1; /*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/ + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_raw; union { struct { - uint32_t rx_start_int_st: 1; - uint32_t tx_start_int_st: 1; - uint32_t rx_hung_int_st: 1; - uint32_t tx_hung_int_st: 1; - uint32_t in_done_int_st: 1; - uint32_t in_suc_eof_int_st: 1; - uint32_t in_err_eof_int_st: 1; - uint32_t out_done_int_st: 1; - uint32_t out_eof_int_st: 1; - uint32_t in_dscr_err_int_st: 1; - uint32_t out_dscr_err_int_st: 1; - uint32_t in_dscr_empty_int_st: 1; - uint32_t outlink_eof_err_int_st: 1; - uint32_t out_total_eof_int_st: 1; - uint32_t send_s_q_int_st: 1; - uint32_t send_a_q_int_st: 1; - uint32_t dma_infifo_full_wm_int_st: 1; - uint32_t reserved17: 15; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_st; union { struct { - uint32_t rx_start_int_ena: 1; - uint32_t tx_start_int_ena: 1; - uint32_t rx_hung_int_ena: 1; - uint32_t tx_hung_int_ena: 1; - uint32_t in_done_int_ena: 1; - uint32_t in_suc_eof_int_ena: 1; - uint32_t in_err_eof_int_ena: 1; - uint32_t out_done_int_ena: 1; - uint32_t out_eof_int_ena: 1; - uint32_t in_dscr_err_int_ena: 1; - uint32_t out_dscr_err_int_ena: 1; - uint32_t in_dscr_empty_int_ena: 1; - uint32_t outlink_eof_err_int_ena: 1; - uint32_t out_total_eof_int_ena: 1; - uint32_t send_s_q_int_ena: 1; - uint32_t send_a_q_int_ena: 1; - uint32_t dma_infifo_full_wm_int_ena: 1; - uint32_t reserved17: 15; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_ena; union { struct { - uint32_t rx_start_int_clr: 1; - uint32_t tx_start_int_clr: 1; - uint32_t rx_hung_int_clr: 1; - uint32_t tx_hung_int_clr: 1; - uint32_t in_done_int_clr: 1; - uint32_t in_suc_eof_int_clr: 1; - uint32_t in_err_eof_int_clr: 1; - uint32_t out_done_int_clr: 1; - uint32_t out_eof_int_clr: 1; - uint32_t in_dscr_err_int_clr: 1; - uint32_t out_dscr_err_int_clr: 1; - uint32_t in_dscr_empty_int_clr: 1; - uint32_t outlink_eof_err_int_clr: 1; - uint32_t out_total_eof_int_clr: 1; - uint32_t send_s_q_int_clr: 1; - uint32_t send_a_q_int_clr: 1; - uint32_t dma_infifo_full_wm_int_clr: 1; - uint32_t reserved17: 15; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t in_done: 1; + uint32_t in_suc_eof: 1; + uint32_t in_err_eof: 1; + uint32_t out_done: 1; + uint32_t out_eof: 1; + uint32_t in_dscr_err: 1; + uint32_t out_dscr_err: 1; + uint32_t in_dscr_empty: 1; + uint32_t outlink_eof_err: 1; + uint32_t out_total_eof: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t dma_in_fifo_full_wm: 1; + uint32_t reserved17: 15; }; uint32_t val; }int_clr; union { struct { - uint32_t out_full: 1; /*1:DMA out link descriptor's fifo is full.*/ - uint32_t out_empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ + uint32_t full: 1; /*1:DMA out link descriptor's fifo is full.*/ + uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/ uint32_t reserved2: 30; }; uint32_t val; }dma_out_status; union { struct { - uint32_t outfifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ - uint32_t reserved9: 7; - uint32_t outfifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ - uint32_t reserved17: 15; + uint32_t fifo_wdata: 9; /*This is the data need to be pushed into out link descriptor's fifo.*/ + uint32_t reserved9: 7; + uint32_t fifo_push: 1; /*Set this bit to push data in out link descriptor's fifo.*/ + uint32_t reserved17:15; }; uint32_t val; }dma_out_push; union { struct { - uint32_t in_full: 1; - uint32_t in_empty: 1; + uint32_t full: 1; + uint32_t empty: 1; uint32_t reserved2: 2; - uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ + uint32_t rx_err_cause: 3; /*This register stores the errors caused in out link descriptor's data packet.*/ uint32_t reserved7: 25; }; uint32_t val; }dma_in_status; union { struct { - uint32_t infifo_rdata:12; /*This register stores the data pop from in link descriptor's fifo.*/ + uint32_t fifo_rdata: 12; /*This register stores the data pop from in link descriptor's fifo.*/ uint32_t reserved12: 4; - uint32_t infifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ + uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/ uint32_t reserved17: 15; }; uint32_t val; }dma_in_pop; union { struct { - uint32_t outlink_addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ - uint32_t reserved20: 8; - uint32_t outlink_stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ - uint32_t outlink_start: 1; /*Set this bit to start dealing with the out link descriptors.*/ - uint32_t outlink_restart: 1; /*Set this bit to mount on new out link descriptors*/ - uint32_t outlink_park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ + uint32_t addr: 20; /*This register stores the least 20 bits of the first out link descriptor's address.*/ + uint32_t reserved20: 8; + uint32_t stop: 1; /*Set this bit to stop dealing with the out link descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the out link descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount on new out link descriptors*/ + uint32_t park: 1; /*1： the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working.*/ }; uint32_t val; }dma_out_link; union { struct { - uint32_t inlink_addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ - uint32_t inlink_auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ - uint32_t reserved21: 7; - uint32_t inlink_stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ - uint32_t inlink_start: 1; /*Set this bit to start dealing with the in link descriptors.*/ - uint32_t inlink_restart: 1; /*Set this bit to mount on new in link descriptors*/ - uint32_t inlink_park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ + uint32_t addr: 20; /*This register stores the least 20 bits of the first in link descriptor's address.*/ + uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/ + uint32_t reserved21: 7; + uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/ + uint32_t start: 1; /*Set this bit to start dealing with the in link descriptors.*/ + uint32_t restart: 1; /*Set this bit to mount on new in link descriptors*/ + uint32_t park: 1; /*1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working*/ }; uint32_t val; }dma_in_link; union { struct { - uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ - uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ - uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ - uint32_t save_head: 1; /*Set this bit to save packet header .*/ - uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ - uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ - uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ - uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ - uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ - uint32_t dma_infifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt.*/ - uint32_t reserved21: 11; + uint32_t check_sum_en: 1; /*Set this bit to enable decoder to check check_sum in packet header.*/ + uint32_t check_seq_en: 1; /*Set this bit to enable decoder to check seq num in packet header.*/ + uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/ + uint32_t save_head: 1; /*Set this bit to save packet header .*/ + uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in packet header automatically.*/ + uint32_t tx_ack_num_re: 1; /*Set this bit to enable hardware replace ack num in packet header automatically.*/ + uint32_t check_owner: 1; /*Set this bit to check the owner bit in link descriptor.*/ + uint32_t wait_sw_start: 1; /*Set this bit to enable software way to add packet header.*/ + uint32_t sw_start: 1; /*Set this bit to start inserting the packet header.*/ + uint32_t dma_in_fifo_full_thrs:12; /*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/ + uint32_t reserved21: 11; }; uint32_t val; }conf1; @@ -219,10 +219,10 @@ typedef volatile struct { uint32_t dma_out_eof_bfr_des_addr; /*This register stores the address of out link descriptor when there are some errors in this descriptor.*/ union { struct { - uint32_t ahb_testmode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ - uint32_t reserved3: 1; - uint32_t ahb_testaddr: 2; /*The two bits represent ahb bus address bit[20:19]*/ - uint32_t reserved6: 26; + uint32_t test_mode: 3; /*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/ + uint32_t reserved3: 1; + uint32_t test_addr: 2; /*The two bits represent ahb bus address bit[20:19]*/ + uint32_t reserved6: 26; }; uint32_t val; }ahb_test; @@ -271,7 +271,7 @@ typedef volatile struct { uint32_t val; }quick_sent; struct{ - uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ + uint32_t w_data[2]; /*This register stores the content of short packet's dword*/ }q_data[7]; union { struct { @@ -284,34 +284,34 @@ typedef volatile struct { }esc_conf0; union { struct { - uint32_t esc_seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ - uint32_t esc_seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ - uint32_t esc_seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ - uint32_t reserved24: 8; + uint32_t seq0: 8; /*This register stores the first substitute char used to replace the separate char.*/ + uint32_t seq0_char0: 8; /*This register stores the first char used to replace reg_esc_seq0 in data.*/ + uint32_t seq0_char1: 8; /*This register stores the second char used to replace the reg_esc_seq0 in data*/ + uint32_t reserved24: 8; }; uint32_t val; }esc_conf1; union { struct { - uint32_t esc_seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ - uint32_t esc_seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ - uint32_t esc_seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ - uint32_t reserved24: 8; + uint32_t seq1: 8; /*This register stores the flow control char to turn on the flow_control*/ + uint32_t seq1_char0: 8; /*This register stores the first char used to replace the reg_esc_seq1 in data.*/ + uint32_t seq1_char1: 8; /*This register stores the second char used to replace the reg_esc_seq1 in data.*/ + uint32_t reserved24: 8; }; uint32_t val; }esc_conf2; union { struct { - uint32_t esc_seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ - uint32_t esc_seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ - uint32_t esc_seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ - uint32_t reserved24: 8; + uint32_t seq2: 8; /*This register stores the flow_control char to turn off the flow_control*/ + uint32_t seq2_char0: 8; /*This register stores the first char used to replace the reg_esc_seq2 in data.*/ + uint32_t seq2_char1: 8; /*This register stores the second char used to replace the reg_esc_seq2 in data.*/ + uint32_t reserved24: 8; }; uint32_t val; }esc_conf3; union { struct { - uint32_t pkt_thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ + uint32_t thrs: 13; /*when the amount of packet payload is larger than this value the process of receiving data is done.*/ uint32_t reserved13:19; }; uint32_t val; From 015ae7e0d0680c697589f5b5e05f0dcade3e9db2 Mon Sep 17 00:00:00 2001 From: Wangjialin Date: Sun, 18 Sep 2016 19:24:43 +0800 Subject: [PATCH 46/57] fix ledc and spi typo --- components/esp32/include/soc/ledc_struct.h | 2 +- components/esp32/include/soc/spi_struct.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp32/include/soc/ledc_struct.h b/components/esp32/include/soc/ledc_struct.h index 26ddf6867..40341f00e 100644 --- a/components/esp32/include/soc/ledc_struct.h +++ b/components/esp32/include/soc/ledc_struct.h @@ -180,7 +180,7 @@ typedef volatile struct { uint32_t lstimer0_ovf: 1; /*The interrupt status bit for low speed channel0 counter overflow event.*/ uint32_t lstimer1_ovf: 1; /*The interrupt status bit for low speed channel1 counter overflow event.*/ uint32_t lstimer2_ovf: 1; /*The interrupt status bit for low speed channel2 counter overflow event.*/ - uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.* uint32_t duty_chng_end_hsch0: 1; /*The interrupt status bit for high speed channel 0 duty change done event.*/ + uint32_t lstimer3_ovf: 1; /*The interrupt status bit for low speed channel3 counter overflow event.*/ uint32_t duty_chng_end_hsch1: 1; /*The interrupt status bit for high speed channel 1 duty change done event.*/ uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/ uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/ diff --git a/components/esp32/include/soc/spi_struct.h b/components/esp32/include/soc/spi_struct.h index 31b86308b..5c1c93021 100644 --- a/components/esp32/include/soc/spi_struct.h +++ b/components/esp32/include/soc/spi_struct.h @@ -420,7 +420,7 @@ typedef volatile struct { uint32_t val; }dma_status; union { - struct {_int_clr + struct { uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/ uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/ uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/ From 69278b28bfc326e3a04c2c934dd59885c0906bfe Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Sun, 18 Sep 2016 20:24:31 +0800 Subject: [PATCH 47/57] components/log: fix bugs, add options to override log level for files, components, and bootloader --- components/bootloader/Kconfig.projbuild | 28 +++++ components/log/include/esp_log.h | 65 +++++------- components/log/log.c | 134 +++++++++++++++--------- 3 files changed, 138 insertions(+), 89 deletions(-) diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 8d5f66721..394bcc1bd 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -1,3 +1,31 @@ menu "Bootloader config" +choice LOG_BOOTLOADER_LEVEL + bool "Bootloader log verbosity" + default LOG_BOOTLOADER_LEVEL_WARN + help + Specify how much output to see in bootloader logs. + +config LOG_BOOTLOADER_LEVEL_NONE + bool "No output" +config LOG_BOOTLOADER_LEVEL_ERROR + bool "Error" +config LOG_BOOTLOADER_LEVEL_WARN + bool "Warning" +config LOG_BOOTLOADER_LEVEL_INFO + bool "Info" +config LOG_BOOTLOADER_LEVEL_DEBUG + bool "Debug" +config LOG_BOOTLOADER_LEVEL_VERBOSE + bool "Verbose" +endchoice + +config LOG_BOOTLOADER_LEVEL + int + default 0 if LOG_BOOTLOADER_LEVEL_NONE + default 1 if LOG_BOOTLOADER_LEVEL_ERROR + default 2 if LOG_BOOTLOADER_LEVEL_WARN + default 3 if LOG_BOOTLOADER_LEVEL_INFO + default 4 if LOG_BOOTLOADER_LEVEL_DEBUG + default 5 if LOG_BOOTLOADER_LEVEL_VERBOSE endmenu diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h index 32f6d0bb3..a12d324de 100644 --- a/components/log/include/esp_log.h +++ b/components/log/include/esp_log.h @@ -68,8 +68,17 @@ extern "C" { * from _EARLY version to normal version on the fly. Unfortunately, ets_vprintf in ROM * has been inlined by the compiler into ets_printf, so it is not accessible outside.) * + * To override default verbosity level at file or component scope, define LOG_LOCAL_LEVEL macro. + * At file scope, define it before including esp_log.h, e.g.: * - * To configure logging output per module, add calls to esp_log_set_level function: + * #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE + * #include "esp_log.h" + * + * At component scope, define it in component makefile: + * + * CFLAGS += -D LOG_LOCAL_LEVEL=ESP_LOG_DEBUG + * + * To configure logging output per module at runtime, add calls to esp_log_set_level function: * * esp_log_set_level("*", ESP_LOG_ERROR); // set all components to ERROR level * esp_log_set_level("wifi", ESP_LOG_WARN); // enable WARN logs from WiFi stack @@ -162,68 +171,50 @@ uint32_t esp_log_timestamp(); #define LOG_RESET_COLOR #endif //CONFIG_LOG_COLORS +#ifndef LOG_LOCAL_LEVEL +#ifndef BOOTLOADER_BUILD +#define LOG_LOCAL_LEVEL ((esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL) +#else +#define LOG_LOCAL_LEVEL ((esp_log_level_t) CONFIG_LOG_BOOTLOADER_LEVEL) +#endif +#endif + #define LOG_FORMAT(letter, format) LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n" -#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_ERROR) -#define ESP_EARLY_LOGE( tag, format, ... ) ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGE( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #ifndef BOOTLOADER_BUILD -#define ESP_LOGE( tag, format, ... ) esp_log_write(ESP_LOG_ERROR, tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_LOGE( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { esp_log_write(ESP_LOG_ERROR, tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #else #define ESP_LOGE( tag, format, ... ) ESP_EARLY_LOGE( tag, format, ##__VA_ARGS__) #endif // BOOTLOADER_BUILD -#else -#define ESP_LOGE( tag, format, ... ) -#define ESP_EARLY_LOGE( tag, format, ... ) -#endif -#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_WARN) -#define ESP_EARLY_LOGW( tag, format, ... ) ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGW( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #ifndef BOOTLOADER_BUILD -#define ESP_LOGW( tag, format, ... ) esp_log_write(ESP_LOG_WARN, tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_LOGW( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { esp_log_write(ESP_LOG_WARN, tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #else #define ESP_LOGW( tag, format, ... ) ESP_EARLY_LOGW( tag, format, ##__VA_ARGS__) #endif // BOOTLOADER_BUILD -#else -#define ESP_LOGW( tag, format, ... ) -#define ESP_EARLY_LOGW( tag, format, ... ) -#endif -#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_INFO) -#define ESP_EARLY_LOGI( tag, format, ... ) ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGI( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #ifndef BOOTLOADER_BUILD -#define ESP_LOGI( tag, format, ... ) esp_log_write(ESP_LOG_INFO, tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_LOGI( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { esp_log_write(ESP_LOG_INFO, tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #else #define ESP_LOGI( tag, format, ... ) ESP_EARLY_LOGI( tag, format, ##__VA_ARGS__) #endif //BOOTLOADER_BUILD -#else -#define ESP_LOGI( tag, format, ... ) -#define ESP_EARLY_LOGI( tag, format, ... ) -#endif - -#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_DEBUG) -#define ESP_EARLY_LOGD( tag, format, ... ) ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGD( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #ifndef BOOTLOADER_BUILD -#define ESP_LOGD( tag, format, ... ) esp_log_write(ESP_LOG_DEBUG, tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_LOGD( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { esp_log_write(ESP_LOG_DEBUG, tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #else #define ESP_LOGD( tag, format, ... ) ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__) #endif // BOOTLOADER_BUILD -#else -#define ESP_LOGD( tag, format, ... ) -#define ESP_EARLY_LOGD( tag, format, ... ) -#endif -#if (CONFIG_LOG_DEFAULT_LEVEL >= ESP_LOG_VERBOSE) -#define ESP_EARLY_LOGV( tag, format, ... ) ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_EARLY_LOGV( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #ifndef BOOTLOADER_BUILD -#define ESP_LOGV( tag, format, ... ) esp_log_write(ESP_LOG_VERBOSE, tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__) +#define ESP_LOGV( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { esp_log_write(ESP_LOG_VERBOSE, tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #else #define ESP_LOGV( tag, format, ... ) ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__) #endif // BOOTLOADER_BUILD -#else -#define ESP_LOGV( tag, format, ... ) -#define ESP_EARLY_LOGV( tag, format, ... ) -#endif #ifdef __cplusplus } diff --git a/components/log/log.c b/components/log/log.c index bd6df01b2..9063d264e 100644 --- a/components/log/log.c +++ b/components/log/log.c @@ -51,13 +51,21 @@ #include #include #include +#include #include "esp_log.h" #ifndef BOOTLOADER_BUILD -#define TAG_CACHE_SIZE 32 -#define MAX_MUTEX_WAIT_TICKS ((10 + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS) +// Number of tags to be cached. Must be 2**n - 1, n >= 2. +#define TAG_CACHE_SIZE 31 + +// Maximum time to wait for the mutex in a logging statement. +#define MAX_MUTEX_WAIT_MS 10 +#define MAX_MUTEX_WAIT_TICKS ((MAX_MUTEX_WAIT_MS + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS) + +// Uncomment this to enable consistency checks and cache statistics in this file. +// #define LOG_BUILTIN_CHECKS typedef struct { const char* tag; @@ -71,14 +79,18 @@ typedef struct uncached_tag_entry_{ char tag[0]; // beginning of a zero-terminated string } uncached_tag_entry_t; -static esp_log_level_t s_default_level = (esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL; -static uncached_tag_entry_t* s_head = NULL; -static uncached_tag_entry_t* s_tail = NULL; -static cached_tag_entry_t s_cache[TAG_CACHE_SIZE]; -static uint32_t s_cache_max_generation = 0; -static uint32_t s_cache_entry_count = 0; -static vprintf_like_t s_print_func = &vprintf; -static SemaphoreHandle_t s_mutex = NULL; +static esp_log_level_t s_log_default_level = (esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL; +static uncached_tag_entry_t* s_log_tags_head = NULL; +static uncached_tag_entry_t* s_log_tags_tail = NULL; +static cached_tag_entry_t s_log_cache[TAG_CACHE_SIZE]; +static uint32_t s_log_cache_max_generation = 0; +static uint32_t s_log_cache_entry_count = 0; +static vprintf_like_t s_log_print_func = &vprintf; +static SemaphoreHandle_t s_log_mutex = NULL; + +#ifdef LOG_BUILTIN_CHECKS +static uint32_t s_log_cache_misses = 0; +#endif static inline bool get_cached_log_level(const char* tag, esp_log_level_t* level); static inline bool get_uncached_log_level(const char* tag, esp_log_level_t* level); @@ -90,21 +102,21 @@ static inline void clear_log_level_list(); void esp_log_set_vprintf(vprintf_like_t func) { - s_print_func = func; + s_log_print_func = func; } void esp_log_level_set(const char* tag, esp_log_level_t level) { - if (!s_mutex) { - s_mutex = xSemaphoreCreateMutex(); + if (!s_log_mutex) { + s_log_mutex = xSemaphoreCreateMutex(); } - xSemaphoreTake(&s_mutex, portMAX_DELAY); + xSemaphoreTake(s_log_mutex, portMAX_DELAY); // for wildcard tag, remove all linked list items and clear the cache if (strcmp(tag, "*") == 0) { - s_default_level = level; + s_log_default_level = level; clear_log_level_list(); - xSemaphoreGive(&s_mutex); + xSemaphoreGive(s_log_mutex); return; } @@ -112,60 +124,68 @@ void esp_log_level_set(const char* tag, esp_log_level_t level) size_t entry_size = offsetof(uncached_tag_entry_t, tag) + strlen(tag) + 1; uncached_tag_entry_t* new_entry = (uncached_tag_entry_t*) malloc(entry_size); if (!new_entry) { - xSemaphoreGive(&s_mutex); + xSemaphoreGive(s_log_mutex); return; } new_entry->next = NULL; new_entry->level = (uint8_t) level; strcpy(new_entry->tag, tag); - if (s_tail) { - s_tail->next = new_entry; + if (s_log_tags_tail) { + s_log_tags_tail->next = new_entry; } - s_tail = new_entry; - if (!s_head) { - s_head = new_entry; + s_log_tags_tail = new_entry; + if (!s_log_tags_head) { + s_log_tags_head = new_entry; } - xSemaphoreGive(&s_mutex); + xSemaphoreGive(s_log_mutex); } void clear_log_level_list() { - for (uncached_tag_entry_t* it = s_head; it != NULL; ) { + for (uncached_tag_entry_t* it = s_log_tags_head; it != NULL; ) { uncached_tag_entry_t* next = it->next; free(it); it = next; } + s_log_tags_tail = NULL; + s_log_tags_head = NULL; + s_log_cache_entry_count = 0; + s_log_cache_max_generation = 0; +#ifdef LOG_BUILTIN_CHECKS + s_log_cache_misses = 0; +#endif - s_cache_entry_count = 0; - s_cache_max_generation = 0; } void IRAM_ATTR esp_log_write(esp_log_level_t level, const char* tag, const char* format, ...) { - if (!s_mutex) { - s_mutex = xSemaphoreCreateMutex(); + if (!s_log_mutex) { + s_log_mutex = xSemaphoreCreateMutex(); } - if (xSemaphoreTake(&s_mutex, MAX_MUTEX_WAIT_TICKS) == pdFALSE) { + if (xSemaphoreTake(s_log_mutex, MAX_MUTEX_WAIT_TICKS) == pdFALSE) { return; } esp_log_level_t level_for_tag; // Look for the tag in cache first, then in the linked list of all tags if (!get_cached_log_level(tag, &level_for_tag)) { if (!get_uncached_log_level(tag, &level_for_tag)) { - level_for_tag = s_default_level; + level_for_tag = s_log_default_level; } add_to_cache(tag, level_for_tag); +#ifdef LOG_BUILTIN_CHECKS + ++s_log_cache_misses; +#endif } - xSemaphoreGive(&s_mutex); + xSemaphoreGive(s_log_mutex); if (!should_output(level, level_for_tag)) { return; } va_list list; va_start(list, format); - (*s_print_func)(format, list); + (*s_log_print_func)(format, list); va_end(list); } @@ -173,43 +193,53 @@ static inline bool get_cached_log_level(const char* tag, esp_log_level_t* level) { // Look for `tag` in cache int i; - for (i = 0; i < s_cache_entry_count; ++i) { - if (s_cache[i].tag == tag) { + for (i = 0; i < s_log_cache_entry_count; ++i) { +#ifdef LOG_BUILTIN_CHECKS + assert(i == 0 || s_log_cache[(i - 1) / 2].generation < s_log_cache[i].generation); +#endif + if (s_log_cache[i].tag == tag) { break; } } - if (i == s_cache_entry_count) { // Not found in cache + if (i == s_log_cache_entry_count) { // Not found in cache return false; } // Return level from cache - *level = (esp_log_level_t) s_cache[i].level; - // Update item generation - s_cache[i].generation = s_cache_max_generation++; - // Restore heap ordering - heap_bubble_down(i); + *level = (esp_log_level_t) s_log_cache[i].level; + // If cache has been filled, start taking ordering into account + // (other options are: dynamically resize cache, add "dummy" entries + // to the cache; this option was chosen because code is much simpler, + // and the unfair behavior of cache will show it self at most once, when + // it has just been filled) + if (s_log_cache_entry_count == TAG_CACHE_SIZE) { + // Update item generation + s_log_cache[i].generation = s_log_cache_max_generation++; + // Restore heap ordering + heap_bubble_down(i); + } return true; } static inline void add_to_cache(const char* tag, esp_log_level_t level) { - uint32_t generation = s_cache_max_generation++; + uint32_t generation = s_log_cache_max_generation++; // First consider the case when cache is not filled yet. // In this case, just add new entry at the end. // This happens to satisfy binary min-heap ordering. - if (s_cache_entry_count < TAG_CACHE_SIZE) { - s_cache[s_cache_entry_count] = (cached_tag_entry_t) { + if (s_log_cache_entry_count < TAG_CACHE_SIZE) { + s_log_cache[s_log_cache_entry_count] = (cached_tag_entry_t) { .generation = generation, .level = level, .tag = tag }; - ++s_cache_entry_count; + ++s_log_cache_entry_count; return; } // Cache is full, so we replace the oldest entry (which is at index 0 // because this is a min-heap) with the new one, and do bubble-down // operation to restore min-heap ordering. - s_cache[0] = (cached_tag_entry_t) { + s_log_cache[0] = (cached_tag_entry_t) { .tag = tag, .level = level, .generation = generation @@ -221,7 +251,7 @@ static inline bool get_uncached_log_level(const char* tag, esp_log_level_t* leve { // Walk the linked list of all tags and see if given tag is present in the list. // This is slow because tags are compared as strings. - for (uncached_tag_entry_t* it = s_head; it != NULL; ++it) { + for (uncached_tag_entry_t* it = s_log_tags_head; it != NULL; it = it->next) { if (strcmp(tag, it->tag) == 0) { *level = it->level; return true; @@ -240,7 +270,7 @@ static void heap_bubble_down(int index) while (index < TAG_CACHE_SIZE / 2) { int left_index = index * 2 + 1; int right_index = left_index + 1; - int next = (s_cache[left_index].generation < s_cache[right_index].generation) ? left_index : right_index; + int next = (s_log_cache[left_index].generation < s_log_cache[right_index].generation) ? left_index : right_index; heap_swap(index, next); index = next; } @@ -248,13 +278,13 @@ static void heap_bubble_down(int index) static inline void heap_swap(int i, int j) { - cached_tag_entry_t tmp = s_cache[i]; - s_cache[i] = s_cache[j]; - s_cache[j] = tmp; + cached_tag_entry_t tmp = s_log_cache[i]; + s_log_cache[i] = s_log_cache[j]; + s_log_cache[j] = tmp; } #endif //BOOTLOADER_BUILD -inline uint32_t esp_log_early_timestamp() +inline IRAM_ATTR uint32_t esp_log_early_timestamp() { return xthal_get_ccount() / (CPU_CLK_FREQ_ROM / 1000); } @@ -275,7 +305,7 @@ uint32_t IRAM_ATTR esp_log_timestamp() #else -uint32_t esp_log_timestamp() +uint32_t IRAM_ATTR esp_log_timestamp() { return esp_log_early_timestamp(); } From 3cdefd99238e1e209ef6d83b803120ff5a76db79 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Sun, 18 Sep 2016 20:51:57 +0800 Subject: [PATCH 48/57] components/log: fix error when using ESP_LOGx from C++ code --- components/log/include/esp_log.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h index a12d324de..d2097e362 100644 --- a/components/log/include/esp_log.h +++ b/components/log/include/esp_log.h @@ -154,8 +154,8 @@ uint32_t esp_log_timestamp(); #define LOG_COLOR_BLUE "34" #define LOG_COLOR_PURPLE "35" #define LOG_COLOR_CYAN "36" -#define LOG_COLOR(COLOR) "\033[0;"COLOR"m" -#define LOG_BOLD(COLOR) "\033[1;"COLOR"m" +#define LOG_COLOR(COLOR) "\033[0;" COLOR "m" +#define LOG_BOLD(COLOR) "\033[1;" COLOR "m" #define LOG_RESET_COLOR "\033[0m" #define LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED) #define LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN) From 26bf85bad6d926255f7bf0fcb483849f92b7755c Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Sun, 18 Sep 2016 21:01:28 +0800 Subject: [PATCH 49/57] components/log: set default runtime log level to ESP_LOG_VERBOSE With this change, it is possible to use LOG_LOCAL_LEVEL to raise debug level for given file/component --- components/log/log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/log/log.c b/components/log/log.c index 9063d264e..b347b20a3 100644 --- a/components/log/log.c +++ b/components/log/log.c @@ -79,7 +79,7 @@ typedef struct uncached_tag_entry_{ char tag[0]; // beginning of a zero-terminated string } uncached_tag_entry_t; -static esp_log_level_t s_log_default_level = (esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL; +static esp_log_level_t s_log_default_level = ESP_LOG_VERBOSE; static uncached_tag_entry_t* s_log_tags_head = NULL; static uncached_tag_entry_t* s_log_tags_tail = NULL; static cached_tag_entry_t s_log_cache[TAG_CACHE_SIZE]; From 1188bdfc684bda5cfc84ca239526d87509320743 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Sun, 18 Sep 2016 21:06:43 +0800 Subject: [PATCH 50/57] components/log: fix timestamp calculation --- components/log/log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/log/log.c b/components/log/log.c index b347b20a3..aae12a773 100644 --- a/components/log/log.c +++ b/components/log/log.c @@ -300,7 +300,7 @@ uint32_t IRAM_ATTR esp_log_timestamp() if (base == 0) { base = esp_log_early_timestamp(); } - return base + xTaskGetTickCount() * configTICK_RATE_HZ; + return base + xTaskGetTickCount() * (1000 / configTICK_RATE_HZ); } #else From d9338e64e5bc751003b53313912849d122259a3f Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Sun, 18 Sep 2016 23:12:50 +0800 Subject: [PATCH 51/57] gitlab-ci: allow running tests for branches, triggered via API --- .gitlab-ci.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 10a9298db..7233d9ac4 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -95,6 +95,7 @@ test_build_system: when: on_success only: - master + - triggers variables: # need user to set SDK_NAME and CONFIG_FILE (may need to set BIN_PATH and APP_NAME later) in before_script From 14e003fcf205b6b2ac2904f1faf701dc4898a49d Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 19 Sep 2016 08:53:09 +0800 Subject: [PATCH 52/57] components/log: regroup macros for better readability --- components/log/include/esp_log.h | 45 +++++++++++--------------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h index d2097e362..8ca6e241d 100644 --- a/components/log/include/esp_log.h +++ b/components/log/include/esp_log.h @@ -171,6 +171,8 @@ uint32_t esp_log_timestamp(); #define LOG_RESET_COLOR #endif //CONFIG_LOG_COLORS +#define LOG_FORMAT(letter, format) LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n" + #ifndef LOG_LOCAL_LEVEL #ifndef BOOTLOADER_BUILD #define LOG_LOCAL_LEVEL ((esp_log_level_t) CONFIG_LOG_DEFAULT_LEVEL) @@ -179,40 +181,23 @@ uint32_t esp_log_timestamp(); #endif #endif -#define LOG_FORMAT(letter, format) LOG_COLOR_ ## letter #letter " (%d) %s: " format LOG_RESET_COLOR "\n" - -#define ESP_EARLY_LOGE( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#ifndef BOOTLOADER_BUILD -#define ESP_LOGE( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { esp_log_write(ESP_LOG_ERROR, tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#else -#define ESP_LOGE( tag, format, ... ) ESP_EARLY_LOGE( tag, format, ##__VA_ARGS__) -#endif // BOOTLOADER_BUILD - -#define ESP_EARLY_LOGW( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#ifndef BOOTLOADER_BUILD -#define ESP_LOGW( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { esp_log_write(ESP_LOG_WARN, tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#else -#define ESP_LOGW( tag, format, ... ) ESP_EARLY_LOGW( tag, format, ##__VA_ARGS__) -#endif // BOOTLOADER_BUILD - -#define ESP_EARLY_LOGI( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#ifndef BOOTLOADER_BUILD -#define ESP_LOGI( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { esp_log_write(ESP_LOG_INFO, tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#else -#define ESP_LOGI( tag, format, ... ) ESP_EARLY_LOGI( tag, format, ##__VA_ARGS__) -#endif //BOOTLOADER_BUILD - -#define ESP_EARLY_LOGD( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#ifndef BOOTLOADER_BUILD -#define ESP_LOGD( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { esp_log_write(ESP_LOG_DEBUG, tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } -#else -#define ESP_LOGD( tag, format, ... ) ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__) -#endif // BOOTLOADER_BUILD - +#define ESP_EARLY_LOGE( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { ets_printf(LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } +#define ESP_EARLY_LOGW( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { ets_printf(LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } +#define ESP_EARLY_LOGI( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { ets_printf(LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } +#define ESP_EARLY_LOGD( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { ets_printf(LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #define ESP_EARLY_LOGV( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { ets_printf(LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } + #ifndef BOOTLOADER_BUILD +#define ESP_LOGE( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_ERROR) { esp_log_write(ESP_LOG_ERROR, tag, LOG_FORMAT(E, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } +#define ESP_LOGW( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_WARN) { esp_log_write(ESP_LOG_WARN, tag, LOG_FORMAT(W, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } +#define ESP_LOGI( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_INFO) { esp_log_write(ESP_LOG_INFO, tag, LOG_FORMAT(I, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } +#define ESP_LOGD( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_DEBUG) { esp_log_write(ESP_LOG_DEBUG, tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #define ESP_LOGV( tag, format, ... ) if (LOG_LOCAL_LEVEL >= ESP_LOG_VERBOSE) { esp_log_write(ESP_LOG_VERBOSE, tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); } #else +#define ESP_LOGE( tag, format, ... ) ESP_EARLY_LOGE(tag, format, ##__VA_ARGS__) +#define ESP_LOGW( tag, format, ... ) ESP_EARLY_LOGW(tag, format, ##__VA_ARGS__) +#define ESP_LOGI( tag, format, ... ) ESP_EARLY_LOGI(tag, format, ##__VA_ARGS__) +#define ESP_LOGD( tag, format, ... ) ESP_EARLY_LOGD(tag, format, ##__VA_ARGS__) #define ESP_LOGV( tag, format, ... ) ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__) #endif // BOOTLOADER_BUILD From ff2750ab07a1fe54cb821a0db79ddac116c205d8 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 19 Sep 2016 15:05:32 +0800 Subject: [PATCH 53/57] components/esp32: move peripheral symbols to separate ld script --- components/esp32/component.mk | 2 +- components/esp32/ld/esp32.peripherals.ld | 20 ++++++++++++++++++++ components/esp32/ld/esp32.rom.ld | 23 ----------------------- 3 files changed, 21 insertions(+), 24 deletions(-) create mode 100644 components/esp32/ld/esp32.peripherals.ld diff --git a/components/esp32/component.mk b/components/esp32/component.mk index e7397b2a1..d275898db 100644 --- a/components/esp32/component.mk +++ b/components/esp32/component.mk @@ -26,7 +26,7 @@ else endif endif -LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld +LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld COMPONENT_ADD_LDFLAGS := -lesp32 \ $(abspath libhal.a) \ diff --git a/components/esp32/ld/esp32.peripherals.ld b/components/esp32/ld/esp32.peripherals.ld new file mode 100644 index 000000000..aaadedce4 --- /dev/null +++ b/components/esp32/ld/esp32.peripherals.ld @@ -0,0 +1,20 @@ +PROVIDE ( UART0 = 0x3ff40000 ); +PROVIDE ( SPI1 = 0x3ff42000 ); +PROVIDE ( SPI0 = 0x3ff43000 ); +PROVIDE ( GPIO = 0x3ff44000 ); +PROVIDE ( SIGMADELTA = 0x3ff44f00 ); +PROVIDE ( UHCI1 = 0x3ff4C000 ); +PROVIDE ( I2S0 = 0x3ff4F000 ); +PROVIDE ( UART1 = 0x3ff50000 ); +PROVIDE ( I2C0 = 0x3ff53000 ); +PROVIDE ( UHCI0 = 0x3ff54000 ); +PROVIDE ( RMT = 0x3ff56000 ); +PROVIDE ( PCNT = 0x3ff57000 ); +PROVIDE ( LEDC = 0x3ff59000 ); +PROVIDE ( TIMERG0 = 0x3ff5F000 ); +PROVIDE ( TIMERG1 = 0x3ff60000 ); +PROVIDE ( SPI2 = 0x3ff64000 ); +PROVIDE ( SPI3 = 0x3ff65000 ); +PROVIDE ( I2C1 = 0x3ff67000 ); +PROVIDE ( I2S1 = 0x3ff6D000 ); +PROVIDE ( UART2 = 0x3ff6E000 ); diff --git a/components/esp32/ld/esp32.rom.ld b/components/esp32/ld/esp32.rom.ld index f8aa70631..6f9064a39 100644 --- a/components/esp32/ld/esp32.rom.ld +++ b/components/esp32/ld/esp32.rom.ld @@ -1835,26 +1835,3 @@ PROVIDE ( _xtos_syscall_handler = 0x40000790 ); PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); - -PROVIDE ( I2S0 = 0x3ff4F000 ); -PROVIDE ( I2S1 = 0x3ff6D000 ); -PROVIDE ( GPIO = 0x3ff44000 ); -PROVIDE ( SIGMADELTA = 0x3ff44f00 ); -PROVIDE ( I2C0 = 0x3ff53000 ); -PROVIDE ( I2C1 = 0x3ff67000 ); -PROVIDE ( LEDC = 0x3ff59000 ); -PROVIDE ( PCNT = 0x3ff57000 ); -PROVIDE ( RMT = 0x3ff56000 ); -PROVIDE ( SPI0 = 0x3ff43000 ); -PROVIDE ( SPI1 = 0x3ff42000 ); -PROVIDE ( SPI2 = 0x3ff64000 ); -PROVIDE ( SPI3 = 0x3ff65000 ); -PROVIDE ( TIMERG0 = 0x3ff5F000 ); -PROVIDE ( TIMERG1 = 0x3ff60000 ); -PROVIDE ( UART0 = 0x3ff40000 ); -PROVIDE ( UART1 = 0x3ff50000 ); -PROVIDE ( UART2 = 0x3ff6E000 ); -PROVIDE ( UHCI0 = 0x3ff54000 ); -PROVIDE ( UHCI1 = 0x3ff4C000 ); - - From e8ae38024d5a13c3090f1ad500e48fb2143da3e8 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 19 Sep 2016 19:28:36 +0800 Subject: [PATCH 54/57] components/freertos: override per-task __cleanup handler to close stdin, stdout, stderr Default _cleanup_r doesn't do that, which leaks these three file descriptors. --- components/esp32/syscalls.c | 17 +++++++++++++++++ components/freertos/tasks.c | 5 +++++ 2 files changed, 22 insertions(+) diff --git a/components/esp32/syscalls.c b/components/esp32/syscalls.c index 1aff0167a..350f5f410 100644 --- a/components/esp32/syscalls.c +++ b/components/esp32/syscalls.c @@ -367,6 +367,23 @@ void IRAM_ATTR _lock_release_recursive(_lock_t *lock) { lock_release_generic(lock, queueQUEUE_TYPE_RECURSIVE_MUTEX); } +// This function is not part on newlib API, it is defined in libc/stdio/local.h +// It is called as part of _reclaim_reent via a pointer in __cleanup member +// of struct _reent. +// This function doesn't call _fclose_r for _stdin, _stdout, _stderr members +// of struct reent. Not doing so causes a memory leak each time a task is +// terminated. We replace __cleanup member with _extra_cleanup_r (below) to work +// around this. +extern void _cleanup_r(struct _reent* r); + +void _extra_cleanup_r(struct _reent* r) +{ + _cleanup_r(r); + _fclose_r(r, r->_stdout); + _fclose_r(r, r->_stderr); + _fclose_r(r, r->_stdin); +} + static struct _reent s_reent; /* diff --git a/components/freertos/tasks.c b/components/freertos/tasks.c index a4595154e..ff3a0530d 100644 --- a/components/freertos/tasks.c +++ b/components/freertos/tasks.c @@ -85,6 +85,7 @@ task.h is included from an application file. */ #include "StackMacros.h" #include "portmacro.h" #include "semphr.h" +#include "sys/reent.h" /* Lint e961 and e750 are suppressed as a MISRA exception justified because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the @@ -3489,6 +3490,9 @@ TCB_t *pxNewTCB; #if ( INCLUDE_vTaskDelete == 1 ) + // TODO: move this to newlib component and provide a header file + extern void _extra_cleanup_r(struct _reent* r); + static void prvDeleteTCB( TCB_t *pxTCB ) { /* This call is required specifically for the TriCore port. It must be @@ -3500,6 +3504,7 @@ TCB_t *pxNewTCB; to the task to free any memory allocated at the application level. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { + pxTCB->xNewLib_reent.__cleanup = &_extra_cleanup_r; _reclaim_reent( &( pxTCB->xNewLib_reent ) ); } #endif /* configUSE_NEWLIB_REENTRANT */ From dcf34b1be1ba8d614aefb3b6e70f762767d89997 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 20 Sep 2016 14:18:23 +0800 Subject: [PATCH 55/57] bootloader: remove trailing newlines from log messages --- components/bootloader/src/main/flash_encrypt.c | 10 +++++----- components/bootloader/src/main/secure_boot.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/components/bootloader/src/main/flash_encrypt.c b/components/bootloader/src/main/flash_encrypt.c index 4b5674f21..26e66aa03 100644 --- a/components/bootloader/src/main/flash_encrypt.c +++ b/components/bootloader/src/main/flash_encrypt.c @@ -106,7 +106,7 @@ bool flash_encrypt(bootloader_state_t *bs) uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_FLASH_CRYPT_CNT); uint8_t count = bitcount(flash_crypt_cnt); int i = 0; - ESP_LOGD(TAG, "flash encrypt cnt %x, bitcount %d\n", flash_crypt_cnt, count); + ESP_LOGD(TAG, "flash encrypt cnt %x, bitcount %d", flash_crypt_cnt, count); if ((count % 2) == 0) { boot_cache_redirect( 0, 64*1024); @@ -135,7 +135,7 @@ bool flash_encrypt(bootloader_state_t *bs) /* encrypt write factory bin */ if(bs->factory.offset != 0x00) { - ESP_LOGD(TAG, "have factory bin\n"); + ESP_LOGD(TAG, "have factory bin"); boot_cache_redirect(bs->factory.offset, bs->factory.size); bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->factory.offset&0xffff)); if(bin_len != 0) { @@ -147,7 +147,7 @@ bool flash_encrypt(bootloader_state_t *bs) } /* encrypt write test bin */ if(bs->test.offset != 0x00) { - ESP_LOGD(TAG, "have test bin\n"); + ESP_LOGD(TAG, "have test bin"); boot_cache_redirect(bs->test.offset, bs->test.size); bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->test.offset&0xffff)); if(bin_len != 0) { @@ -160,7 +160,7 @@ bool flash_encrypt(bootloader_state_t *bs) /* encrypt write ota bin */ for (i = 0;i<16;i++) { if(bs->ota[i].offset != 0x00) { - ESP_LOGD(TAG, "have ota[%d] bin\n",i); + ESP_LOGD(TAG, "have ota[%d] bin",i); boot_cache_redirect(bs->ota[i].offset, bs->ota[i].size); bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->ota[i].offset&0xffff)); if(bin_len != 0) { @@ -180,7 +180,7 @@ bool flash_encrypt(bootloader_state_t *bs) REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */ REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */ - ESP_LOGW(TAG, "burn flash_crypt_cnt\n"); + ESP_LOGW(TAG, "burn flash_crypt_cnt"); REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */ REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */ diff --git a/components/bootloader/src/main/secure_boot.c b/components/bootloader/src/main/secure_boot.c index 64332ff4e..3dfdbd141 100644 --- a/components/bootloader/src/main/secure_boot.c +++ b/components/bootloader/src/main/secure_boot.c @@ -117,11 +117,11 @@ bool secure_boot(void){ REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */ REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */ - ESP_LOGW(TAG, "burn abstract_done_0\n"); + ESP_LOGW(TAG, "burn abstract_done_0"); REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */ REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */ while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */ - ESP_LOGI(TAG, "read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6_REG)); + ESP_LOGI(TAG, "read EFUSE_BLK0_RDATA6 %x", REG_READ(EFUSE_BLK0_RDATA6_REG)); return true; } From 316d3f9c4a82d2511521946533f0497215036f28 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 20 Sep 2016 15:36:55 +0800 Subject: [PATCH 56/57] components/lwip: make SO_REUSE configurable via menuconfig Not all environments need or can work with SO_REUSE enabled, so making this option configurable. --- components/lwip/Kconfig | 7 +++++++ components/lwip/include/lwip/port/lwipopts.h | 4 +++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig index 8f38ba931..911db6fff 100644 --- a/components/lwip/Kconfig +++ b/components/lwip/Kconfig @@ -16,6 +16,13 @@ config LWIP_THREAD_LOCAL_STORAGE_INDEX Specify the thread-local-storage-pointer index for lwip use. +config LWIP_SO_REUSE + bool "Enable SO_REUSEADDR option" + default 0 + help + Enabling this option allows to bind to a port which remains in + TIME_WAIT. + endmenu diff --git a/components/lwip/include/lwip/port/lwipopts.h b/components/lwip/include/lwip/port/lwipopts.h index 99520f1cd..2c24b2be9 100755 --- a/components/lwip/include/lwip/port/lwipopts.h +++ b/components/lwip/include/lwip/port/lwipopts.h @@ -34,6 +34,7 @@ #include #include "esp_task.h" +#include "sdkconfig.h" /* Enable all Espressif-only options */ #define LWIP_ESP8266 @@ -404,8 +405,9 @@ extern unsigned char misc_prof_get_tcp_snd_buf(void); /** * SO_REUSE==1: Enable SO_REUSEADDR option. + * This option is set via menuconfig. */ -#define SO_REUSE 1 +#define SO_REUSE CONFIG_LWIP_SO_REUSE /* ---------------------------------------- From 3b22173a938926a5d60a561e1e80ba6029012cf4 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Tue, 20 Sep 2016 16:53:56 +0800 Subject: [PATCH 57/57] components/lwip: fix grammar --- components/lwip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig index 911db6fff..ceb1453f9 100644 --- a/components/lwip/Kconfig +++ b/components/lwip/Kconfig @@ -20,7 +20,7 @@ config LWIP_SO_REUSE bool "Enable SO_REUSEADDR option" default 0 help - Enabling this option allows to bind to a port which remains in + Enabling this option allows binding to a port which remains in TIME_WAIT. endmenu