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xtensa: make XTHAL_GET_INTERRUPT, XTHAL_GET_CCOUNT volatile

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INTERRUPT and CCOUNT registers will change outside of program control.
Making the inline assembly used to read these registers volatile
indicates this fact to the compiler.

Fixes https://github.com/espressif/esp-idf/issues/2127
This commit is contained in:
Ivan Grokhotkov 2018-07-02 11:31:19 +08:00
parent a8fa4201b9
commit da179e0098
1 changed files with 2 additions and 2 deletions
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4
components/esp32/include/xtensa/core-macros.h
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@ -335,7 +335,7 @@
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
} while(0)
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
__asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
__asm__ __volatile__("rsr.interrupt %0" : "=a"(__interrupt)); \
__interrupt; })
# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
@ -344,7 +344,7 @@
__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_GET_CCOUNT() ({ int __ccount; \
__asm__("rsr.ccount %0" : "=a"(__ccount)); \
__asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
__ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \