Merge branch 'feature/efuse_add_voltage_level' into 'master'
feature(efuse): add support for setting core voltage in high performance cases See merge request idf/esp-idf!4124
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commit
d96f6d6b12
2 changed files with 47 additions and 12 deletions
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@ -205,12 +205,28 @@
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF
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#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
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/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */
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/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO)
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BIT[27] is the sign bit, 0: + , 1: -
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BIT[26:24] is the difference value, unit: 0.017V
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volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */
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#define EFUSE_RD_DIG_VOL_L6 0x0F
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#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
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#define EFUSE_RD_DIG_VOL_L6_V 0x0F
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#define EFUSE_RD_DIG_VOL_L6_S 24
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/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
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/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
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0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/
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#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
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#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
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#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
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#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
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/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
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/*description: */
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#define EFUSE_RD_INST_CONFIG 0x000000FF
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#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))
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#define EFUSE_RD_INST_CONFIG_V 0xFF
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#define EFUSE_RD_INST_CONFIG_S 20
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/* Deprecated */
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#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/
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#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/
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#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/
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#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/
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/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
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/*description: read for SPI_pad_config_cs0*/
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#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F
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@ -464,12 +480,28 @@
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#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S))
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#define EFUSE_FLASH_CRYPT_CONFIG_V 0xF
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#define EFUSE_FLASH_CRYPT_CONFIG_S 28
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/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */
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/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W)
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BIT[27] is the sign bit, 0: + , 1: -
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BIT[26:24] is the difference value, unit: 0.017V
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volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */
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#define EFUSE_DIG_VOL_L6 0x0F
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#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
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#define EFUSE_DIG_VOL_L6_V 0x0F
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#define EFUSE_DIG_VOL_L6_S 24
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/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */
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/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
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0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/
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#define EFUSE_VOL_LEVEL_HP_INV 0x03
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#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
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#define EFUSE_VOL_LEVEL_HP_INV_V 0x03
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#define EFUSE_VOL_LEVEL_HP_INV_S 22
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/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
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/*description: */
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#define EFUSE_INST_CONFIG 0x000000FF
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#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))
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#define EFUSE_INST_CONFIG_V 0xFF
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#define EFUSE_INST_CONFIG_S 20
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/* Deprecated */
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#define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/
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#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/
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#define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/
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#define EFUSE_INST_CONFIG_S 20 /** Deprecated **/
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/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
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/*description: program for SPI_pad_config_cs0*/
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#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F
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@ -85,13 +85,16 @@
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/* Core voltage needs to be increased in two cases:
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* 1. running at 240 MHz
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* 2. running with 80MHz Flash frequency
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*
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* There is a record in efuse which indicates the proper voltage for these two cases.
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*/
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#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
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#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
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#else
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
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#endif
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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