esp32s2: add more unit test for esp32s2
Most of the test cases are copied from esp32 add int_alloc test add delay test add random test
This commit is contained in:
parent
783779c870
commit
d70961ad58
5 changed files with 437 additions and 11 deletions
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@ -4,11 +4,7 @@
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#include <esp_types.h>
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#include <esp_types.h>
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#include <stdio.h>
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#include <stdio.h>
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#include "esp32/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#endif
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#include "freertos/FreeRTOS.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/semphr.h"
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@ -187,22 +183,22 @@ void local_timer_test(void)
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}
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}
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TEST_CASE("Intr_alloc test, CPU-local int source", "[esp32]")
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TEST_CASE("Intr_alloc test, CPU-local int source", "[intr_alloc]")
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{
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{
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local_timer_test();
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local_timer_test();
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}
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}
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TEST_CASE("Intr_alloc test, private ints", "[esp32]")
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TEST_CASE("Intr_alloc test, private ints", "[intr_alloc]")
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{
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{
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timer_test(0);
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timer_test(0);
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}
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}
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TEST_CASE("Intr_alloc test, shared ints", "[esp32]")
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TEST_CASE("Intr_alloc test, shared ints", "[intr_alloc]")
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{
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{
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timer_test(ESP_INTR_FLAG_SHARED);
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timer_test(ESP_INTR_FLAG_SHARED);
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}
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}
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TEST_CASE("Can allocate IRAM int only with an IRAM handler", "[esp32]")
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TEST_CASE("Can allocate IRAM int only with an IRAM handler", "[intr_alloc]")
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{
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{
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void dummy(void* arg)
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void dummy(void* arg)
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{
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{
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@ -261,7 +257,7 @@ void IRAM_ATTR int_handler2(void* arg)
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}
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}
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}
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}
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TEST_CASE("allocate 2 handlers for a same source and remove the later one","[esp32]")
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TEST_CASE("allocate 2 handlers for a same source and remove the later one","[intr_alloc]")
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{
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{
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intr_alloc_test_ctx_t ctx = {false, false, false, false };
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intr_alloc_test_ctx_t ctx = {false, false, false, false };
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intr_handle_t handle1, handle2;
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intr_handle_t handle1, handle2;
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@ -328,7 +324,7 @@ void isr_alloc_free_test(void)
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printf("test passed\n");
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printf("test passed\n");
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}
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}
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TEST_CASE("alloc and free isr handle on different core", "[esp32]")
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TEST_CASE("alloc and free isr handle on different core", "[intr_alloc]")
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{
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{
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isr_alloc_free_test();
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isr_alloc_free_test();
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}
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}
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73
components/esp32s2/test/test_delay.c
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73
components/esp32s2/test/test_delay.c
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@ -0,0 +1,73 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <time.h>
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#include <sys/time.h>
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#include "esp32s2/rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "unity.h"
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#include "test_utils.h"
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typedef struct {
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int delay_us;
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int method;
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int result;
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SemaphoreHandle_t done;
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} delay_test_arg_t;
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static void test_delay_task(void *p)
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{
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delay_test_arg_t *arg = (delay_test_arg_t *)p;
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vTaskDelay(1);
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uint64_t start = ref_clock_get();
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switch (arg->method) {
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case 0:
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ets_delay_us(arg->delay_us);
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break;
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case 1:
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vTaskDelay(arg->delay_us / portTICK_PERIOD_MS / 1000);
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break;
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default:
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TEST_FAIL();
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}
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uint64_t stop = ref_clock_get();
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arg->result = (int)(stop - start);
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xSemaphoreGive(arg->done);
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vTaskDelete(NULL);
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}
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TEST_CASE("ets_delay produces correct delay", "[delay]")
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{
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int delay_ms = 50;
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const delay_test_arg_t args = {
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.delay_us = delay_ms * 1000,
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.method = 0,
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.done = xSemaphoreCreateBinary()
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};
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ref_clock_init();
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xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void *)&args, 3, NULL, 0);
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TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS));
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TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
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ref_clock_deinit();
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vSemaphoreDelete(args.done);
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}
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TEST_CASE("vTaskDelay produces correct delay", "[delay]")
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{
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int delay_ms = 50;
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const delay_test_arg_t args = {
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.delay_us = delay_ms * 1000,
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.method = 1,
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.done = xSemaphoreCreateBinary()
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};
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ref_clock_init();
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xTaskCreatePinnedToCore(test_delay_task, "", 2048, (void *)&args, 3, NULL, 0);
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TEST_ASSERT(xSemaphoreTake(args.done, delay_ms * 2 / portTICK_PERIOD_MS));
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TEST_ASSERT_INT32_WITHIN(1000, args.delay_us, args.result);
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ref_clock_deinit();
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vSemaphoreDelete(args.done);
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}
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291
components/esp32s2/test/test_intr_alloc.c
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291
components/esp32s2/test/test_intr_alloc.c
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/*
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Tests for the interrupt allocator.
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*/
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#include <stdio.h>
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#include "unity.h"
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#include "esp_types.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "soc/uart_periph.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_periph.h"
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#include "esp_intr_alloc.h"
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#include "driver/periph_ctrl.h"
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#include "driver/timer.h"
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#define TIMER_DIVIDER 16 /*!< Hardware timer clock divider */
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#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */
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#define TIMER_INTERVAL0_SEC (3.4179) /*!< test interval for timer 0 */
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#define TIMER_INTERVAL1_SEC (5.78) /*!< test interval for timer 1 */
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static void my_timer_init(int timer_group, int timer_idx, int ival)
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{
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timer_config_t config;
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config.alarm_en = 1;
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config.auto_reload = 1;
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config.counter_dir = TIMER_COUNT_UP;
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config.divider = TIMER_DIVIDER;
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config.intr_type = TIMER_INTR_LEVEL;
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config.counter_en = TIMER_PAUSE;
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/*Configure timer*/
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timer_init(timer_group, timer_idx, &config);
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/*Stop timer counter*/
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timer_pause(timer_group, timer_idx);
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/*Load counter value */
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timer_set_counter_value(timer_group, timer_idx, 0x00000000ULL);
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/*Set alarm value*/
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timer_set_alarm_value(timer_group, timer_idx, ival);
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/*Enable timer interrupt*/
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timer_enable_intr(timer_group, timer_idx);
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}
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static volatile int count[4] = {0, 0, 0, 0};
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static void timer_isr(void *arg)
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{
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int timer_idx = (int)arg;
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count[timer_idx]++;
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if (timer_idx == 0) {
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timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_0);
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timer_group_enable_alarm_in_isr(TIMER_GROUP_0, TIMER_0);
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}
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if (timer_idx == 1) {
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timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_1);
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timer_group_enable_alarm_in_isr(TIMER_GROUP_0, TIMER_1);
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}
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if (timer_idx == 2) {
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timer_group_clr_intr_status_in_isr(TIMER_GROUP_1, TIMER_0);
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timer_group_enable_alarm_in_isr(TIMER_GROUP_1, TIMER_0);
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}
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if (timer_idx == 3) {
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timer_group_clr_intr_status_in_isr(TIMER_GROUP_1, TIMER_1);
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timer_group_enable_alarm_in_isr(TIMER_GROUP_1, TIMER_1);
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}
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}
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static void timer_test(int flags)
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{
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int x;
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timer_isr_handle_t inth[4];
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my_timer_init(TIMER_GROUP_0, TIMER_0, 110000);
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my_timer_init(TIMER_GROUP_0, TIMER_1, 120000);
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my_timer_init(TIMER_GROUP_1, TIMER_0, 130000);
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my_timer_init(TIMER_GROUP_1, TIMER_1, 140000);
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timer_isr_register(TIMER_GROUP_0, TIMER_0, timer_isr, (void *)0, flags | ESP_INTR_FLAG_INTRDISABLED, &inth[0]);
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timer_isr_register(TIMER_GROUP_0, TIMER_1, timer_isr, (void *)1, flags, &inth[1]);
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timer_isr_register(TIMER_GROUP_1, TIMER_0, timer_isr, (void *)2, flags, &inth[2]);
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timer_isr_register(TIMER_GROUP_1, TIMER_1, timer_isr, (void *)3, flags, &inth[3]);
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timer_start(TIMER_GROUP_0, TIMER_0);
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timer_start(TIMER_GROUP_0, TIMER_1);
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timer_start(TIMER_GROUP_1, TIMER_0);
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timer_start(TIMER_GROUP_1, TIMER_1);
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for (x = 0; x < 4; x++) {
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count[x] = 0;
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}
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printf("Interrupts allocated: %d (dis) %d %d %d\n",
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esp_intr_get_intno(inth[0]), esp_intr_get_intno(inth[1]),
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esp_intr_get_intno(inth[2]), esp_intr_get_intno(inth[3]));
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printf("Timer values on start: %d %d %d %d\n", count[0], count[1], count[2], count[3]);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer values after 1 sec: %d %d %d %d\n", count[0], count[1], count[2], count[3]);
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TEST_ASSERT(count[0] == 0);
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TEST_ASSERT(count[1] != 0);
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TEST_ASSERT(count[2] != 0);
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TEST_ASSERT(count[3] != 0);
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printf("Disabling timers 1 and 2...\n");
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esp_intr_enable(inth[0]);
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esp_intr_disable(inth[1]);
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esp_intr_disable(inth[2]);
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for (x = 0; x < 4; x++) {
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count[x] = 0;
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}
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer values after 1 sec: %d %d %d %d\n", count[0], count[1], count[2], count[3]);
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TEST_ASSERT(count[0] != 0);
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TEST_ASSERT(count[1] == 0);
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TEST_ASSERT(count[2] == 0);
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TEST_ASSERT(count[3] != 0);
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printf("Disabling other half...\n");
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esp_intr_enable(inth[1]);
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esp_intr_enable(inth[2]);
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esp_intr_disable(inth[0]);
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esp_intr_disable(inth[3]);
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for (x = 0; x < 4; x++) {
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count[x] = 0;
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}
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer values after 1 sec: %d %d %d %d\n", count[0], count[1], count[2], count[3]);
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TEST_ASSERT(count[0] == 0);
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TEST_ASSERT(count[1] != 0);
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TEST_ASSERT(count[2] != 0);
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TEST_ASSERT(count[3] == 0);
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printf("Done.\n");
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esp_intr_free(inth[0]);
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esp_intr_free(inth[1]);
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esp_intr_free(inth[2]);
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esp_intr_free(inth[3]);
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}
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static volatile int int_timer_ctr;
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void int_timer_handler(void *arg)
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{
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xthal_set_ccompare(1, xthal_get_ccount() + 8000000);
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int_timer_ctr++;
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}
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void local_timer_test(void)
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{
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intr_handle_t ih;
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esp_err_t r;
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r = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, 0, int_timer_handler, NULL, &ih);
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TEST_ASSERT(r == ESP_OK);
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printf("Int timer 1 intno %d\n", esp_intr_get_intno(ih));
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xthal_set_ccompare(1, xthal_get_ccount() + 8000000);
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int_timer_ctr = 0;
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer val after 1 sec: %d\n", int_timer_ctr);
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TEST_ASSERT(int_timer_ctr != 0);
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printf("Disabling int\n");
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esp_intr_disable(ih);
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int_timer_ctr = 0;
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer val after 1 sec: %d\n", int_timer_ctr);
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TEST_ASSERT(int_timer_ctr == 0);
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printf("Re-enabling\n");
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esp_intr_enable(ih);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer val after 1 sec: %d\n", int_timer_ctr);
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TEST_ASSERT(int_timer_ctr != 0);
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printf("Free int, re-alloc disabled\n");
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r = esp_intr_free(ih);
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TEST_ASSERT(r == ESP_OK);
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r = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, ESP_INTR_FLAG_INTRDISABLED, int_timer_handler, NULL, &ih);
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TEST_ASSERT(r == ESP_OK);
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int_timer_ctr = 0;
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer val after 1 sec: %d\n", int_timer_ctr);
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TEST_ASSERT(int_timer_ctr == 0);
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printf("Re-enabling\n");
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esp_intr_enable(ih);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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printf("Timer val after 1 sec: %d\n", int_timer_ctr);
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TEST_ASSERT(int_timer_ctr != 0);
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r = esp_intr_free(ih);
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TEST_ASSERT(r == ESP_OK);
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printf("Done.\n");
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}
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TEST_CASE("Intr_alloc test, CPU-local int source", "[intr_alloc]")
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{
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local_timer_test();
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}
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TEST_CASE("Intr_alloc test, private ints", "[intr_alloc]")
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{
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timer_test(0);
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}
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TEST_CASE("Intr_alloc test, shared ints", "[intr_alloc]")
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{
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timer_test(ESP_INTR_FLAG_SHARED);
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}
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TEST_CASE("Can allocate IRAM int only with an IRAM handler", "[intr_alloc]")
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{
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||||||
|
void dummy(void *arg) {
|
||||||
|
}
|
||||||
|
IRAM_ATTR void dummy_iram(void *arg) {
|
||||||
|
}
|
||||||
|
RTC_IRAM_ATTR void dummy_rtc(void *arg) {
|
||||||
|
}
|
||||||
|
intr_handle_t ih;
|
||||||
|
esp_err_t err = esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE,
|
||||||
|
ESP_INTR_FLAG_IRAM, &dummy, NULL, &ih);
|
||||||
|
TEST_ASSERT_EQUAL_INT(ESP_ERR_INVALID_ARG, err);
|
||||||
|
err = esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE,
|
||||||
|
ESP_INTR_FLAG_IRAM, &dummy_iram, NULL, &ih);
|
||||||
|
TEST_ESP_OK(err);
|
||||||
|
err = esp_intr_free(ih);
|
||||||
|
TEST_ESP_OK(err);
|
||||||
|
err = esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE,
|
||||||
|
ESP_INTR_FLAG_IRAM, &dummy_rtc, NULL, &ih);
|
||||||
|
TEST_ESP_OK(err);
|
||||||
|
err = esp_intr_free(ih);
|
||||||
|
TEST_ESP_OK(err);
|
||||||
|
}
|
||||||
|
|
||||||
|
#include "soc/spi_periph.h"
|
||||||
|
typedef struct {
|
||||||
|
bool flag1;
|
||||||
|
bool flag2;
|
||||||
|
bool flag3;
|
||||||
|
bool flag4;
|
||||||
|
} intr_alloc_test_ctx_t;
|
||||||
|
|
||||||
|
void IRAM_ATTR int_handler1(void *arg)
|
||||||
|
{
|
||||||
|
intr_alloc_test_ctx_t *ctx = (intr_alloc_test_ctx_t *)arg;
|
||||||
|
ets_printf("handler 1 called.\n");
|
||||||
|
if (ctx->flag1) {
|
||||||
|
ctx->flag3 = true;
|
||||||
|
} else {
|
||||||
|
ctx->flag1 = true;
|
||||||
|
}
|
||||||
|
GPSPI2.slave.trans_done = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void IRAM_ATTR int_handler2(void *arg)
|
||||||
|
{
|
||||||
|
intr_alloc_test_ctx_t *ctx = (intr_alloc_test_ctx_t *)arg;
|
||||||
|
ets_printf("handler 2 called.\n");
|
||||||
|
if (ctx->flag2) {
|
||||||
|
ctx->flag4 = true;
|
||||||
|
} else {
|
||||||
|
ctx->flag2 = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
TEST_CASE("allocate 2 handlers for a same source and remove the later one", "[intr_alloc]")
|
||||||
|
{
|
||||||
|
intr_alloc_test_ctx_t ctx = {false, false, false, false};
|
||||||
|
intr_handle_t handle1, handle2;
|
||||||
|
|
||||||
|
//enable SPI2
|
||||||
|
periph_module_enable(PERIPH_FSPI_MODULE);
|
||||||
|
|
||||||
|
esp_err_t r;
|
||||||
|
r = esp_intr_alloc(ETS_SPI2_INTR_SOURCE, ESP_INTR_FLAG_SHARED, int_handler1, &ctx, &handle1);
|
||||||
|
TEST_ESP_OK(r);
|
||||||
|
//try an invalid assign first
|
||||||
|
r = esp_intr_alloc(ETS_SPI2_INTR_SOURCE, 0, int_handler2, NULL, &handle2);
|
||||||
|
TEST_ASSERT_EQUAL_INT(r, ESP_ERR_NOT_FOUND);
|
||||||
|
//assign shared then
|
||||||
|
r = esp_intr_alloc(ETS_SPI2_INTR_SOURCE, ESP_INTR_FLAG_SHARED, int_handler2, &ctx, &handle2);
|
||||||
|
TEST_ESP_OK(r);
|
||||||
|
GPSPI2.slave.int_trans_done_en = 1;
|
||||||
|
|
||||||
|
printf("trigger first time.\n");
|
||||||
|
GPSPI2.slave.trans_done = 1;
|
||||||
|
|
||||||
|
vTaskDelay(100);
|
||||||
|
TEST_ASSERT(ctx.flag1 && ctx.flag2);
|
||||||
|
|
||||||
|
printf("remove intr 1.\n");
|
||||||
|
r = esp_intr_free(handle2);
|
||||||
|
|
||||||
|
printf("trigger second time.\n");
|
||||||
|
GPSPI2.slave.trans_done = 1;
|
||||||
|
|
||||||
|
vTaskDelay(500);
|
||||||
|
TEST_ASSERT(ctx.flag3 && !ctx.flag4);
|
||||||
|
printf("test passed.\n");
|
||||||
|
}
|
66
components/esp32s2/test/test_random.c
Normal file
66
components/esp32s2/test/test_random.c
Normal file
|
@ -0,0 +1,66 @@
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include "unity.h"
|
||||||
|
#include "esp_system.h"
|
||||||
|
|
||||||
|
/* Note: these are just sanity tests, not the same as
|
||||||
|
entropy tests
|
||||||
|
*/
|
||||||
|
|
||||||
|
TEST_CASE("call esp_random()", "[random]")
|
||||||
|
{
|
||||||
|
const size_t NUM_RANDOM = 128; /* in most cases this is massive overkill */
|
||||||
|
|
||||||
|
uint32_t zeroes = UINT32_MAX;
|
||||||
|
uint32_t ones = 0;
|
||||||
|
for (int i = 0; i < NUM_RANDOM - 1; i++) {
|
||||||
|
uint32_t r = esp_random();
|
||||||
|
ones |= r;
|
||||||
|
zeroes &= ~r;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* assuming a 'white' random distribution, we can expect
|
||||||
|
usually at least one time each bit will be zero and at
|
||||||
|
least one time each will be one. Statistically this
|
||||||
|
can still fail, just *very* unlikely to. */
|
||||||
|
TEST_ASSERT_EQUAL_HEX32(0, zeroes);
|
||||||
|
TEST_ASSERT_EQUAL_HEX32(UINT32_MAX, ones);
|
||||||
|
}
|
||||||
|
|
||||||
|
TEST_CASE("call esp_fill_random()", "[random]")
|
||||||
|
{
|
||||||
|
const size_t NUM_BUF = 200;
|
||||||
|
const size_t BUF_SZ = 16;
|
||||||
|
uint8_t buf[NUM_BUF][BUF_SZ];
|
||||||
|
uint8_t zero_buf[BUF_SZ];
|
||||||
|
uint8_t one_buf[BUF_SZ];
|
||||||
|
|
||||||
|
bzero(buf, sizeof(buf));
|
||||||
|
bzero(one_buf, sizeof(zero_buf));
|
||||||
|
memset(zero_buf, 0xFF, sizeof(one_buf));
|
||||||
|
|
||||||
|
for (int i = 0; i < NUM_BUF; i++) {
|
||||||
|
esp_fill_random(buf[i], BUF_SZ);
|
||||||
|
}
|
||||||
|
/* No two 128-bit buffers should be the same
|
||||||
|
(again, statistically this could happen but it's very unlikely) */
|
||||||
|
for (int i = 0; i < NUM_BUF; i++) {
|
||||||
|
for (int j = 0; j < NUM_BUF; j++) {
|
||||||
|
if (i != j) {
|
||||||
|
TEST_ASSERT_NOT_EQUAL(0, memcmp(buf[i], buf[j], BUF_SZ));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Do the same all bits are zero and one at least once test across the buffers */
|
||||||
|
for (int i = 0; i < NUM_BUF; i++) {
|
||||||
|
for (int x = 0; x < BUF_SZ; x++) {
|
||||||
|
zero_buf[x] &= ~buf[i][x];
|
||||||
|
one_buf[x] |= buf[i][x];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (int x = 0; x < BUF_SZ; x++) {
|
||||||
|
TEST_ASSERT_EQUAL_HEX8(0, zero_buf[x]);
|
||||||
|
TEST_ASSERT_EQUAL_HEX8(0xFF, one_buf[x]);
|
||||||
|
}
|
||||||
|
}
|
|
@ -539,7 +539,7 @@ UT_034:
|
||||||
|
|
||||||
UT_035:
|
UT_035:
|
||||||
extends: .unit_test_s2_template
|
extends: .unit_test_s2_template
|
||||||
parallel: 36
|
parallel: 38
|
||||||
tags:
|
tags:
|
||||||
- ESP32S2_IDF
|
- ESP32S2_IDF
|
||||||
- UT_T1_1
|
- UT_T1_1
|
||||||
|
|
Loading…
Reference in a new issue