diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c
index 79f9f23da..8c2948553 100644
--- a/components/soc/esp32/rtc_clk.c
+++ b/components/soc/esp32/rtc_clk.c
@@ -39,10 +39,16 @@
 #define RTC_SLOW_CLK_FREQ_8MD256    (RTC_FAST_CLK_FREQ_8M / 256)
 #define RTC_SLOW_CLK_FREQ_32K       32768
 
+/* BBPLL configuration values */
 #define BBPLL_ENDIV5_VAL_320M       0x43
 #define BBPLL_BBADC_DSMP_VAL_320M   0x84
 #define BBPLL_ENDIV5_VAL_480M       0xc3
 #define BBPLL_BBADC_DSMP_VAL_480M   0x74
+#define BBPLL_IR_CAL_DELAY_VAL      0x18
+#define BBPLL_IR_CAL_EXT_CAP_VAL    0x20
+#define BBPLL_OC_ENB_FCAL_VAL       0x9a
+#define BBPLL_OC_ENB_VCON_VAL       0x00
+#define BBPLL_BBADC_CAL_7_0_VAL     0x00
 
 #define APLL_SDM_STOP_VAL_1         0x09
 #define APLL_SDM_STOP_VAL_2_REV0    0x69
@@ -429,6 +435,13 @@ static void rtc_clk_bbpll_enable()
     CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
              RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
              RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
+
+    /* reset BBPLL configuration */
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
 }
 
 /**