driver(ledc): fix ledc fade API and update the register header file
1. fix error when fading is too fast 2. fix error when setting duty and update immediately 3. update register header file to be in accord with TRM closes https://github.com/espressif/esp-idf/issues/2903
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Wangjialin
parent
097597b978
commit
d518a19d95
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@ -649,6 +649,10 @@ static esp_err_t _ledc_set_fade_with_time(ledc_mode_t speed_mode, ledc_channel_t
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} else {
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cycle_num = 1;
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scale = duty_delta / total_cycles;
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if (scale > LEDC_DUTY_SCALE_HSCH0_V) {
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ESP_LOGW(LEDC_TAG, LEDC_FADE_TOO_FAST_STR);
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scale = LEDC_DUTY_SCALE_HSCH0_V;
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}
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}
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return _ledc_set_fade_with_step(speed_mode, channel, target_duty, scale, cycle_num);
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}
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@ -739,14 +743,9 @@ esp_err_t ledc_set_duty_and_update(ledc_mode_t speed_mode, ledc_channel_t channe
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LEDC_ARG_CHECK(channel < LEDC_CHANNEL_MAX, "channel");
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LEDC_ARG_CHECK(duty <= ledc_get_max_duty(speed_mode, channel), "target_duty");
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LEDC_CHECK(ledc_fade_channel_init_check(speed_mode, channel) == ESP_OK , LEDC_FADE_INIT_ERROR_STR, ESP_FAIL);
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uint32_t cur_duty = ledc_get_duty(speed_mode, channel);
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if (duty == cur_duty) {
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return ESP_OK;
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}
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_ledc_op_lock_acquire(speed_mode, channel);
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_ledc_fade_hw_acquire(speed_mode, channel);
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int scale = cur_duty > duty ? cur_duty - duty : duty - cur_duty;
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_ledc_set_fade_with_step(speed_mode, channel, duty, scale, 1);
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_ledc_set_fade_with_step(speed_mode, channel, duty, 0, 1);
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_ledc_fade_start(speed_mode, channel, LEDC_FADE_WAIT_DONE);
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_ledc_fade_hw_release(speed_mode, channel);
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_ledc_op_lock_release(speed_mode, channel);
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@ -1469,10 +1469,15 @@
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/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER0_LIM 0x0000001F
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#define LEDC_HSTIMER0_LIM_M ((LEDC_HSTIMER0_LIM_V)<<(LEDC_HSTIMER0_LIM_S))
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#define LEDC_HSTIMER0_LIM_V 0x1F
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#define LEDC_HSTIMER0_LIM_S 0
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#define LEDC_HSTIMER0_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
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#define LEDC_HSTIMER0_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER0_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER0_LIM LEDC_HSTIMER0_DUTY_RES
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#define LEDC_HSTIMER0_LIM_M LEDC_HSTIMER0_DUTY_RES_M
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#define LEDC_HSTIMER0_LIM_V LEDC_HSTIMER0_DUTY_RES_V
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#define LEDC_HSTIMER0_LIM_S LEDC_HSTIMER0_DUTY_RES_S
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#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)
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/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1513,10 +1518,15 @@
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/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer1. the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER1_LIM 0x0000001F
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#define LEDC_HSTIMER1_LIM_M ((LEDC_HSTIMER1_LIM_V)<<(LEDC_HSTIMER1_LIM_S))
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#define LEDC_HSTIMER1_LIM_V 0x1F
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#define LEDC_HSTIMER1_LIM_S 0
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#define LEDC_HSTIMER1_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
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#define LEDC_HSTIMER1_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER1_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER1_LIM LEDC_HSTIMER1_DUTY_RES
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#define LEDC_HSTIMER1_LIM_M LEDC_HSTIMER1_DUTY_RES_M
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#define LEDC_HSTIMER1_LIM_V LEDC_HSTIMER1_DUTY_RES_V
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#define LEDC_HSTIMER1_LIM_S LEDC_HSTIMER1_DUTY_RES_S
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#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)
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/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1557,10 +1567,15 @@
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/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer2. the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER2_LIM 0x0000001F
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#define LEDC_HSTIMER2_LIM_M ((LEDC_HSTIMER2_LIM_V)<<(LEDC_HSTIMER2_LIM_S))
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#define LEDC_HSTIMER2_LIM_V 0x1F
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#define LEDC_HSTIMER2_LIM_S 0
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#define LEDC_HSTIMER2_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
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#define LEDC_HSTIMER2_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER2_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER2_LIM LEDC_HSTIMER2_DUTY_RES
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#define LEDC_HSTIMER2_LIM_M LEDC_HSTIMER2_DUTY_RES_M
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#define LEDC_HSTIMER2_LIM_V LEDC_HSTIMER2_DUTY_RES_V
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#define LEDC_HSTIMER2_LIM_S LEDC_HSTIMER2_DUTY_RES_S
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#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)
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/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1601,10 +1616,15 @@
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/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in high speed
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timer3. the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/
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#define LEDC_HSTIMER3_LIM 0x0000001F
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#define LEDC_HSTIMER3_LIM_M ((LEDC_HSTIMER3_LIM_V)<<(LEDC_HSTIMER3_LIM_S))
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#define LEDC_HSTIMER3_LIM_V 0x1F
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#define LEDC_HSTIMER3_LIM_S 0
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#define LEDC_HSTIMER3_DUTY_RES 0x0000001F
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#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
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#define LEDC_HSTIMER3_DUTY_RES_V 0x1F
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#define LEDC_HSTIMER3_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_HSTIMER3_LIM LEDC_HSTIMER3_DUTY_RES
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#define LEDC_HSTIMER3_LIM_M LEDC_HSTIMER3_DUTY_RES_M
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#define LEDC_HSTIMER3_LIM_V LEDC_HSTIMER3_DUTY_RES_V
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#define LEDC_HSTIMER3_LIM_S LEDC_HSTIMER3_DUTY_RES_S
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#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)
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/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1651,10 +1671,15 @@
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/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
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timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER0_LIM 0x0000001F
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#define LEDC_LSTIMER0_LIM_M ((LEDC_LSTIMER0_LIM_V)<<(LEDC_LSTIMER0_LIM_S))
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#define LEDC_LSTIMER0_LIM_V 0x1F
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#define LEDC_LSTIMER0_LIM_S 0
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#define LEDC_LSTIMER0_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
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#define LEDC_LSTIMER0_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER0_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER0_LIM LEDC_LSTIMER0_DUTY_RES
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#define LEDC_LSTIMER0_LIM_M LEDC_LSTIMER0_DUTY_RES_M
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#define LEDC_LSTIMER0_LIM_V LEDC_LSTIMER0_DUTY_RES_V
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#define LEDC_LSTIMER0_LIM_S LEDC_LSTIMER0_DUTY_RES_S
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#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)
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/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1701,10 +1726,15 @@
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/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
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timer1. the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER1_LIM 0x0000001F
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#define LEDC_LSTIMER1_LIM_M ((LEDC_LSTIMER1_LIM_V)<<(LEDC_LSTIMER1_LIM_S))
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#define LEDC_LSTIMER1_LIM_V 0x1F
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#define LEDC_LSTIMER1_LIM_S 0
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#define LEDC_LSTIMER1_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
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#define LEDC_LSTIMER1_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER1_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER1_LIM LEDC_LSTIMER1_DUTY_RES
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#define LEDC_LSTIMER1_LIM_M LEDC_LSTIMER1_DUTY_RES_M
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#define LEDC_LSTIMER1_LIM_V LEDC_LSTIMER1_DUTY_RES_V
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#define LEDC_LSTIMER1_LIM_S LEDC_LSTIMER1_DUTY_RES_S
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#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)
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/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1751,10 +1781,15 @@
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/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
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timer2. the counter range is [0 2**reg_lstimer2_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER2_LIM 0x0000001F
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#define LEDC_LSTIMER2_LIM_M ((LEDC_LSTIMER2_LIM_V)<<(LEDC_LSTIMER2_LIM_S))
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#define LEDC_LSTIMER2_LIM_V 0x1F
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#define LEDC_LSTIMER2_LIM_S 0
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#define LEDC_LSTIMER2_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
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#define LEDC_LSTIMER2_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER2_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER2_LIM LEDC_LSTIMER2_DUTY_RES
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#define LEDC_LSTIMER2_LIM_M LEDC_LSTIMER2_DUTY_RES_M
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#define LEDC_LSTIMER2_LIM_V LEDC_LSTIMER2_DUTY_RES_V
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#define LEDC_LSTIMER2_LIM_S LEDC_LSTIMER2_DUTY_RES_S
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#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)
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/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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@ -1801,10 +1836,15 @@
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/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
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/*description: This register controls the range of the counter in low speed
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timer3. the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/
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#define LEDC_LSTIMER3_LIM 0x0000001F
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#define LEDC_LSTIMER3_LIM_M ((LEDC_LSTIMER3_LIM_V)<<(LEDC_LSTIMER3_LIM_S))
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#define LEDC_LSTIMER3_LIM_V 0x1F
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#define LEDC_LSTIMER3_LIM_S 0
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#define LEDC_LSTIMER3_DUTY_RES 0x0000001F
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#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
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#define LEDC_LSTIMER3_DUTY_RES_V 0x1F
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#define LEDC_LSTIMER3_DUTY_RES_S 0
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// Keep the definitions below to be compatible with previous version
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#define LEDC_LSTIMER3_LIM LEDC_LSTIMER3_DUTY_RES
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#define LEDC_LSTIMER3_LIM_M LEDC_LSTIMER3_DUTY_RES_M
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#define LEDC_LSTIMER3_LIM_V LEDC_LSTIMER3_DUTY_RES_V
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#define LEDC_LSTIMER3_LIM_S LEDC_LSTIMER3_DUTY_RES_S
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#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)
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/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
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