diff --git a/components/soc/include/hal/cpu_hal.h b/components/soc/include/hal/cpu_hal.h
index 34e2a7a1e..adda25de0 100644
--- a/components/soc/include/hal/cpu_hal.h
+++ b/components/soc/include/hal/cpu_hal.h
@@ -76,21 +76,15 @@ extern "C" {
  *
  * @param id breakpoint to set [0..SOC_CPU_BREAKPOINTS_NUM - 1]
  * @param addr address to set a breakpoint on
- * 
- * @return ESP_OK success
- * @return others fail
  */
-esp_err_t cpu_hal_set_breakpoint(int id, const void* addr);
+void cpu_hal_set_breakpoint(int id, const void* addr);
 
 /**
  * Clear and disable breakpoint.
  *
  * @param id breakpoint to clear [0..SOC_CPU_BREAKPOINTS_NUM - 1]
- *
- * @return ESP_OK success
- * @return others fail
  */
-esp_err_t cpu_hal_clear_breakpoint(int id);
+void cpu_hal_clear_breakpoint(int id);
 
 #endif // SOC_CPU_BREAKPOINTS_NUM > 0
 
@@ -103,21 +97,15 @@ esp_err_t cpu_hal_clear_breakpoint(int id);
  * @param addr starting address
  * @param size number of bytes from starting address to watch
  * @param trigger operation on specified memory range that triggers the watchpoint (read, write, read/write)
- * 
- * @return ESP_OK success
- * @return others fail
  */
-esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
+void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger);
 
 /**
  * Clear and disable watchpoint.
  *
  * @param id watchpoint to clear [0..SOC_CPU_WATCHPOINTS_NUM - 1]
- * 
- * @return ESP_OK success
- * @return others fail
  */
-esp_err_t cpu_hal_clear_watchpoint(int id);
+void cpu_hal_clear_watchpoint(int id);
 
 #endif // SOC_CPU_WATCHPOINTS_NUM > 0
 
diff --git a/components/soc/include/hal/mpu_hal.h b/components/soc/include/hal/mpu_hal.h
index 4f96a4362..0614de9eb 100644
--- a/components/soc/include/hal/mpu_hal.h
+++ b/components/soc/include/hal/mpu_hal.h
@@ -28,11 +28,8 @@ extern "C" {
  * @param id index to the region table; on targets not SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED,
  * the region divisions is predefined in hardware which is likely reflected in LL implementation.
  * @param access type of access allowed
- * 
- * @return ESP_OK success
- * @return others fail
  */
-esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access);
+void mpu_hal_set_region_access(int id, mpu_access_t access);
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/include/hal/soc_hal.h b/components/soc/include/hal/soc_hal.h
index bc2d99bf6..6a4ab30c0 100644
--- a/components/soc/include/hal/soc_hal.h
+++ b/components/soc/include/hal/soc_hal.h
@@ -17,8 +17,9 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-#include "hal/cpu_hal.h"
 #include "soc/soc_caps.h"
+#include "hal/cpu_hal.h"
+#include "hal/soc_ll.h"
 
 #include "esp_err.h"
 
@@ -27,7 +28,6 @@ extern "C" {
 #endif
 
 #if SOC_CPU_CORES_NUM > 1
-
 // Utility functions for multicore targets
 #define __SOC_HAL_PERFORM_ON_OTHER_CORES(action)    { \
                                                         for (int i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
@@ -68,7 +68,7 @@ void soc_hal_unstall_core(int core);
  *
  * @param core core to reset [0..SOC_CPU_CORES_NUM - 1]
  */
-void soc_hal_reset_core(int core);
+#define soc_hal_reset_core(core)         soc_ll_reset_core((core))
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/src/cpu_util.c b/components/soc/src/cpu_util.c
index 8e947d15c..eadeb2f52 100644
--- a/components/soc/src/cpu_util.c
+++ b/components/soc/src/cpu_util.c
@@ -65,7 +65,8 @@ esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
         return ESP_ERR_INVALID_ARG;
     }
 
-    return cpu_hal_set_watchpoint(no, adr, size, trigger);
+    cpu_hal_set_watchpoint(no, adr, size, trigger);
+    return ESP_OK;
 }
 
 void IRAM_ATTR esp_clear_watchpoint(int no)
diff --git a/components/soc/src/hal/cpu_hal.c b/components/soc/src/hal/cpu_hal.c
index b44270704..4b2ca22c9 100644
--- a/components/soc/src/hal/cpu_hal.c
+++ b/components/soc/src/hal/cpu_hal.c
@@ -22,33 +22,21 @@
 
 #include "soc/cpu_caps.h"
 
-#define CHECK(cond)         {  if (!(cond)) abort(); }
-
 #if SOC_CPU_BREAKPOINTS_NUM > 0
-esp_err_t cpu_hal_set_breakpoint(int id, const void* addr)
+void cpu_hal_set_breakpoint(int id, const void* addr)
 {
-    CHECK(id < SOC_CPU_BREAKPOINTS_NUM && id >= 0);
     cpu_ll_set_breakpoint(id, cpu_ll_ptr_to_pc(addr));
-    return ESP_OK;
 }
 
-esp_err_t cpu_hal_clear_breakpoint(int id)
+void cpu_hal_clear_breakpoint(int id)
 {
-    CHECK(id < SOC_CPU_BREAKPOINTS_NUM && id >= 0);
     cpu_ll_clear_breakpoint(id);
-    return ESP_OK;
 }
 #endif // SOC_CPU_BREAKPOINTS_NUM > 0
 
 #if SOC_CPU_WATCHPOINTS_NUM > 0
-esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger)
+void cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoint_trigger_t trigger)
 {
-    CHECK(id < SOC_CPU_WATCHPOINTS_NUM && id >= 0);
-    CHECK(size <= SOC_CPU_WATCHPOINT_SIZE);
-    CHECK(trigger == WATCHPOINT_TRIGGER_ON_RO || 
-           trigger == WATCHPOINT_TRIGGER_ON_WO ||
-           trigger == WATCHPOINT_TRIGGER_ON_RW);
-
     bool on_read = false, on_write = false;
 
     if (trigger == WATCHPOINT_TRIGGER_ON_RO) {
@@ -60,14 +48,10 @@ esp_err_t cpu_hal_set_watchpoint(int id, const void* addr, size_t size, watchpoi
     }
 
     cpu_ll_set_watchpoint(id, addr, size, on_read, on_write);
-
-    return ESP_OK;
 }
 
-esp_err_t cpu_hal_clear_watchpoint(int id)
+void cpu_hal_clear_watchpoint(int id)
 {
-    CHECK(id < SOC_CPU_WATCHPOINTS_NUM && id >= 0);
     cpu_ll_clear_watchpoint(id);
-    return ESP_OK;
 }
 #endif // SOC_CPU_WATCHPOINTS_NUM > 0
\ No newline at end of file
diff --git a/components/soc/src/hal/mpu_hal.c b/components/soc/src/hal/mpu_hal.c
index c721aeb13..b2cae6b76 100644
--- a/components/soc/src/hal/mpu_hal.c
+++ b/components/soc/src/hal/mpu_hal.c
@@ -23,23 +23,8 @@
 
 #include "soc/mpu_caps.h"
 
-#define CHECK(cond)         {  if (!(cond)) abort(); }
-
-esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access)
+void mpu_hal_set_region_access(int id, mpu_access_t access)
 {
-    CHECK(id < SOC_MPU_REGIONS_MAX_NUM && id >= 0);
-    CHECK(
-#if SOC_MPU_REGION_RO_SUPPORTED
-           access == MPU_REGION_RO ||
-#endif
-#if SOC_MPU_REGION_WO_SUPPORTED
-           access == MPU_REGION_WO ||
-#endif
-           access == MPU_REGION_RW ||
-           access == MPU_REGION_X  ||
-           access == MPU_REGION_RWX ||
-           access == MPU_REGION_ILLEGAL);
-
     uint32_t addr = cpu_ll_id_to_addr(id);
 
     switch (access)
@@ -66,6 +51,4 @@ esp_err_t mpu_hal_set_region_access(int id, mpu_access_t access)
         default:
             break;
     }
-
-    return ESP_OK;
 }
\ No newline at end of file
diff --git a/components/soc/src/hal/soc_hal.c b/components/soc/src/hal/soc_hal.c
index d2e032daf..c01ab3e62 100644
--- a/components/soc/src/hal/soc_hal.c
+++ b/components/soc/src/hal/soc_hal.c
@@ -21,26 +21,14 @@
 #include "hal/soc_ll.h"
 #include "soc/soc_caps.h"
 
-#define CHECK(cond)         {  if (!(cond)) abort(); }
-
 #if SOC_CPU_CORES_NUM > 1
-
 void soc_hal_stall_core(int core)
 {
-    CHECK(core < SOC_CPU_CORES_NUM && core >= 0);
     soc_ll_stall_core(core);
 }
 
 void soc_hal_unstall_core(int core)
 {
-    CHECK(core < SOC_CPU_CORES_NUM && core >= 0);
     soc_ll_unstall_core(core);
 }
-
-#endif // SOC_CPU_CORES_NUM > 1
-
-void soc_hal_reset_core(int core)
-{
-    CHECK(core < SOC_CPU_CORES_NUM && core >= 0);
-    soc_ll_reset_core(core);
-}
\ No newline at end of file
+#endif // SOC_CPU_CORES_NUM > 1
\ No newline at end of file