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Merge branch 'feature/spiram_init_in_app' into 'master'

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spiram: expose function to initialize SPI RAM cache

See merge request !1281
This commit is contained in:
Ivan Grokhotkov 2017-10-17 04:56:35 +08:00
commit d3bb9de36a
3 changed files with 19 additions and 5 deletions
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1
components/esp32/cpu_start.c
View file

@ -150,6 +150,7 @@ void IRAM_ATTR call_start_cpu0()
} }
#if CONFIG_SPIRAM_BOOT_INIT #if CONFIG_SPIRAM_BOOT_INIT
esp_spiram_init_cache();
if (esp_spiram_init() != ESP_OK) { if (esp_spiram_init() != ESP_OK) {
ESP_EARLY_LOGE(TAG, "Failed to init external RAM!"); ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
abort(); abort();

13
components/esp32/include/esp_spiram.h
View file

@ -27,6 +27,17 @@
*/ */
esp_err_t esp_spiram_init(); esp_err_t esp_spiram_init();
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
*
* Normally this function is called from cpu_start, if CONFIG_SPIRAM_BOOT_INIT
* option is enabled. Applications which need to enable SPI RAM at run time
* can disable CONFIG_SPIRAM_BOOT_INIT, and call this function later.
*
* @attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache();
/** /**
* @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
@ -76,4 +87,4 @@ void esp_spiram_writeback_cache();
esp_err_t esp_spiram_reserve_dma_pool(size_t size); esp_err_t esp_spiram_reserve_dma_pool(size_t size);
#endif #endif

10
components/esp32/spiram.c
View file

@ -91,9 +91,7 @@ bool esp_spiram_test()
} }
} }
void IRAM_ATTR esp_spiram_init_cache()
esp_err_t esp_spiram_init()
{ {
//Enable external RAM in MMU //Enable external RAM in MMU
cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 ); cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
@ -102,7 +100,11 @@ esp_err_t esp_spiram_init()
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1); DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 ); cache_sram_mmu_set( 1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
#endif #endif
}
esp_err_t esp_spiram_init()
{
esp_err_t r; esp_err_t r;
r = psram_enable(PSRAM_SPEED, PSRAM_MODE); r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
if (r != ESP_OK) { if (r != ESP_OK) {
@ -202,4 +204,4 @@ void IRAM_ATTR esp_spiram_writeback_cache()
#endif #endif