bootloader: add configuration of flash pins and VDDIO boost
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2 changed files with 113 additions and 0 deletions
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@ -43,6 +43,16 @@ config BOOTLOADER_SPI_WP_PIN
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The default value (GPIO 7) is correct for WP pin on ESP32-D2WD integrated flash.
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config BOOTLOADER_VDDSDIO_BOOST
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bool "Increase VDDSDIO LDO voltage to 1.9V"
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default y
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help
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If this option is enabled, and VDDSDIO LDO is set to 1.8V (using EFUSE
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or MTDI bootstrapping pin), bootloader will change LDO settings to
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output 1.9V instead. This helps prevent flash chip from browning out
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during flash programming operations.
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For 3.3V flash, this option has no effect.
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endmenu # Bootloader
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@ -73,6 +73,8 @@ static void set_cache_and_start_app(uint32_t drom_addr,
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uint32_t irom_size,
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uint32_t entry_addr);
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static void update_flash_config(const esp_image_header_t* pfhdr);
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static void vddsdio_configure();
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static void flash_gpio_configure();
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static void clock_configure(void);
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static void uart_console_configure(void);
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static void wdt_reset_check(void);
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@ -443,6 +445,8 @@ static bool load_boot_image(const bootloader_state_t *bs, int start_index, esp_i
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void bootloader_main()
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{
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vddsdio_configure();
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flash_gpio_configure();
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clock_configure();
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uart_console_configure();
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wdt_reset_check();
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@ -737,6 +741,105 @@ static void print_flash_info(const esp_image_header_t* phdr)
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}
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static void vddsdio_configure()
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{
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#if CONFIG_BOOTLOADER_VDDSDIO_BOOST
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rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
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if (cfg.tieh == 0) { // 1.8V is used
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cfg.drefh = 3;
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cfg.drefm = 3;
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cfg.drefl = 3;
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cfg.force = 1;
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cfg.enable = 1;
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rtc_vddsdio_set_config(cfg);
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ets_delay_us(10); // wait for regulator to become stable
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}
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#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
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}
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#define FLASH_CLK_IO 6
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#define FLASH_CS_IO 11
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#define FLASH_SPIQ_IO 7
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#define FLASH_SPID_IO 8
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#define FLASH_SPIWP_IO 10
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#define FLASH_SPIHD_IO 9
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#define FLASH_IO_MATRIX_DUMMY_40M 1
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#define FLASH_IO_MATRIX_DUMMY_80M 2
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static void IRAM_ATTR flash_gpio_configure()
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{
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int spi_cache_dummy = 0;
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int drv = 2;
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#if CONFIG_FLASHMODE_QIO
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spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; //qio 3
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#elif CONFIG_FLASHMODE_QOUT
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; //qout 7
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#elif CONFIG_FLASHMODE_DIO
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //dio 3
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#elif CONFIG_FLASHMODE_DOUT
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; //dout 7
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#endif
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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#if CONFIG_ESPTOOLPY_FLASHFREQ_40M
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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drv = 3;
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#endif
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uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_ver = chip_ver & 0x7;
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if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
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// For ESP32D2WD the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32D2WD");
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
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// For ESP32PICOD2 the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32PICOD2");
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
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// For ESP32PICOD4 the SPI pins are already configured
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ESP_LOGI(TAG, "Detected ESP32PICOD4");
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//flash clock signal should come from IO MUX.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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} else {
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ESP_LOGI(TAG, "Detected ESP32");
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
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gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
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gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
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gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
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gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
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//select pin function gpio
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
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// flash clock signal should come from IO MUX.
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// set drive ability for clock
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
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SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
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}
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}
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}
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static void clock_configure(void)
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{
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/* Set CPU to 80MHz. Keep other clocks unmodified. */
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