From ca751648fa76153c21da9f3adf28b5b7ba0051a1 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Thu, 7 Dec 2017 17:11:24 +0800 Subject: [PATCH] ulp: document the need to wait for RTC to be ready for wakeup --- components/soc/esp32/include/soc/rtc_cntl_reg.h | 11 ++++++++++- docs/api-guides/ulp_instruction_set.rst | 12 +++++++++--- examples/system/ulp/main/ulp/pulse_cnt.S | 5 +++++ examples/system/ulp_adc/main/ulp/adc.S | 2 +- 4 files changed, 25 insertions(+), 5 deletions(-) diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h index ffcbb3c03..d54a7dde7 100644 --- a/components/soc/esp32/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h @@ -1830,7 +1830,16 @@ #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_S 0 -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xc0) +/* RTC_CNTL_RDY_FOR_WAKEUP : R/0; bitpos:[19]; default: 0 */ +/*description: 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise */ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 + +/* Compatibility definition */ +#define RTC_CNTL_DIAG0_REG RTC_CNTL_LOW_POWER_ST_REG /* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ /*description: */ #define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF diff --git a/docs/api-guides/ulp_instruction_set.rst b/docs/api-guides/ulp_instruction_set.rst index c4d21947c..62cbe3bd5 100755 --- a/docs/api-guides/ulp_instruction_set.rst +++ b/docs/api-guides/ulp_instruction_set.rst @@ -573,11 +573,17 @@ Similar considerations apply to ``LD`` and ``ST`` instructions. Consider the fol - If the SoC is not in deep sleep mode, and ULP interrupt bit (RTC_CNTL_ULP_CP_INT_ENA) is set in RTC_CNTL_INT_ENA_REG register, RTC interrupt will be triggered. + Note that before using WAKE instruction, ULP program may needs to wait until RTC controller is ready to wake up the main CPU. This is indicated using RTC_CNTL_RDY_FOR_WAKEUP bit of RTC_CNTL_LOW_POWER_ST_REG register. If WAKE instruction is executed while RTC_CNTL_RDY_FOR_WAKEUP is zero, it has no effect (wake up does not occur). + **Examples**:: - 1: WAKE // Trigger wake up - REG_WR 0x006, 24, 24, 0 // Stop ULP timer (clear RTC_CNTL_ULP_CP_SLP_TIMER_EN) - HALT // Stop the ULP program + 1: is_rdy_for_wakeup: // Read RTC_CNTL_RDY_FOR_WAKEUP bit + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) + AND r0, r0, 1 + JUMP is_rdy_for_wakeup, eq // Retry until the bit is set + WAKE // Trigger wake up + REG_WR 0x006, 24, 24, 0 // Stop ULP timer (clear RTC_CNTL_ULP_CP_SLP_TIMER_EN) + HALT // Stop the ULP program // After these instructions, SoC will wake up, // and ULP will not run again until started by the main program. diff --git a/examples/system/ulp/main/ulp/pulse_cnt.S b/examples/system/ulp/main/ulp/pulse_cnt.S index ba7b45344..e573e3244 100644 --- a/examples/system/ulp/main/ulp/pulse_cnt.S +++ b/examples/system/ulp/main/ulp/pulse_cnt.S @@ -130,6 +130,11 @@ edge_detected: .global wake_up wake_up: + /* Check if the system can be woken up */ + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) + and r0, r0, 1 + jump wake_up, eq + /* Wake up the SoC, end program */ wake halt diff --git a/examples/system/ulp_adc/main/ulp/adc.S b/examples/system/ulp_adc/main/ulp/adc.S index 1f0f6d5ac..70d0439c8 100644 --- a/examples/system/ulp_adc/main/ulp/adc.S +++ b/examples/system/ulp_adc/main/ulp/adc.S @@ -105,7 +105,7 @@ exit: .global wake_up wake_up: /* Check if the system can be woken up */ - READ_RTC_REG(RTC_CNTL_DIAG0_REG, 19, 1) + READ_RTC_FIELD(RTC_CNTL_LOW_POWER_ST_REG, RTC_CNTL_RDY_FOR_WAKEUP) and r0, r0, 1 jump exit, eq