rtc: update from bringup branch
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38d61f83db
commit
c9a911e4aa
5 changed files with 52 additions and 7 deletions
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@ -247,6 +247,11 @@ bool rtc_clk_8md256_enabled(void);
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*/
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*/
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void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
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void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
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/**
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* @brief Set XTAL wait cycles by RTC slow clock's period
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*/
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void rtc_clk_set_xtal_wait(void);
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/**
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/**
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* @brief Select source for RTC_SLOW_CLK
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* @brief Select source for RTC_SLOW_CLK
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* @param slow_freq clock source (one of rtc_slow_freq_t values)
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* @param slow_freq clock source (one of rtc_slow_freq_t values)
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@ -265,6 +265,29 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
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}
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}
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}
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}
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void rtc_clk_set_xtal_wait(void)
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{
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/*
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the `xtal_wait` time need 1ms, so we need calibrate slow clk period,
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and `RTC_CNTL_XTL_BUF_WAIT` depend on it.
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*/
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rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
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rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
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rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_freq == (rtc_slow_freq_x32k)) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_freq == rtc_slow_freq_8MD256) {
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cal_clk = RTC_CAL_8MD256;
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}
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uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 2000);
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uint32_t xtal_wait_1ms = 100;
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if (slow_clk_period) {
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xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period;
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}
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms);
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}
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void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
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void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
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{
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{
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
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@ -275,6 +298,11 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
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(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
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(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
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/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
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so if the slow_clk is 8md256, clk_8m must be force power on
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*/
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG,RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
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rtc_clk_set_xtal_wait();
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ets_delay_us(DELAY_SLOW_CLK_SWITCH);
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ets_delay_us(DELAY_SLOW_CLK_SWITCH);
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}
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}
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@ -458,6 +486,7 @@ static void rtc_clk_cpu_freq_to_xtal(void)
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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s_cur_freq = RTC_CPU_FREQ_XTAL;
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s_cur_freq = RTC_CPU_FREQ_XTAL;
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s_cur_pll = RTC_PLL_NONE;
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}
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}
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/**
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/**
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@ -570,12 +599,15 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
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}
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}
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if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
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if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
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ets_update_cpu_frequency(80);
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ets_update_cpu_frequency(80);
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} else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
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} else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
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ets_update_cpu_frequency(160);
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ets_update_cpu_frequency(160);
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} else if (cpu_freq == RTC_CPU_FREQ_240M) {
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} else if (cpu_freq == RTC_CPU_FREQ_240M) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
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DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
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ets_update_cpu_frequency(240);
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ets_update_cpu_frequency(240);
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}
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}
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@ -49,9 +49,8 @@
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void rtc_init(rtc_config_t cfg)
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void rtc_init(rtc_config_t cfg)
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{
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
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rtc_clk_set_xtal_wait();
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, cfg.xtal_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
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/* Moved from rtc sleep to rtc init to save sleep function running time */
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/* Moved from rtc sleep to rtc init to save sleep function running time */
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@ -144,7 +144,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
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RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
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} else {
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 6);
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}
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}
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/* enable VDDSDIO control by state machine */
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/* enable VDDSDIO control by state machine */
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@ -51,6 +51,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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}
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}
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/* Prepare calibration */
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/* Prepare calibration */
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
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/* There may be another calibration process already running during we call this function,
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* so we should wait the last process is done.
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*/
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if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
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if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
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while(!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY));
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}
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}
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
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/* Figure out how long to wait for calibration to finish */
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/* Figure out how long to wait for calibration to finish */
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@ -58,14 +66,14 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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/* Set timeout reg and expect time delay*/
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/* Set timeout reg and expect time delay*/
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uint32_t expected_freq;
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uint32_t expected_freq;
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if (cal_clk == RTC_CAL_32K_XTAL) {
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if (cal_clk == RTC_CAL_32K_XTAL) {
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 12));
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 13));
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expected_freq = 32768;
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expected_freq = 32768;
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} else if (cal_clk == RTC_CAL_8MD256) {
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} else if (cal_clk == RTC_CAL_8MD256) {
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 12));
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 13));
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expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256;
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expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256;
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} else {
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} else {
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 10));
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REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 11));
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expected_freq = 150000;
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expected_freq = 90000;
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}
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}
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uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
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uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
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/* Start calibration */
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/* Start calibration */
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@ -85,6 +93,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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break;
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break;
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}
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}
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}
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}
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
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