driver(I2S): Fix I2S reset issue for release/v3.3
`i2s_start` reseting I2S in incorrect order causeing the word-order error.
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9ff108dcd0
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c7f33524b4
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@ -492,6 +492,15 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
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rate, real_rate, bits, clkmInteger, bck, (double)I2S_BASE_CLK / mclk, real_rate*bits*channel, 64, clkmDecimals);
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}
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if (p_i2s_obj[i2s_num]->mode & I2S_MODE_TX) {
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p_i2s_obj[i2s_num]->tx->curr_ptr = NULL;
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p_i2s_obj[i2s_num]->tx->rw_pos = 0;
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}
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if (p_i2s_obj[i2s_num]->mode & I2S_MODE_RX) {
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p_i2s_obj[i2s_num]->rx->curr_ptr = NULL;
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p_i2s_obj[i2s_num]->rx->rw_pos = 0;
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}
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I2S[i2s_num]->sample_rate_conf.tx_bits_mod = bits;
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I2S[i2s_num]->sample_rate_conf.rx_bits_mod = bits;
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@ -673,17 +682,16 @@ esp_err_t i2s_start(i2s_port_t i2s_num)
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I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
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//start DMA link
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I2S_ENTER_CRITICAL();
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i2s_reset_fifo(i2s_num);
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I2S[i2s_num]->conf.tx_reset = 1;
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I2S[i2s_num]->conf.tx_reset = 0;
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I2S[i2s_num]->conf.rx_reset = 1;
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I2S[i2s_num]->conf.rx_reset = 0;
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//reset dma
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I2S[i2s_num]->lc_conf.in_rst = 1;
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I2S[i2s_num]->lc_conf.in_rst = 0;
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I2S[i2s_num]->lc_conf.out_rst = 1;
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I2S[i2s_num]->lc_conf.out_rst = 0;
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I2S[i2s_num]->conf.tx_reset = 1;
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I2S[i2s_num]->conf.tx_reset = 0;
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I2S[i2s_num]->conf.rx_reset = 1;
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I2S[i2s_num]->conf.rx_reset = 0;
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i2s_reset_fifo(i2s_num);
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esp_intr_disable(p_i2s_obj[i2s_num]->i2s_isr_handle);
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I2S[i2s_num]->int_clr.val = 0xFFFFFFFF;
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@ -898,7 +906,6 @@ static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_co
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adc_power_always_on();
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}
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// configure I2S data port interface.
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i2s_reset_fifo(i2s_num);
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//reset i2s
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I2S[i2s_num]->conf.tx_reset = 1;
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I2S[i2s_num]->conf.tx_reset = 0;
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@ -910,6 +917,7 @@ static esp_err_t i2s_param_config(i2s_port_t i2s_num, const i2s_config_t *i2s_co
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I2S[i2s_num]->lc_conf.in_rst = 0;
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I2S[i2s_num]->lc_conf.out_rst = 1;
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I2S[i2s_num]->lc_conf.out_rst = 0;
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i2s_reset_fifo(i2s_num);
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//Enable and configure DMA
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I2S[i2s_num]->lc_conf.check_owner = 0;
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