Fix dualcore PSRAM.

components/esp32/cpu_start.c

@@ -94,6 +94,13 @@ extern volatile int port_xSchedulerRunning[2];
 
 static const char* TAG = "cpu_start";
 
+
+#if CONFIG_FREERTOS_UNICORE
+#define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
+#else
+#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
+#endif
+
 /*
  * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
  * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
@@ -136,11 +143,23 @@ void IRAM_ATTR call_start_cpu0()
         memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
     }
 
+#if CONFIG_MEMMAP_SPIRAM_ENABLE
+    if ( psram_enable(PSRAM_CACHE_F40M_S40M, PSRAM_MODE) != ESP_OK) {
+        ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out.");
+        abort();
+    }
+#endif
+
     ESP_EARLY_LOGI(TAG, "Pro cpu up.");
 
+
 #if !CONFIG_FREERTOS_UNICORE
     ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
     //Flush and enable icache for APP CPU
+
+    CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1);
+
+    cache_sram_mmu_set( 1, 0, 0x3f800000, 0, 32, 128 );
     Cache_Flush(1);
     Cache_Read_Enable(1);
 
@@ -152,6 +171,7 @@ void IRAM_ATTR call_start_cpu0()
     DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
     ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
 
+
     while (!app_cpu_started) {
         ets_delay_us(100);
     }
@@ -263,6 +283,8 @@ void start_cpu0_default(void)
     vTaskStartScheduler();
 }
 
+
+
 #if !CONFIG_FREERTOS_UNICORE
 void start_cpu1_default(void)
 {

components/esp32/heap_alloc_caps.c

@@ -270,10 +270,6 @@ void heap_alloc_caps_init() {
 #endif
 
 #if CONFIG_MEMMAP_SPIRAM_ENABLE
-    if ( psram_enable(PSRAM_CACHE_F40M_S40M) != ESP_OK) {
-        ESP_EARLY_LOGE(TAG, "PSRAM enabled but initialization failed. Bailing out.");
-        abort();
-    }
 #if CONFIG_MEMMAP_SPIRAM_TEST
     if (!test_spiram(4*1024*1024)) abort();
 #endif

components/esp32/include/esp_psram.h

@@ -10,6 +10,12 @@ typedef enum {
     PSRAM_CACHE_MAX,
 } psram_cache_mode_t;
 
-esp_err_t psram_enable(psram_cache_mode_t mode);
+typedef enum {
+    PSRAM_VADDR_MODE_NORMAL=0,
+    PSRAM_VADDR_MODE_LOWHIGH,
+    PSRAM_VADDR_MODE_EVENODD,
+} psram_vaddr_mode_t;
+
+esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
 
 #endif

components/esp32/psram.c

@@ -71,7 +71,7 @@ typedef struct {
     uint32_t dummyBitLen;
 } psram_cmd_t;
 
-static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode);
+static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
 
 
 static void psram_clear_spi_fifo(psram_spi_num_t spiNum)
@@ -642,7 +642,7 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode)
 
 
 //psram gpio init , different working frequency we have different solutions
-esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode)   //psram init
+esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)   //psram init
 {
     WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG,BIT16|BIT17);//DISALBE OUPUT FOR IO16/17
 
@@ -713,12 +713,12 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode)   //psram init
         return ESP_FAIL;
     }
     psram_enable_qio_mode(PSRAM_SPI_1);
-    psram_cache_init(mode);
+    psram_cache_init(mode, vaddrmode);
     return ESP_OK;
 }
 
 //register initialization for sram cache params and r/w commands
-static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode)
+static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
 {
     CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0),SPI_CLK_EQU_SYSCLK_M);
     SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKDIV_PRE_V,0,SPI_CLKDIV_PRE_S);
@@ -781,8 +781,24 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode)
                 SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
             break;
     }
-    CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG , DPORT_PRO_CACHE_MASK_DRAM1);//use Dram1 to visit ext sram.
+
+
+    CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
+    CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
+    if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
+        SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_SPLIT);
+        SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_SPLIT);
+    } else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
+        SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG , DPORT_PRO_DRAM_HL);
+        SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG , DPORT_APP_DRAM_HL);
+    }
+
+    CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG , DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM);//use Dram1 to visit ext sram.
     SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S); //cache page mode : 1 -->16k  4 -->2k  0-->32k,(accord with the settings in cache_sram_mmu_set)
+ 
+    CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG , DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM);//use Dram1 to visit ext sram.
+    SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S); //cache page mode : 1 -->16k  4 -->2k  0-->32k,(accord with the settings in cache_sram_mmu_set)
+ 
     CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
 }
 

tools/unit-test-app/sdkconfig

@@ -117,6 +117,11 @@ CONFIG_BASE_MAC_STORED_DEFAULT_EFUSE=y
 # CONFIG_TWO_MAC_ADDRESS_FROM_EFUSE is not set
 CONFIG_FOUR_MAC_ADDRESS_FROM_EFUSE=y
 CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE=4
+CONFIG_MEMMAP_SPIRAM_ENABLE=y
+CONFIG_MEMMAP_SPIRAM_TYPE_ESPPSRAM32=y
+CONFIG_MEMMAP_SPIRAM_TEST=y
+CONFIG_MEMMAP_SPIRAM_ENABLE_MALLOC=y
+CONFIG_MEMMAP_SPIRAM_ALLOC_LIMIT_INTERNAL=1024
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2048
 CONFIG_MAIN_TASK_STACK_SIZE=4096
@@ -130,9 +135,9 @@ CONFIG_CONSOLE_UART_BAUDRATE=115200
 CONFIG_ULP_COPROC_ENABLED=y
 CONFIG_ULP_COPROC_RESERVE_MEM=512
 # CONFIG_ESP32_PANIC_PRINT_HALT is not set
-CONFIG_ESP32_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP32_PANIC_PRINT_REBOOT is not set
 # CONFIG_ESP32_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32_PANIC_GDBSTUB is not set
+CONFIG_ESP32_PANIC_GDBSTUB=y
 CONFIG_ESP32_DEBUG_OCDAWARE=y
 CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300