From c3102e8fb278dc9b0a8a077ff58c065f4c36d119 Mon Sep 17 00:00:00 2001 From: Wu Jian Gang Date: Fri, 19 Aug 2016 18:28:32 +0800 Subject: [PATCH] ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld --- .../ld/{eagle.fpga32.v7.ld => esp32.common.ld} | 15 --------------- components/esp32/ld/esp32.ld | 14 ++++++++++++++ .../{eagle.fpga32.rom.addr.v7.ld => esp32.rom.ld} | 0 3 files changed, 14 insertions(+), 15 deletions(-) rename components/esp32/ld/{eagle.fpga32.v7.ld => esp32.common.ld} (80%) create mode 100644 components/esp32/ld/esp32.ld rename components/esp32/ld/{eagle.fpga32.rom.addr.v7.ld => esp32.rom.ld} (100%) diff --git a/components/esp32/ld/eagle.fpga32.v7.ld b/components/esp32/ld/esp32.common.ld similarity index 80% rename from components/esp32/ld/eagle.fpga32.v7.ld rename to components/esp32/ld/esp32.common.ld index ca79c52de..45bcc24f4 100644 --- a/components/esp32/ld/eagle.fpga32.v7.ld +++ b/components/esp32/ld/esp32.common.ld @@ -1,18 +1,3 @@ -/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ -/* The load addresses are defined later using the AT statements. */ -MEMORY -{ - /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ - drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 -} - -_heap_end = 0x3fffe000; - /* Default entry point: */ ENTRY(call_user_start_cpu0); diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld new file mode 100644 index 000000000..4cb1c99bf --- /dev/null +++ b/components/esp32/ld/esp32.ld @@ -0,0 +1,14 @@ +/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ +/* The load addresses are defined later using the AT statements. */ +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + are connected to the data port of the CPU and eg allow bytewise access. */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x18000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ + dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x20000 /* Shared RAM, minus rom bss/data/stack.*/ + drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 +} + +_heap_end = 0x3fffe000; diff --git a/components/esp32/ld/eagle.fpga32.rom.addr.v7.ld b/components/esp32/ld/esp32.rom.ld similarity index 100% rename from components/esp32/ld/eagle.fpga32.rom.addr.v7.ld rename to components/esp32/ld/esp32.rom.ld