From 7fbfb0fc9bb36faee566cc9f96bb0695297db4c6 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 13 Jul 2018 17:44:57 +0800 Subject: [PATCH 1/2] ulp example: fix for RTC IOs - call rtc_gpio_init for pins which aren't configured as RTC by default - for RTC IOs 16 and 17, read higher part of the input register - automatically convert GPIO number into RTC IO number - use ulp_set_wakeup_period instead of writing to register --- examples/system/ulp/main/ulp/pulse_cnt.S | 23 ++++++++++++++++++--- examples/system/ulp/main/ulp_example_main.c | 15 +++++++++----- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/examples/system/ulp/main/ulp/pulse_cnt.S b/examples/system/ulp/main/ulp/pulse_cnt.S index e573e3244..774375e2a 100644 --- a/examples/system/ulp/main/ulp/pulse_cnt.S +++ b/examples/system/ulp/main/ulp/pulse_cnt.S @@ -66,12 +66,29 @@ io_number: .text .global entry entry: - /* Read the value of lower 16 RTC IOs into R0 */ - READ_RTC_FIELD(RTC_GPIO_IN_REG, RTC_GPIO_IN_NEXT) - /* Load io_number, extract the state of input */ + /* Load io_number */ move r3, io_number ld r3, r3, 0 + + /* Lower 16 IOs and higher need to be handled separately, + * because r0-r3 registers are 16 bit wide. + * Check which IO this is. + */ + move r0, r3 + jumpr read_io_high, 16, ge + + /* Read the value of lower 16 RTC IOs into R0 */ + READ_RTC_REG(RTC_GPIO_IN_REG, RTC_GPIO_IN_NEXT_S, 16) rsh r0, r0, r3 + jump read_done + + /* Read the value of RTC IOs 16-17, into R0 */ +read_io_high: + READ_RTC_REG(RTC_GPIO_IN_REG, RTC_GPIO_IN_NEXT_S + 16, 2) + sub r3, r3, 16 + rsh r0, r0, r3 + +read_done: and r0, r0, 1 /* State of input changed? */ move r3, next_edge diff --git a/examples/system/ulp/main/ulp_example_main.c b/examples/system/ulp/main/ulp_example_main.c index 873a17620..c03ab20ee 100644 --- a/examples/system/ulp/main/ulp_example_main.c +++ b/examples/system/ulp/main/ulp_example_main.c @@ -13,6 +13,7 @@ #include "nvs_flash.h" #include "soc/rtc_cntl_reg.h" #include "soc/sens_reg.h" +#include "soc/rtc_periph.h" #include "driver/gpio.h" #include "driver/rtc_io.h" #include "esp32/ulp.h" @@ -46,6 +47,10 @@ static void init_ulp_program() (ulp_main_bin_end - ulp_main_bin_start) / sizeof(uint32_t)); ESP_ERROR_CHECK(err); + /* GPIO used for pulse counting. */ + gpio_num_t gpio_num = GPIO_NUM_0; + assert(rtc_gpio_desc[gpio_num].reg && "GPIO used for pulse counting must be an RTC IO"); + /* Initialize some variables used by ULP program. * Each 'ulp_xyz' variable corresponds to 'xyz' variable in the ULP program. * These variables are declared in an auto generated header file, @@ -58,11 +63,11 @@ static void init_ulp_program() ulp_debounce_counter = 3; ulp_debounce_max_count = 3; ulp_next_edge = 0; - ulp_io_number = 11; /* GPIO0 is RTC_IO 11 */ + ulp_io_number = rtc_gpio_desc[gpio_num].rtc_num; /* map from GPIO# to RTC_IO# */ ulp_edge_count_to_wake_up = 10; - /* Initialize GPIO0 as RTC IO, input, disable pullup and pulldown */ - gpio_num_t gpio_num = GPIO_NUM_0; + /* Initialize selected GPIO as RTC IO, enable input, disable pullup and pulldown */ + rtc_gpio_init(gpio_num); rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_INPUT_ONLY); rtc_gpio_pulldown_dis(gpio_num); rtc_gpio_pullup_dis(gpio_num); @@ -76,10 +81,10 @@ static void init_ulp_program() rtc_gpio_isolate(GPIO_NUM_12); rtc_gpio_isolate(GPIO_NUM_15); - /* Set ULP wake up period to T = 20ms (3095 cycles of RTC_SLOW_CLK clock). + /* Set ULP wake up period to T = 20ms. * Minimum pulse width has to be T * (ulp_debounce_counter + 1) = 80ms. */ - REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG, SENS_SLEEP_CYCLES_S0, 3095); + ulp_set_wakeup_period(0, 20000); /* Start the program */ err = ulp_run((&ulp_entry - RTC_SLOW_MEM) / sizeof(uint32_t)); From 90c6ea59a6031772eadb67a608ae94bdba711824 Mon Sep 17 00:00:00 2001 From: negativekelvin Date: Thu, 12 Jul 2018 23:16:15 -0700 Subject: [PATCH 2/2] Fix errors in rtc_gpio_desc values --- components/soc/esp32/rtc_periph.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/components/soc/esp32/rtc_periph.c b/components/soc/esp32/rtc_periph.c index db4fb4946..36439362c 100644 --- a/components/soc/esp32/rtc_periph.c +++ b/components/soc/esp32/rtc_periph.c @@ -51,9 +51,9 @@ const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = { {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_GPIO32_CHANNEL}, //32 {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_GPIO33_CHANNEL}, //33 {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO34_CHANNEL}, //34 - {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL}, //35 + {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC2_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL}, //35 {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO36_CHANNEL}, //36 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL}, //37 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL}, //38 - {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL}, //39 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE2_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL}, //37 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE3_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL}, //38 + {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE4_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL}, //39 };