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Merge branch 'fix/add_parentheses_to_spi_swap_data_tx_4.0' into 'release/v4.0'

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spi: Put argument of macro SPI_SWAP_DATA_TX in parentheses (backport v4.0)

See merge request espressif/esp-idf!6107
This commit is contained in:
Ivan Grokhotkov 2019-09-26 21:25:20 +08:00
commit c225801b3e
1 changed files with 7 additions and 7 deletions
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14
components/driver/include/driver/spi_common.h
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@ -41,11 +41,11 @@ extern "C"
* *
* Then points tx_buffer to ``&data``. * Then points tx_buffer to ``&data``.
* *
* @param data Data to be sent, can be uint8_t, uint16_t or uint32_t. @param * @param DATA Data to be sent, can be uint8_t, uint16_t or uint32_t.
* len Length of data to be sent, since the SPI peripheral sends from the MSB, * @param LEN Length of data to be sent, since the SPI peripheral sends from
* this helps to shift the data to the MSB. * the MSB, this helps to shift the data to the MSB.
*/ */
#define SPI_SWAP_DATA_TX(data, len) __builtin_bswap32((uint32_t)data<<(32-len)) #define SPI_SWAP_DATA_TX(DATA, LEN) __builtin_bswap32((uint32_t)(DATA)<<(32-(LEN)))
/** /**
* Transform received data of length <= 32 bits to the format of an unsigned integer. * Transform received data of length <= 32 bits to the format of an unsigned integer.
@ -54,11 +54,11 @@ extern "C"
* *
* uint16_t data = SPI_SWAP_DATA_RX(*(uint32_t*)t->rx_data, 15); * uint16_t data = SPI_SWAP_DATA_RX(*(uint32_t*)t->rx_data, 15);
* *
* @param data Data to be rearranged, can be uint8_t, uint16_t or uint32_t. * @param DATA Data to be rearranged, can be uint8_t, uint16_t or uint32_t.
* @param len Length of data received, since the SPI peripheral writes from * @param LEN Length of data received, since the SPI peripheral writes from
* the MSB, this helps to shift the data to the LSB. * the MSB, this helps to shift the data to the LSB.
*/ */
#define SPI_SWAP_DATA_RX(data, len) (__builtin_bswap32(data)>>(32-len)) #define SPI_SWAP_DATA_RX(DATA, LEN) (__builtin_bswap32(DATA)>>(32-(LEN)))
/** /**
* @brief This is a configuration structure for a SPI bus. * @brief This is a configuration structure for a SPI bus.