Fix int level 4 panics to give a correct backtrace. Add cache invalid access interrupt to panic handler reasons and wire it up to panic(). Fix issue where cache was re-enabled for pro cpu and pro cpu continuing execution while cache was still disabled on app cpu.
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@ -1,5 +1,5 @@
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/*
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This code triggers a psram-related silicon bug in rev0 silicon. The bug is fixed in rev1 silicon.
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This code tests the interaction between PSRAM and SPI flash routines.
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*/
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#include <esp_types.h>
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@ -97,7 +97,6 @@ TEST_CASE("PSram cache flush on write/read", "[psram][ignore]")
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spi_flash_write(FLASHPOS, buf, 512);
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spi_flash_read(i, buf, 512);
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vTaskDelay(1);
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//if ((i%31)==0)
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}
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printf("Checked memory %d and %d times.\n", res[0], res[1]);
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@ -230,7 +230,7 @@ void *pvReturn = NULL;
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pxBlock = xStart.pxNextFreeBlock;
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while( ( ( pxBlock->xTag != tag ) || ( pxBlock->xBlockSize < xWantedSize ) ) && ( pxBlock->pxNextFreeBlock != NULL ) )
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{
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// ets_printf("Block %x -> %x\n", (uint32_t)pxBlock, (uint32_t)pxBlock->pxNextFreeBlock);
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ets_printf("Block %x -> %x\n", (uint32_t)pxBlock, (uint32_t)pxBlock->pxNextFreeBlock);
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#if (configENABLE_MEMORY_DEBUG == 1)
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{
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@ -419,6 +419,9 @@ uint8_t *puc;
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than the block being inserted. */
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for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
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{
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ets_printf("i %p\n", pxIterator);
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ets_printf("n %p\n", pxIterator->pxNextFreeBlock);
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/* Nothing to do here, just iterate to the right position. */
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}
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@ -30,6 +30,7 @@
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#include "esp_intr_alloc.h"
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#include "esp_spi_flash.h"
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#include "esp_log.h"
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#include "esp_psram.h"
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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@ -59,6 +60,13 @@ void spi_flash_op_unlock()
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xSemaphoreGive(s_flash_op_mutex);
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}
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/*
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If you're going to modify this, keep in mind that while the flash caches of the pro and app
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cpu are separate, the psram cache is *not*. If one of the CPUs returns from a flash routine
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with its cache enabled but the other CPUs cache is not enabled yet, you will have problems
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when accessing psram from the former CPU.
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*/
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void IRAM_ATTR spi_flash_op_block_func(void* arg)
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{
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// Disable scheduler on this CPU
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@ -76,8 +84,6 @@ void IRAM_ATTR spi_flash_op_block_func(void* arg)
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while (!s_flash_op_complete) {
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// busy loop here and wait for the other CPU to finish flash operation
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}
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// Flash operation is complete, re-enable cache
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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// Restore interrupts that aren't located in IRAM
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esp_intr_noniram_enable();
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// Re-enable scheduler
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@ -110,8 +116,8 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
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esp_err_t ret = esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void*) other_cpuid);
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assert(ret == ESP_OK);
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while (!s_flash_op_can_start) {
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// Busy loop and wait for spi_flash_op_block_func to disable cache
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// on the other CPU
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// Busy loop and wait for spi_flash_op_block_func to run so we can
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// disable cache of the other CPU
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}
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// Disable scheduler on the current CPU
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vTaskSuspendAll();
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@ -121,8 +127,9 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
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}
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// Kill interrupts that aren't located in IRAM
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esp_intr_noniram_disable();
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// Disable cache on this CPU as well
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// Disable cache on both CPUs as well
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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}
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void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
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@ -135,8 +142,9 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
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s_flash_op_cpu = -1;
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#endif
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// Re-enable cache on this CPU
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// Re-enable cache on both CPUs
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]);
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if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
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// Scheduler is not running yet — this means we are running on PRO CPU.
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