diff --git a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld
index c2861a4ff..4f0655a25 100644
--- a/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld
@@ -16,8 +16,8 @@ MEMORY
   /* IRAM POOL1, used for APP CPU cache. Bootloader runs from here during the final stage of loading the app because APP CPU is still held in reset, the main app enables APP CPU cache */
   iram_loader_seg (RWX) :           org = 0x40022000, len = 0x2000  /* 8KB, APP CPU cache */
   iram_seg (RWX) :                  org = 0x40024000, len = 0x4000  /* 16KB, IRAM */
-  /* 12k at the end of DRAM, after ROM bootloader stack */
-  dram_seg (RW) :                   org = 0x3FFF5000, len = 0x3000
+  /* 16k at the end of DRAM, after ROM bootloader stack */
+  dram_seg (RW) :                   org = 0x3FFF8000, len = 0x4000
 }
 
 /*  Default entry point:  */
diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c
index 9c9bc7e80..38df52df0 100644
--- a/components/soc/esp32s2beta/soc_memory_layout.c
+++ b/components/soc/esp32s2beta/soc_memory_layout.c
@@ -122,7 +122,7 @@ extern int _data_start_xtos;
    These are removed from the soc_memory_regions array when heaps are created.
  */
 //ROM data region
-SOC_RESERVE_MEMORY_REGION(0x3fff8000, (intptr_t)&_data_start_xtos, rom_data_region);
+SOC_RESERVE_MEMORY_REGION(0x3fffc000, (intptr_t)&_data_start_xtos, rom_data_region);
 
 // TODO: soc_memory_layout: handle trace memory regions - IDF-750