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Merge branch 'bugfix/xtal_freq_40_2.0' into 'release/v2.0' 

esp32: by default, set 40MHz crystal frequency

See merge request !1144
This commit is contained in:
Ivan Grokhotkov 2017-08-24 15:48:06 +08:00
parent 024ef51d1a 18dbdd46f4
commit bef9896305
2 changed files with 4 additions and 2 deletions
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4
.gitlab-ci.yml
View File

@ -337,6 +337,7 @@ check_doc_links:
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
- git checkout ${CI_COMMIT_REF_NAME} || echo "Using default branch..."
# run test
- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH -m $MODULE_UPDATE_FILE bin_path $APP_NAME $BIN_PATH
@ -364,6 +365,7 @@ check_doc_links:
# clone test bench
- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
- cd auto_test_script
- git checkout ${CI_COMMIT_REF_NAME} || echo "Using default branch..."
# run test
- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH -m $MODULE_UPDATE_FILE bin_path $APP_NAME $BIN_PATH
@ -380,7 +382,7 @@ check_doc_links:
APP_NAME: "ut"
TEST_CASE_FILE_PATH: "$CI_PROJECT_DIR/components/idf_test/unit_test"
MODULE_UPDATE_FILE: "$CI_PROJECT_DIR/tools/unit-test-app/ModuleDefinition.yml"
dependencies:
- build_esp_idf_tests

2
components/esp32/cpu_freq.c
View File

@ -36,7 +36,7 @@ void esp_set_cpu_freq(void)
// wait uart tx finish, otherwise some uart output will be lost
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
rtc_init_lite(XTAL_AUTO);
rtc_init_lite(XTAL_40M);
// work around a bug that RTC fast memory may be isolated
// from the system after rtc_init_lite
SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO_M);