diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index a4375a654..2eca06942 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -350,7 +350,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme /* Before loading segment, check it doesn't clobber bootloader RAM. */ if (do_load) { const intptr_t load_end = load_addr + data_len; - if (load_end <= (intptr_t) SOC_DIRAM_DRAM_HIGH) { + if (load_end < (intptr_t) SOC_DRAM_HIGH) { /* Writing to DRAM */ intptr_t sp = (intptr_t)get_sp(); if (load_end > sp - STACK_LOAD_HEADROOM) { diff --git a/components/heap/heap_caps.c b/components/heap/heap_caps.c index 9c7d91a2e..4323a2389 100644 --- a/components/heap/heap_caps.c +++ b/components/heap/heap_caps.c @@ -39,12 +39,16 @@ possible. This should optimize the amount of RAM accessible to the code without IRAM_ATTR static void *dram_alloc_to_iram_addr(void *addr, size_t len) { uintptr_t dstart = (uintptr_t)addr; //First word - uintptr_t dend = dstart + len - 4; //Last word + uintptr_t dend = dstart + len; //Last word + 4 assert(esp_ptr_in_diram_dram((void *)dstart)); assert(esp_ptr_in_diram_dram((void *)dend)); assert((dstart & 3) == 0); assert((dend & 3) == 0); +#if CONFIG_IDF_TARGET_ESP32 uint32_t istart = SOC_DIRAM_IRAM_LOW + (SOC_DIRAM_DRAM_HIGH - dend); +#elif CONFIG_IDF_TARGET_ESP32S2BETA + uint32_t istart = SOC_DIRAM_IRAM_LOW + (dstart - SOC_DIRAM_DRAM_LOW); +#endif uint32_t *iptr = (uint32_t *)istart; *iptr = dstart; return iptr + 1; diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index c751072ca..603408795 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -258,9 +258,9 @@ //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x400A0000 -#define SOC_DIRAM_IRAM_HIGH 0x400BFFFC +#define SOC_DIRAM_IRAM_HIGH 0x400C0000 #define SOC_DIRAM_DRAM_LOW 0x3FFE0000 -#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC +#define SOC_DIRAM_DRAM_HIGH 0x40000000 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FFAE000 diff --git a/components/soc/esp32s2beta/include/soc/soc.h b/components/soc/esp32s2beta/include/soc/soc.h index 86cd83e3d..80e68aacc 100644 --- a/components/soc/esp32s2beta/include/soc/soc.h +++ b/components/soc/esp32s2beta/include/soc/soc.h @@ -201,9 +201,9 @@ //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40020000 -#define SOC_DIRAM_IRAM_HIGH 0x4006FFFC +#define SOC_DIRAM_IRAM_HIGH 0x40070000 #define SOC_DIRAM_DRAM_LOW 0x3FFB0000 -#define SOC_DIRAM_DRAM_HIGH 0x3FFFFFFC +#define SOC_DIRAM_DRAM_HIGH 0x40000000 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). #define SOC_DMA_LOW 0x3FFB0000 diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c index 390794f45..9c9bc7e80 100644 --- a/components/soc/esp32s2beta/soc_memory_layout.c +++ b/components/soc/esp32s2beta/soc_memory_layout.c @@ -75,21 +75,21 @@ const soc_memory_region_t soc_memory_regions[] = { #endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB #if CONFIG_ESP32S2_DATA_CACHE_0KB - { 0x3FFB2000, 0x2000, 0, 0x400B2000}, //Block 1, can be use as I/D cache memory - { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB2000, 0x2000, 0, 0x40022000}, //Block 1, can be use as I/D cache memory + { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #elif CONFIG_ESP32S2_DATA_CACHE_8KB - { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #else - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #endif #else #if CONFIG_ESP32S2_DATA_CACHE_0KB - { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #elif CONFIG_ESP32S2_DATA_CACHE_8KB - { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory + { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory #endif #endif { 0x3FFB8000, 0x4000, 0, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory @@ -121,9 +121,6 @@ extern int _data_start_xtos; These are removed from the soc_memory_regions array when heaps are created. */ -// DRAM counterpart of the of the region reserved for IRAM in the linker script -SOC_RESERVE_MEMORY_REGION(0x3ffb8000, 0x3FFD0000, dram_mapped_to_iram); - //ROM data region SOC_RESERVE_MEMORY_REGION(0x3fff8000, (intptr_t)&_data_start_xtos, rom_data_region); diff --git a/components/soc/src/memory_layout_utils.c b/components/soc/src/memory_layout_utils.c index 29f752b9d..cc3b91046 100644 --- a/components/soc/src/memory_layout_utils.c +++ b/components/soc/src/memory_layout_utils.c @@ -127,13 +127,14 @@ size_t soc_get_available_memory_regions(soc_memory_region_t *regions) bool move_to_next = true; for (size_t i = 0; i < num_reserved; i++) { - if (reserved[i].end <= in_start) { - /* reserved region ends before 'in' starts */ - continue; + if (reserved[i].start >= SOC_DRAM_HIGH && in_end < SOC_DRAM_HIGH && in.iram_address != 0) { + reserved[i].start = reserved[i].start - (in.iram_address - in.start); + reserved[i].end = reserved[i].end - (in.iram_address - in.start); } - else if (reserved[i].start >= in_end) { - /* reserved region starts after 'in' ends */ - break; + + if (reserved[i].end <= in_start || reserved[i].start >= in_end) { + /* reserved region ends before 'in' starts or reserved region starts after 'in' ends */ + continue; } else if (reserved[i].start <= in_start && reserved[i].end >= in_end) { /* reserved covers all of 'in' */ diff --git a/components/xtensa/include/esp_debug_helpers.h b/components/xtensa/include/esp_debug_helpers.h index ad2681de2..d088ddeef 100644 --- a/components/xtensa/include/esp_debug_helpers.h +++ b/components/xtensa/include/esp_debug_helpers.h @@ -22,6 +22,7 @@ extern "C" { #include #include "esp_err.h" +#include "soc/soc.h" #define ESP_WATCHPOINT_LOAD 0x40000000 #define ESP_WATCHPOINT_STORE 0x80000000 @@ -126,7 +127,6 @@ bool esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame); */ esp_err_t esp_backtrace_print(int depth); - #endif #ifdef __cplusplus }