Merge branch 'bugfix/wdt_reset_info_for_cpu1_not_correct' into 'master'
bugfix:Fix bug that wdt reset information for CPU1 was not correct See merge request !823
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commit
bb6189b335
2 changed files with 11 additions and 4 deletions
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@ -766,12 +766,11 @@ static void uart_console_configure(void)
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#endif // CONFIG_CONSOLE_UART_NONE
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}
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static void wdt_reset_info_enable(void)
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static void wdt_reset_cpu0_info_enable(void)
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{
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//We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1.
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DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
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DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
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}
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static void wdt_reset_info_dump(int cpu)
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@ -841,5 +840,5 @@ static void wdt_reset_check(void)
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wdt_reset_info_dump(0);
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wdt_reset_info_dump(1);
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}
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wdt_reset_info_enable();
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wdt_reset_cpu0_info_enable();
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}
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@ -170,6 +170,13 @@ void IRAM_ATTR call_start_cpu0()
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}
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#if !CONFIG_FREERTOS_UNICORE
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static void wdt_reset_cpu1_info_enable(void)
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{
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DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
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DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
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}
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void IRAM_ATTR call_start_cpu1()
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{
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asm volatile (\
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@ -188,6 +195,7 @@ void IRAM_ATTR call_start_cpu1()
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uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
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#endif
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wdt_reset_cpu1_info_enable();
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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app_cpu_started = 1;
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start_cpu1();
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