diff --git a/components/bootloader/src/main/bootloader_start.c b/components/bootloader/src/main/bootloader_start.c index b9df64012..a25a266c0 100644 --- a/components/bootloader/src/main/bootloader_start.c +++ b/components/bootloader/src/main/bootloader_start.c @@ -294,7 +294,7 @@ void bootloader_main() log_notice( "compile time %s\n", __TIME__ ); /* close watch dog here */ REG_CLR_BIT( RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN ); - REG_CLR_BIT( WDTCONFIG0, TIMERS_WDT_FLASHBOOT_MOD_EN ); + REG_CLR_BIT( WDTCONFIG0(0), TIMERS_WDT_FLASHBOOT_MOD_EN ); SPIUnlock(); /*register first sector in drom0 page 0 */ boot_cache_redirect( 0, 0x5000 ); diff --git a/components/esp32/include/esp_intr.h b/components/esp32/include/esp_intr.h index fc2083889..e138133f6 100644 --- a/components/esp32/include/esp_intr.h +++ b/components/esp32/include/esp_intr.h @@ -61,8 +61,8 @@ extern "C" { #define ESP_GPIO_INTR_ATTACH(func, arg) \ xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg)) -#define ESP_UART_INTR_ATTACH(func, arg) \ - xt_set_interrupt_handler(ETS_UART_INUM, (func), (void *)(arg)) +#define ESP_UART0_INTR_ATTACH(func, arg) \ + xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg)) #define ESP_WDT_INTR_ATTACH(func, arg) \ xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg)) @@ -142,11 +142,11 @@ extern "C" { #define ESP_BB_INTR_DISABLE() \ ESP_INTR_DISABLE(ETS_BB_INUM) -#define ESP_UART_INTR_ENABLE() \ - ESP_INTR_ENABLE(ETS_UART_INUM) +#define ESP_UART0_INTR_ENABLE() \ + ESP_INTR_ENABLE(ETS_UART0_INUM) -#define ESP_UART_INTR_DISABLE() \ - ESP_INTR_DISABLE(ETS_UART_INUM) +#define ESP_UART0_INTR_DISABLE() \ + ESP_INTR_DISABLE(ETS_UART0_INUM) #define ESP_LEDC_INTR_ENABLE() \ ESP_INTR_ENABLE(ETS_LEDC_INUM) diff --git a/components/esp32/include/rom/aes.h b/components/esp32/include/rom/aes.h index 9fd0e5bae..d81d8f6f9 100644 --- a/components/esp32/include/rom/aes.h +++ b/components/esp32/include/rom/aes.h @@ -11,6 +11,7 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #ifndef _ROM_AES_H_ #define _ROM_AES_H_ @@ -21,6 +22,7 @@ extern "C" { #endif +//TODO, add comment for aes apis enum AES_BITS { AES128, AES192, @@ -32,8 +34,8 @@ void ets_aes_enable(void); void ets_aes_disable(void); void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, - bool in_word_swap, bool in_byte_swap, - bool out_word_swap, bool out_byte_swap); + bool in_word_swap, bool in_byte_swap, + bool out_word_swap, bool out_byte_swap); bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits); diff --git a/components/esp32/include/rom/bigint.h b/components/esp32/include/rom/bigint.h index 461469cac..ab4246c6d 100644 --- a/components/esp32/include/rom/bigint.h +++ b/components/esp32/include/rom/bigint.h @@ -11,6 +11,7 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #ifndef _ROM_BIGINT_H_ #define _ROM_BIGINT_H_ @@ -21,6 +22,7 @@ extern "C" { #endif +//TODO: add comment here void ets_bigint_enable(void); void ets_bigint_disable(void); diff --git a/components/esp32/include/rom/cache.h b/components/esp32/include/rom/cache.h index b9e59448f..fb84bca03 100644 --- a/components/esp32/include/rom/cache.h +++ b/components/esp32/include/rom/cache.h @@ -11,6 +11,7 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #ifndef _ROM_CACHE_H_ #define _ROM_CACHE_H_ @@ -18,50 +19,126 @@ extern "C" { #endif -//=========================================== -// function : cache_init -// description: initialise cache mmu, mark all entries as invalid. -// conditions: -// Call Cache_Read_Disable() before calling this function. -// inputs: -// cpu_no is CPU number,0(PRO CPU) or 1(APP CPU), -// output: NONE -//=========================================== +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ void mmu_init(int cpu_no); -//=========================================== -// function : cache_flash_mmu_set -// description: Configure MMU to cache a flash region. -// conditions: -// Call this function to configure the flash cache before enabling it. -// Check return value to verify MMU was set correctly. -// inputs: -// cpu_no is CPU number,0(PRO CPU) or 1(APP CPU), -// pid is process identifier. Range 0~7 -// vaddr is "virtual" address in CPU address space. Can be IRam0, IRam1, IRom0 and DRom0 memory address. -// Should be aligned by psize -// paddr is "physical" address in flash controller's address space. -// ie for 16M flash the range is 0x000000~0xFFFFFF. Should be aligned by psize -// psize is page size of flash, in kilobytes. Can be 64, 32, 16. -// num is number of pages to be set, valid range 0 ~ (flash size)/(page size) -// output: error status -// 0 : mmu set success -// 1 : vaddr or paddr is not aligned -// 2 : pid error -// 3 : psize error -// 4 : mmu table to be written is out of range -// 5 : vaddr is out of range -//=========================================== +/** + * @brief Set Flash-Cache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu. + * + * @param int pod : process identifier. Range 0~7. + * + * @param unsigned int vaddr : virtual address in CPU address space. + * Can be IRam0, IRam1, IRom0 and DRom0 memory address. + * Should be aligned by psize. + * + * @param unsigned int paddr : physical address in Flash. + * Should be aligned by psize. + * + * @param int psize : page size of flash, in kilobytes. Should be 64 here. + * + * @param int num : pages to be set. + * + * @return unsigned int: error status + * 0 : mmu set success + * 1 : vaddr or paddr is not aligned + * 2 : pid error + * 3 : psize error + * 4 : mmu table to be written is out of range + * 5 : vaddr is out of range + */ unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num); -unsigned int cache_sram_mmu_set(int cpu_no, int pid,unsigned int vaddr, unsigned int paddr, int psize, int num); +/** + * @brief Set Ext-SRAM-Cache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu. + * + * @param int pod : process identifier. Range 0~7. + * + * @param unsigned int vaddr : virtual address in CPU address space. + * Can be IRam0, IRam1, IRom0 and DRom0 memory address. + * Should be aligned by psize. + * + * @param unsigned int paddr : physical address in Ext-SRAM. + * Should be aligned by psize. + * + * @param int psize : page size of flash, in kilobytes. Should be 32 here. + * + * @param int num : pages to be set. + * + * @return unsigned int: error status + * 0 : mmu set success + * 1 : vaddr or paddr is not aligned + * 2 : pid error + * 3 : psize error + * 4 : mmu table to be written is out of range + * 5 : vaddr is out of range + */ +unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num); +/** + * @brief Initialise cache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ void Cache_Read_Init(int cpu_no); +/** + * @brief Flush the cache value for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ +void Cache_Flush(int cpu_no); + +/** + * @brief Disable Cache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ void Cache_Read_Disable(int cpu_no); +/** + * @brief Enable Cache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu. + * + * @return None + */ void Cache_Read_Enable(int cpu_no); +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/components/esp32/include/rom/crc.h b/components/esp32/include/rom/crc.h index be763d7dc..84e17882d 100644 --- a/components/esp32/include/rom/crc.h +++ b/components/esp32/include/rom/crc.h @@ -11,20 +11,113 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #ifndef ROM_CRC_H #define ROM_CRC_H +#include + #ifdef __cplusplus extern "C" { #endif +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + + /* Standard CRC8/16/32 algorithms. */ -uint32_t crc32_le(uint32_t crc, uint8_t const * buf, uint32_t len); -uint32_t crc32_be(uint32_t crc, uint8_t const * buf, uint32_t len); -uint16_t crc16_le(uint16_t crc, uint8_t const * buf, uint32_t len); -uint16_t crc16_be(uint16_t crc, uint8_t const * buf, uint32_t len); -uint8_t crc8_le(uint8_t crc, uint8_t const * buf, uint32_t len); -uint8_t crc8_be(uint8_t crc, uint8_t const * buf, uint32_t len); +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ #ifdef __cplusplus } diff --git a/components/esp32/include/rom/efuse.h b/components/esp32/include/rom/efuse.h index 6d0252b5e..58cfdb20b 100644 --- a/components/esp32/include/rom/efuse.h +++ b/components/esp32/include/rom/efuse.h @@ -11,17 +11,100 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #ifndef _ROM_EFUSE_H_ #define _ROM_EFUSE_H_ +#include + #ifdef __cplusplus extern "C" { #endif +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +/** + * @brief Do a efuse read operation, to update the efuse value to efuse read registers. + * + * @param null + * + * @return null + */ void ets_efuse_read_op(void); +/** + * @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again. + * + * @param null + * + * @return null + */ void ets_efuse_program_op(void); +/** + * @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature. + * It can be used to test the external xtal frequency, do not touch this efuse field. + * + * @param null + * + * @return u32: 1 for 100KHZ, range is 0 to 255. + */ +uint32_t ets_efuse_get_8M_clock(void); + +/** + * @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads. + * + * @param null + * + * @return uint32_t: 0, invalid, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + */ +uint32_t ets_efuse_get_spiconfig(void); + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief A crc8 algorithm used in efuse check. + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/components/esp32/include/rom/ets_sys.h b/components/esp32/include/rom/ets_sys.h index fd7bbdb9c..c412c9b41 100644 --- a/components/esp32/include/rom/ets_sys.h +++ b/components/esp32/include/rom/ets_sys.h @@ -24,82 +24,242 @@ extern "C" { #endif -#define ETS_DEBUG -#define ETS_SERIAL_ENABLED() (1) +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ typedef enum { - ETS_OK = 0, - ETS_FAILED = 1 + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1 /**< return failed in ets*/ } ETS_STATUS; typedef uint32_t ETSSignal; typedef uint32_t ETSParam; -typedef struct ETSEventTag ETSEvent; +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ struct ETSEventTag { - ETSSignal sig; - ETSParam par; + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ }; -typedef void (*ETSTask)(ETSEvent *e); - -enum ETS_User_Priorities { - /* task priorities... */ - TICK_TASK_A_PRIO = 2, - KBD_TASK_PRIO = 5, - MAX_ETS_USER_PRIO = 16, - - /* ISR priorities... */ - MAX_ETS_USER_ISR_PRIO = 0xFF - 16 -}; - -/* ETS interrupt entry and exit */ -/* actually we don't need the following 2 macros any more since we won't exit - * isr until it is finised, more over, we don't do nest interrupt - */ +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ +/** + * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. + * + * @param none + * + * @return none + */ void ets_run(void); +/** + * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. + * + * @param ets_idle_cb_t func : The callback function. + * + * @param void *arg : Argument of the callback. + * + * @return None + */ +void ets_set_idle_cb(ets_idle_cb_t func, void *arg); + +/** + * @brief Init a task with processer, priority, queue to receive Event, queue length. + * + * @param ETSTask task : The task processer. + * + * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. + * + * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. + * + * @param uint8_t qlen : Queue length. + * + * @return None + */ void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); +/** + * @brief Post an event to an Task. + * + * @param uint8_t prio : Priority of the Task. + * + * @param ETSSignal sig : Event signal. + * + * @param ETSParam par : Event parameter + * + * @return ETS_OK : post successful + * @return ETS_FAILED : post failed + */ +ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); -/* - * now things become complicated, print could be directed to uart and/or SDIO - */ +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. + * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. + * + * @param uint32_t callback : the Startup code address value in uint32_t + * + * @return None : post successful + */ +void ets_set_startup_callback(uint32_t callback); + +/** + * @brief Set App cpu Entry code, code can be called in PRO CPU. + * When APP booting is completed, APP CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. + * + * @return None + */ +void ets_set_appcpu_boot_addr(uint32_t start); + +/** + * @brief unpack the image in flash to iram and dram, no using cache. + * + * @param uint32_t pos : Flash physical address. + * + * @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address. + * + * @param bool jump : Jump into the code in the function or not. + * + * @param bool config : Config the flash when unpacking the image, config should be done only once. + * + * @return ETS_OK : unpack successful + * @return ETS_FAILED : unpack failed + */ +ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config); + +/** + * @brief unpack the image in flash to iram and dram, using cache, maybe decrypting. + * + * @param uint32_t pos : Flash physical address. + * + * @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address. + * + * @param bool jump : Jump into the code in the function or not. + * + * @param bool sb_need_check : Do security boot check or not. + * + * @param bool config : Config the flash when unpacking the image, config should be done only once. + * + * @return ETS_OK : unpack successful + * @return ETS_FAILED : unpack failed + */ +ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ int ets_printf(const char *fmt, ...); -/* by default it's UART, just install_uart_printf, set putc1 to NULL to disable */ +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ void ets_install_putc1(void (*p)(char c)); -void ets_install_uart_printf(void); -/* no need to install, call directly */ -int ets_uart_printf(const char *fmt, ...); - -/* usually we don't need to call this, unless we want to disable SDIO print */ +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ void ets_install_putc2(void (*p)(char c)); -/* @prepare_buf: allocate buffer for printf internal writting - * @putc: just set to NULL, let printf write to to buffer, unless if you want more fancy stuff - * @post_printf: will be called every time printf finish write buffer - * - * main idea of external printf is re-directing content to an external buffer. - * e.g. sip module allocates an event buffer in prepare_buf() and send the event to host in post_printf() - * moreover, you can check printf_buf_remain_len in post_printf(), send the event to host till buf is - * about to full. - * - * TBD: Another approach is sending printf parameter to host and let host to decode, which could save some bytes. - */ -void ets_install_external_printf(void (*prepare_buf)(char ** bufptr, uint16_t *buflen, uint32_t *cookie), - void (*putc)(char c), - void (*post_printf)(uint32_t cookie)); - -uint16_t est_get_printf_buf_remain_len(void); -void est_reset_printf_buf_len(void); - -/* external (SDIO) printf only, still need to install*/ -int ets_external_printf(const char *fmt, ...); +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); #define ETS_PRINTF(...) ets_printf(...) @@ -110,82 +270,251 @@ int ets_external_printf(const char *fmt, ...); } \ } while (0); -/* memory and string support */ -int8_t ets_char2xdigit(char ch); -uint8_t * ets_str2macaddr(uint8_t *macaddr, char *str); -void ets_getc(char *c); -void ets_putc(char c); +/** + * @} + */ -/* timer related */ -typedef uint32_t ETSHandle; -typedef void ETSTimerFunc(void *timer_arg); +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ typedef struct _ETSTIMER_ { - struct _ETSTIMER_ *timer_next; - uint32_t timer_expire; - uint32_t timer_period; - ETSTimerFunc *timer_func; - void *timer_arg; + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ } ETSTimer; +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ void ets_timer_init(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ void ets_timer_disarm(ETSTimer *timer); -void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); -/* watchdog related */ -typedef enum { - WDT_NONE = -1, - WDT_DISABLED = 0, - WDT_CONTROL_RESET = 1, - WDT_CONTROL_INTR = 2, /* usually we use this mode? */ - WDT_CONTROL_EXTERNAL_FEED = 3, - WDT_TESET_OVERFLOW = 4, // intend to make watchdog overflow to test -} WDT_MODE; +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); -typedef enum{ - WDT_INTERVAL_THREE_SEC = 3, - WDT_INTERVAL_SIX_SEC = 6, - WDT_INTERVAL_TWELVE_SEC = 12, -} WDT_INTERVAL_TIME; +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); -void ets_wdt_init(void); -WDT_MODE ets_wdt_get_mode(void); -void ets_wdt_enable(WDT_MODE mode, WDT_INTERVAL_TIME feed_interval, - WDT_INTERVAL_TIME expire_interval); -WDT_MODE ets_wdt_disable(void); -void ets_wdt_restore(WDT_MODE old_mode); +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); -/* interrupt related */ -typedef void (* ets_isr_t)(void *); +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); -#define ETS_WMAC_SOURCE 0 -#define ETS_SLC_SOURCE 1 -#define ETS_UART_SOURCE 13 -#define ETS_UART1_SOURCE 14 -#define ETS_FRC_TIMER2_SOURCE 43 +/** + * @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module. + * + * @param None + * + * @return uint32_t : xtal_freq/analog_8M*256. + */ +uint32_t ets_get_xtal_scale(void); -#define ETS_WMAC_INUM 0 -#define ETS_SLC_INUM 1 -#define ETS_SPI_INUM 2 -#define ETS_HSIP_INUM 2 -#define ETS_I2S_INUM 2 -#define ETS_RTC_INUM 3 -#define ETS_FRC_TIMER1_INUM 9 /* use edge*/ -#define ETS_FRC_TIMER2_INUM 10 /* use edge*/ -#define ETS_WDT_INUM 8 /* use edge*/ -#define ETS_GPIO_INUM 4 -#define ETS_UART_INUM 5 -#define ETS_UART1_INUM 5 -#define ETS_MAX_INUM 6 +/** + * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. + * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; + * else if analog_8M in efuse + * clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40; + * else clock = 26M. + */ +uint32_t ets_get_detected_xtal_freq(void); +/** + * @} + */ +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ void ets_intr_unlock(void); + +/** + * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_waiti0(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); #define _ETSTR(v) # v @@ -194,126 +523,80 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); : "=a" (__tmp) : : "memory" ); \ }) +#ifdef CONFIG_NONE_OS #define ETS_INTR_LOCK() \ - ets_intr_lock() + ets_intr_lock() #define ETS_INTR_UNLOCK() \ - ets_intr_unlock() - -#define ETS_CCOMPARE_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_CCOMPARE_INUM, (func), (void *)(arg)) - -#define ETS_PWM_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_PWM_INUM, (func), (void *)(arg)) - -#define ETS_WMAC_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_WMAC_INUM, (func), (void *)(arg)) - -#define ETS_FRC_TIMER1_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_FRC_TIMER1_INUM, (func), (void *)(arg)) - -#define ETS_FRC_TIMER2_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_FRC_TIMER2_INUM, (func), (void *)(arg)) - -#define ETS_GPIO_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_GPIO_INUM, (func), (void *)(arg)) - -#define ETS_UART_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_UART_INUM, (func), (void *)(arg)) - -#define ETS_WDT_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_WDT_INUM, (func), (void *)(arg)) - -#define ETS_RTC_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_RTC_INUM, (func), (void *)(arg)) - -#define ETS_SLC_INTR_ATTACH(func, arg) \ - ets_isr_attach(ETS_SLC_INUM, (func), (void *)(arg)) + ets_intr_unlock() +#define ETS_ISR_ATTACH \ + ets_isr_attach #define ETS_INTR_ENABLE(inum) \ - xt_ints_on((1<= '0') && (c <= '9')) - -#define isxdigit(c) (((c >= '0') && (c <= '9')) || \ - ((c >= 'a') && (c <= 'f')) || \ - ((c >= 'A') && (c <= 'F')) ) - -#define isblank(c) ((c == ' ') || (c == '\t')) - -#define isupper(c) ((c >= 'A') && (c <= 'Z')) + ETS_INTR_DISABLE(ETS_SLC_INUM) #endif +/** + * @} + */ #ifndef MAC2STR #define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] @@ -322,6 +605,10 @@ uint32_t ets_get_detected_xtal_freq(); #define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/components/esp32/include/rom/gpio.h b/components/esp32/include/rom/gpio.h index afb8e2018..a6ca66f1d 100644 --- a/components/esp32/include/rom/gpio.h +++ b/components/esp32/include/rom/gpio.h @@ -25,6 +25,14 @@ extern "C" { #endif +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + #define GPIO_REG_READ(reg) READ_PERI_REG(reg) #define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) #define GPIO_PIN_COUNT 40 @@ -37,17 +45,14 @@ extern "C" { #define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) -typedef enum{ - GPIO_PIN_INTR_DISABLE = 0, - GPIO_PIN_INTR_POSEDGE = 1, - GPIO_PIN_INTR_NEGEDGE = 2, - GPIO_PIN_INTR_ANYEGDE = 3, - GPIO_PIN_INTR_LOLEVEL = 4, - GPIO_PIN_INTR_HILEVEL = 5 -}GPIO_INT_TYPE; - -#define GREEN_LED_ON() GPIO_OUTPUT_SET(GPIO_ID_PIN(1) , 0) -#define GREEN_LED_OFF() GPIO_OUTPUT_SET(GPIO_ID_PIN(1) , 1) +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEGDE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; #define GPIO_OUTPUT_SET(gpio_no, bit_value) \ ((gpio_no < 32) ? gpio_output_set(bit_value<BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); -/* - * Change GPIO pin output by setting, clearing, or disabling pins. - * In general, it is expected that a bit will be set in at most one - * of these masks. If a bit is clear in all masks, the output state - * remains unchanged. - * - * There is no particular ordering guaranteed; so if the order of - * writes is significant, calling code should divide a single call - * into multiple calls. - */ -void gpio_output_set(uint32_t set_mask, - uint32_t clear_mask, - uint32_t enable_mask, - uint32_t disable_mask) ROMFN_ATTR; -void gpio_output_set_high(uint32_t set_mask, - uint32_t clear_mask, - uint32_t enable_mask, - uint32_t disable_mask) ROMFN_ATTR; -/* - * Sample the value of GPIO input pins and returns a bitmask. - */ -uint32_t gpio_input_get(void) ROMFN_ATTR; -uint32_t gpio_input_get_high(void) ROMFN_ATTR; +/** + * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); -/* - * Set the specified GPIO register to the specified value. - * This is a very general and powerful interface that is not - * expected to be used during normal operation. It is intended - * mainly for debug, or for unusual requirements. - */ -void gpio_register_set(uint32_t reg_id, uint32_t value) ROMFN_ATTR; +/** + * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); -/* Get the current value of the specified GPIO register. */ -uint32_t gpio_register_get(uint32_t reg_id) ROMFN_ATTR; +/** + * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32. + */ +uint32_t gpio_input_get_high(void); -/* - * Register an application-specific interrupt handler for GPIO pin - * interrupts. Once the interrupt handler is called, it will not - * be called again until after a call to gpio_intr_ack. Any GPIO - * interrupts that occur during the interim are masked. - * - * The application-specific handler is called with a mask of - * pending GPIO interrupts. After processing pin interrupts, the - * application-specific handler may wish to use gpio_intr_pending - * to check for any additional pending interrupts before it returns. - */ -void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg) ROMFN_ATTR; +/** + * @brief Register an application-specific interrupt handler for GPIO pin interrupts. + * Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack. + * Please do not call this function in SDK. + * + * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler + * + * @param void *arg : gpio application-specific interrupt handler argument. + * + * @return None + */ +void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); -/* Determine which GPIO interrupts are pending. */ -uint32_t gpio_intr_pending(void) ROMFN_ATTR; -uint32_t gpio_intr_pending_high(void) ROMFN_ATTR; +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0. + */ +uint32_t gpio_intr_pending(void); -/* - * Acknowledge GPIO interrupts. - * Intended to be called from the gpio_intr_handler_fn. - */ -void gpio_intr_ack(uint32_t ack_mask) ROMFN_ATTR; -void gpio_intr_ack_high(uint32_t ack_mask) ROMFN_ATTR; +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32. + */ +uint32_t gpio_intr_pending_high(void); -void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state) ROMFN_ATTR; +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0. + * + * @return None + */ +void gpio_intr_ack(uint32_t ack_mask); -void gpio_pin_wakeup_disable() ROMFN_ATTR; +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32. + * + * @return None + */ +void gpio_intr_ack_high(uint32_t ack_mask); -//extern void gpio_module_install(struct gpio_api *api); +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); -void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) ROMFN_ATTR; +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); -void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv) ROMFN_ATTR; +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~0x27 + * gpio == 0x30, input 0 to signal + * gpio == 0x34, ??? + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~0x27 + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x100, cancel output put to the gpio + * + * @param bool out_inv : the signal output is inv or not + * + * @param bool oen_inv : the signal output enable is inv or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_select_gpio(uint8_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @param uint8_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_pullup(uint8_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_pulldown(uint8_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_unhold(uint8_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x27 + * + * @return None + */ +void gpio_pad_hold(uint8_t gpio_num); + +/** + * @} + */ #ifdef __cplusplus } diff --git a/components/esp32/include/rom/rtc.h b/components/esp32/include/rom/rtc.h index 31323646f..d8c0c789a 100644 --- a/components/esp32/include/rom/rtc.h +++ b/components/esp32/include/rom/rtc.h @@ -26,30 +26,68 @@ extern "C" { #endif +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3ff61000+SIZE_CP Slow 6144-SIZE_CP + * 0x3ff62800 Slow 2048 Reserved + * + * 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * Rtc store registers usage + * RTC_STORE0 + * RTC_STORE1 + * RTC_STORE2 + * RTC_STORE3 + * RTC_STORE4 Reserved + * RTC_STORE5 External Xtal Frequency + * RTC_STORE6 FAST_RTC_MEMORY_ENTRY + * RTC_STORE7 FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ +#define RTC_ENTRY_ADDR RTC_STORE6 +#define RTC_MEMORY_CRC RTC_STORE7 + + typedef enum { - AWAKE = 0, //CPU ON + AWAKE = 0, // 1 : skip (n - 1) commands. + */ +uint16_t SPI_Common_Command(SpiCommonCmd *cmd); + +/** + * @brief Unlock SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return SPI_FLASH_RESULT_OK : Unlock OK. + * SPI_FLASH_RESULT_ERR : Unlock error. + * SPI_FLASH_RESULT_TIMEOUT : Unlock timeout. + */ +SpiFlashOpResult SPIUnlock(void); + +/** + * @brief SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return SPI_FLASH_RESULT_OK : Lock OK. + * SPI_FLASH_RESULT_ERR : Lock error. + * SPI_FLASH_RESULT_TIMEOUT : Lock timeout. + */ +SpiFlashOpResult SPILock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return SPI_FLASH_RESULT_OK : Update OK. + * SPI_FLASH_RESULT_ERR : Update error. + * SPI_FLASH_RESULT_TIMEOUT : Update timeout. + */ +SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseChip(void); + +/** + * @brief Erase a block of flash. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseBlock(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseSector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return SPI_FLASH_RESULT_OK : Erase OK. + * SPI_FLASH_RESULT_ERR : Erase error. + * SPI_FLASH_RESULT_TIMEOUT : Erase timeout. + */ +SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return SPI_FLASH_RESULT_OK : Write OK. + * SPI_FLASH_RESULT_ERR : Write error. + * SPI_FLASH_RESULT_TIMEOUT : Write timeout. + */ +SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return SPI_FLASH_RESULT_OK : Read OK. + * SPI_FLASH_RESULT_ERR : Read error. + * SPI_FLASH_RESULT_TIMEOUT : Read timeout. + */ +SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void SPI_Write_Encrypt_Enable(void); + +/** + * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @return SPI_FLASH_RESULT_OK : Prepare OK. + * SPI_FLASH_RESULT_ERR : Prepare error. + * SPI_FLASH_RESULT_TIMEOUT : Prepare timeout. + */ +SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void SPI_Write_Encrypt_Disable(void); + +/** + * @brief Encrpto writing data to flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return SPI_FLASH_RESULT_OK : Encrypto write OK. + * SPI_FLASH_RESULT_ERR : Encrypto write error. + * SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len); + +/** + * @} + */ #ifdef __cplusplus } diff --git a/components/esp32/include/rom/ssc.h b/components/esp32/include/rom/ssc.h deleted file mode 100755 index 509e0da2f..000000000 --- a/components/esp32/include/rom/ssc.h +++ /dev/null @@ -1,85 +0,0 @@ -// Copyright 2011-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _ROM_SSC_H_ -#define _ROM_SSC_H_ - -#include "esp_types.h" - -#include "esp_attr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct cmd_s { - char *cmd_str; -#define CMD_T_ASYNC 0x01 -#define CMD_T_SYNC 0x02 - uint8_t flag; - uint8_t id; - void (* cmd_func)(void); - void (* cmd_callback)(void *arg); -} ssc_cmd_t; - -#define ssc_printf ets_printf -#define SSC_CMD_N 10 //since the command not added in ssc_cmd.c -#define MAX_LINE_N 40 -#define PROMPT ":>" -#define SSC_EVT_N 4 - - -#define SSC_PRIO 30 -enum { - CMD_SET_SSID = 0, - CMD_SCAN, - CMD_CONNECT, - CMD_DISCONNECT, - CMD_SET_MACADDR, - CMD_PING, - CMD_PING_COUNT, - CMD_PING_LENGTH, - CMD_SET_IP, -// CMD_RD_I2C, -// CMD_SET_NULL, it's just for solving the old rom bug -// CMD_SET_I2C, -// CMD_RD_I2CM, -// CMD_SET_I2CM, -// CMD_SET_PBUS, -// CMD_SET_TXTONE, -// CMD_SET_STOPTONE, - CMD_END, -}; - -enum { - SIG_SSC_RUNCMD, - SIG_SSC_CMDDONE, - SIG_SSC_RESTART, - SIG_SSC_UART_RX_CHAR, -}; - -void ssc_attach(void) ROMFN_ATTR; -void ssc_cmd_done(int cmd_id, STATUS status) ROMFN_ATTR; -int ssc_param_len(void) ROMFN_ATTR; -char * ssc_param_str(void) ROMFN_ATTR; -void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void)) ROMFN_ATTR; - -extern ssc_cmd_t sscCmdSet[]; -void ssc_help(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_SSC_H_ */ diff --git a/components/esp32/include/rom/uart.h b/components/esp32/include/rom/uart.h old mode 100755 new mode 100644 index b29569773..8e3125133 --- a/components/esp32/include/rom/uart.h +++ b/components/esp32/include/rom/uart.h @@ -22,6 +22,14 @@ extern "C" { #endif +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + #define RX_BUFF_SIZE 0x100 #define TX_BUFF_SIZE 100 @@ -52,9 +60,9 @@ extern "C" { #define UART_RCV_ERR_FLAG BIT7 //send and receive message frame head -#define FRAME_FLAG 0x7E +#define FRAME_FLAG 0x7E -typedef enum{ +typedef enum { UART_LINE_STATUS_INT_FLAG = 0x06, UART_RCV_FIFO_INT_FLAG = 0x04, UART_RCV_TMOUT_INT_FLAG = 0x0C, @@ -82,9 +90,9 @@ typedef enum { } UartStopBitsNum; typedef enum { - NONE_BITS = 0, - ODD_BITS = 2, - EVEN_BITS = 3 + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 } UartParityMode; @@ -113,7 +121,7 @@ typedef enum { typedef enum { EMPTY, UNDER_WRITE, - WRITE_OVER + WRITE_OVER } RcvMsgBuffState; typedef struct { @@ -121,9 +129,9 @@ typedef struct { uint8_t *pRcvMsgBuff; uint8_t *pWritePos; uint8_t *pReadPos; - uint8_t TrigLvl; //JLU: may need to pad + uint8_t TrigLvl; RcvMsgBuffState BuffState; -}RcvMsgBuff; +} RcvMsgBuff; typedef struct { uint32_t TrxBuffSize; @@ -138,7 +146,7 @@ typedef enum { RCV_ESC_CHAR, } RcvMsgState; -typedef struct{ +typedef struct { UartBautRate baut_rate; UartBitsNum4Char data_bits; UartExistParity exist_parity; @@ -153,33 +161,249 @@ typedef struct{ int received; } UartDevice; -void Uart_Init(uint8_t uart_no, uint32_t clock) ROMFN_ATTR; -STATUS UartTxString(uint8_t* pString) ROMFN_ATTR; -STATUS UartRxString(uint8_t* pString, uint8_t MaxStrlen) ROMFN_ATTR; +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void uartAttach(void); -STATUS uart_tx_one_char(uint8_t TxChar) ROMFN_ATTR;//for print -STATUS uart_tx_one_char2(uint8_t TxChar) ROMFN_ATTR;//for send message -STATUS uart_rx_one_char(uint8_t* pRxChar) ROMFN_ATTR; -char uart_rx_one_char_block(void) ROMFN_ATTR; -void uart_rx_intr_handler(void * para) ROMFN_ATTR; -STATUS uart_rx_readbuff( RcvMsgBuff* pRxBuff, uint8_t* pRxByte) ROMFN_ATTR; -STATUS UartGetCmdLn(uint8_t * pCmdLn) ROMFN_ATTR; -UartDevice * GetUartDevice() ROMFN_ATTR; +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); -void uartToggleInterrupt(bool en) ROMFN_ATTR; +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -STATUS SendMsg(uint8_t *pData, uint16_t DataLen) ROMFN_ATTR; +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; + * 1, two UART modules, hard to detect, detect and return. + * + * @return None + */ +int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync) ROMFN_ATTR; +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Switch message exchange channel for UART download booting. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_buff_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char2(uint8_t TxChar);//for send message + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char to message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t DataLen : the string length. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS SendMsg(uint8_t *pData, uint16_t DataLen); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); -void uartAttach() ROMFN_ATTR; -void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue) ROMFN_ATTR; -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync) ROMFN_ATTR; -void uart_buff_switch(uint8_t uart_no) ROMFN_ATTR; -void uart_tx_flush(uint8_t uart_no) ROMFN_ATTR; -void uart_tx_wait_idle(uint8_t uart_no) ROMFN_ATTR; extern UartDevice UartDev; +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/components/esp32/include/rom/wdt.h b/components/esp32/include/rom/wdt.h deleted file mode 100644 index 04a31c329..000000000 --- a/components/esp32/include/rom/wdt.h +++ /dev/null @@ -1,40 +0,0 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _ROM_WDT_H_ -#define _ROM_WDT_H_ - -#include "soc.h" -#include "ets_sys.h" - -#define WDT_RESET_VALUE 0x73 -#define WDT_RESET_LEN 7 //real time: (1<<(WDT_RESET_LEN+1))*pclk -#define WDT_CONTROL_ENABLED BIT0 -#define WDT_MODE_SET(v) (v) -#define WDT_TARGET_SET(v) (v) -#define WDT_ADDRESS 0 - -#define SEC_TO_WDT_TICK(s) (s * WDT_CLK_FREQ) //it's Pclk clock,44MHz - -typedef enum{ - NEXT_OVERFLOW_RESET = 0, - NEXT_OVERFLOW_NO_RESET = 1, - EACH_OVERFLOW_RESET = 2, -} WDT_RESP_MODE; - -#define WDT_DEFAULT_FEED_INTERVAL WDT_INTERVAL_SIX_SEC /* 6 seconds */ -#define WDT_DEFAULT_EXPIRE_INTERVAL WDT_INTERVAL_TWELVE_SEC /* 12 seconds */ - -#endif /* _ROM_WDT_H_ */ - diff --git a/components/esp32/include/soc/io_mux_reg.h b/components/esp32/include/soc/io_mux_reg.h index bc9f769b7..e5027a71d 100644 --- a/components/esp32/include/soc/io_mux_reg.h +++ b/components/esp32/include/soc/io_mux_reg.h @@ -80,21 +80,24 @@ #define FUNC_GPIO33_GPIO33_0 0 #define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO25_EMAC_RXD0 5 #define FUNC_GPIO25_GPIO25 2 #define FUNC_GPIO25_GPIO25_0 0 #define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO26_EMAC_RXD1 5 #define FUNC_GPIO26_GPIO26 2 #define FUNC_GPIO26_GPIO26_0 0 #define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) -#define FUNC_GPIO27_EMAC_RXD2 5 +#define FUNC_GPIO27_EMAC_RX_DV 5 #define FUNC_GPIO27_GPIO27 2 #define FUNC_GPIO27_GPIO27_0 0 #define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) #define FUNC_MTMS_EMAC_TXD2 5 #define FUNC_MTMS_SD_CLK 4 +#define FUNC_MTMS_HS2_CLk 3 #define FUNC_MTMS_GPIO14 2 #define FUNC_MTMS_HSPICLK 1 #define FUNC_MTMS_MTMS 0 @@ -102,6 +105,7 @@ #define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) #define FUNC_MTDI_EMAC_TXD3 5 #define FUNC_MTDI_SD_DATA2 4 +#define FUNC_MTDI_HS2_DATA2 3 #define FUNC_MTDI_GPIO12 2 #define FUNC_MTDI_HSPIQ 1 #define FUNC_MTDI_MTDI 0 @@ -109,7 +113,7 @@ #define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) #define FUNC_MTCK_EMAC_RX_ER 5 #define FUNC_MTCK_SD_DATA3 4 -#define FUNC_MTCK_U0CTS 3 +#define FUNC_MTCK_HS2_DATA3 3 #define FUNC_MTCK_GPIO13 2 #define FUNC_MTCK_HSPID 1 #define FUNC_MTCK_MTCK 0 @@ -117,21 +121,20 @@ #define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) #define FUNC_MTDO_EMAC_RXD3 5 #define FUNC_MTDO_SD_CMD 4 -#define FUNC_MTDO_U0RTS 3 +#define FUNC_MTDO_HS2_CMD 3 #define FUNC_MTDO_GPIO15 2 #define FUNC_MTDO_HSPICS0 1 #define FUNC_MTDO_MTDO 0 #define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) -#define FUNC_GPIO2_EMAC_RX_DV 5 #define FUNC_GPIO2_SD_DATA0 4 +#define FUNC_GPIO2_HS2_DATA0 3 #define FUNC_GPIO2_GPIO2 2 #define FUNC_GPIO2_HSPIWP 1 #define FUNC_GPIO2_GPIO2_0 0 #define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) #define FUNC_GPIO0_EMAC_TX_CLK 5 -#define FUNC_GPIO0_HS2_CMD 3 #define FUNC_GPIO0_GPIO0 2 #define FUNC_GPIO0_CLK_OUT1 1 #define FUNC_GPIO0_GPIO0_0 0 @@ -139,6 +142,7 @@ #define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) #define FUNC_GPIO4_EMAC_TX_ER 5 #define FUNC_GPIO4_SD_DATA1 4 +#define FUNC_GPIO4_HS2_DATA1 3 #define FUNC_GPIO4_GPIO4 2 #define FUNC_GPIO4_HSPIHD 1 #define FUNC_GPIO4_GPIO4_0 0 @@ -207,15 +211,14 @@ #define FUNC_GPIO5_GPIO5_0 0 #define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) -#define FUNC_GPIO18_EMAC_TXD0 5 #define FUNC_GPIO18_HS1_DATA7 3 #define FUNC_GPIO18_GPIO18 2 #define FUNC_GPIO18_VSPICLK 1 #define FUNC_GPIO18_GPIO18_0 0 #define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74) -#define FUNC_GPIO19_EMAC_TXD1 5 -#define FUNC_GPIO19_HS2_DATA2 3 +#define FUNC_GPIO19_EMAC_TXD0 5 +#define FUNC_GPIO19_U0CTS 3 #define FUNC_GPIO19_GPIO19 2 #define FUNC_GPIO19_VSPIQ 1 #define FUNC_GPIO19_GPIO19_0 0 @@ -225,33 +228,30 @@ #define FUNC_GPIO20_GPIO20_0 0 #define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c) -#define FUNC_GPIO21_EMAC_RXD0 5 -#define FUNC_GPIO21_HS2_DATA3 3 +#define FUNC_GPIO21_EMAC_TX_EN 5 #define FUNC_GPIO21_GPIO21 2 #define FUNC_GPIO21_VSPIHD 1 #define FUNC_GPIO21_GPIO21_0 0 #define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80) -#define FUNC_GPIO22_EMAC_RXD1 5 -#define FUNC_GPIO22_HS2_CLK 3 +#define FUNC_GPIO22_EMAC_TXD1 5 +#define FUNC_GPIO22_U0RTS 3 #define FUNC_GPIO22_GPIO22 2 #define FUNC_GPIO22_VSPIWP 1 #define FUNC_GPIO22_GPIO22_0 0 #define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) -#define FUNC_U0RXD_HS2_DATA0 3 #define FUNC_U0RXD_GPIO3 2 #define FUNC_U0RXD_CLK_OUT2 1 #define FUNC_U0RXD_U0RXD 0 #define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) -#define FUNC_U0TXD_HS2_DATA1 3 +#define FUNC_U0TXD_EMAC_RXD2 3 #define FUNC_U0TXD_GPIO1 2 #define FUNC_U0TXD_CLK_OUT3 1 #define FUNC_U0TXD_U0TXD 0 #define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) -#define FUNC_GPIO23_EMAC_TX_EN 5 #define FUNC_GPIO23_HS1_STROBE 3 #define FUNC_GPIO23_GPIO23 2 #define FUNC_GPIO23_VSPID 1 diff --git a/components/esp32/include/soc/soc.h b/components/esp32/include/soc/soc.h index d542efe28..2deab13e5 100755 --- a/components/esp32/include/soc/soc.h +++ b/components/esp32/include/soc/soc.h @@ -58,98 +58,93 @@ #define BIT(nr) (1UL << (nr)) +//write value to register #define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +//read value from register #define REG_READ(_r) (*(volatile uint32_t *)(_r)) +//get bit or get bits from register #define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +//set bit or set bits to register #define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +//clear bit or clear bits of register #define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +//set bits of register controlled by mask #define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) -#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) -#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) -#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) -#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) -#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) -#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//get field from register, used when _f is not left shifted by _f##_S #define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f)) + +//set field to register, used when _f is not left shifted by _f##_S #define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))) +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register #define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) + +//write value to register #define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +//clear bits of register controlled by mask #define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask #define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask #define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift #define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) + +//get field of register #define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) //}} //Periheral Clock {{ -#define APB_CLK_FREQ_ROM 13*1000000 +#define APB_CLK_FREQ_ROM 26*1000000 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ 80*1000000 //unit: Hz #define UART_CLK_FREQ APB_CLK_FREQ -//#define WDT_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 #define SPI_CLK_DIV 4 -//#define RTC_CLK_FREQ 32768 //unit:Hz -//#define RTC_CLK_FREQ 100000 //unit:Hz -//#define CALIB_CLK_MHZ 40 -#define TICKS_PER_US 13 // CPU is 80MHz +#define TICKS_PER_US_ROM 26 // CPU is 80MHz //}} -#if 0 -//Peripheral device base address define{{ -#define DR_REG_DPORT_BASE 0x3ff00000 -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 //no -#define DR_REG_SPI0_BASE 0x60003000 //no -#define DR_REG_GPIO_BASE 0x60004000 //no -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 -#define DR_REG_TIMER_BASE 0x60007000 //no -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 - -#define DR_REG_RTCMEM0_BASE 0x60021000 -#define DR_REG_RTCMEM1_BASE 0x60022000 -#define DR_REG_RTCMEM2_BASE 0x60023000 - -#define DR_REG_IO_MUX_BASE 0x60009000 //no -#define DR_REG_WDG_BASE 0x6000A000 //no -#define DR_REG_HINF_BASE 0x6000B000 //no -#define DR_REG_UHCI1_BASE 0x6000C000 -//#define DR_REG_MISC_BASE 0x6000D000 //no use -#define DR_REG_I2C_BASE 0x6000E000 //no -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 -#define DR_REG_BT_BASE 0x60011000 -//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use -#define DR_REG_I2C_EXT_BASE 0x60013000 //no -#define DR_REG_UHCI0_BASE 0x60014000 -#define DR_REG_SLCHOST_BASE 0x60015000 -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_PCNT_BASE 0x60017000 -#define DR_REG_SLC_BASE 0x60018000 -#define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x6001A000 -#define DR_REG_SPI_ENCRYPT_BASE 0x6001B000 -#define DR_REG_PWM_BASE 0x6001C000 //no -#define DR_REG_TIMERGROUP_BASE 0x6001D000 //no -#define DR_REG_TIMERGROUP1_BASE 0x6001E000 //no -#define DR_REG_BB_BASE 0x6001F000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 -#else #define DR_REG_DPORT_BASE 0x3ff00000 #define DR_REG_UART_BASE 0x3ff40000 -#define DR_REG_SPI1_BASE 0x3ff42000 //no -#define DR_REG_SPI0_BASE 0x3ff43000 //no -#define DR_REG_GPIO_BASE 0x3ff44000 //no +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 #define DR_REG_FE2_BASE 0x3ff45000 #define DR_REG_FE_BASE 0x3ff46000 -#define DR_REG_TIMER_BASE 0x3ff47000 //no +#define DR_REG_TIMER_BASE 0x3ff47000 #define DR_REG_RTCCNTL_BASE 0x3ff48000 #define DR_REG_RTCIO_BASE 0x3ff48400 @@ -157,18 +152,16 @@ #define DR_REG_RTCMEM1_BASE 0x3ff62000 #define DR_REG_RTCMEM2_BASE 0x3ff63000 -#define DR_REG_IO_MUX_BASE 0x3ff49000 //no -#define DR_REG_WDG_BASE 0x3ff4A000 //no -#define DR_REG_HINF_BASE 0x3ff4B000 //no +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_WDG_BASE 0x3ff4A000 +#define DR_REG_HINF_BASE 0x3ff4B000 #define DR_REG_UHCI1_BASE 0x3ff4C000 -//#define DR_REG_MISC_BASE 0x6000D000 //no use -#define DR_REG_I2C_BASE 0x3ff4E000 //no +#define DR_REG_I2C_BASE 0x3ff4E000 #define DR_REG_I2S_BASE 0x3ff4F000 #define DR_REG_I2S1_BASE 0x3ff6D000 #define DR_REG_UART1_BASE 0x3ff50000 #define DR_REG_BT_BASE 0x3ff51000 -//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use -#define DR_REG_I2C_EXT_BASE 0x3ff53000 //no +#define DR_REG_I2C_EXT_BASE 0x3ff53000 #define DR_REG_UHCI0_BASE 0x3ff54000 #define DR_REG_SLCHOST_BASE 0x3ff55000 #define DR_REG_RMT_BASE 0x3ff56000 @@ -177,94 +170,139 @@ #define DR_REG_LEDC_BASE 0x3ff59000 #define DR_REG_EFUSE_BASE 0x3ff5A000 #define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 -#define DR_REG_PWM_BASE 0x3ff5C000 //no -#define DR_REG_TIMERS_BASE 0x3ff5F000 //no -#define DR_REG_TIMERGROUP1_BASE 0x3ff5E000 //no -#define DR_REG_BB_BASE 0x3ff5F000 +#define DR_REG_BB_BASE 0x3ff5C000 +#define DR_REG_PWM_BASE 0x3ff5E000 +#define DR_REG_TIMERS_BASE(i) (0x3ff5F000 + i * (0x1000)) #define DR_REG_GPIO_SD_BASE 0x3ff44f00 -#endif //}} #define REG_SPI_BASE(i) (DR_REG_SPI0_BASE - i*(0x1000)) #define PERIPHS_TIMER_BASEDDR DR_REG_TIMER_BASE #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE -#define UART0_UNHOLD_MASK 0x3 -#define UART1_UNHOLD_MASK 0x60 -#define SDIO_UNHOLD_MASK 0xfc -#define SPI_UNHOLD_MASK 0xfc +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ +#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ +#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ +#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ +#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ +#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ +#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ +#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ +#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ +#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ +#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ +#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ +#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ +#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ +#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ +#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ +#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ +#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ +#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ +#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ +#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ +#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ +#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ +#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ +#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ +#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ +#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ +#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ +#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ +#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ +#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ +#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ +#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ +#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ +#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ +#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/ +#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/ +#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ +#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ +#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/ +#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ +#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ +#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ +#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ +#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ +#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ +#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ +#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ +#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ +#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ +#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ +#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ +#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ +#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ +#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ +#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ +#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ +#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ +#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ +#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ +#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ +#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ -// TIMER reg {{ -#define TIMER_REG_READ(addr) READ_PERI_REG(addr) -#define TIMER_REG_WRITE(addr, val) WRITE_PERI_REG(addr, val) -#define TIMER_SET_REG_MASK(reg, mask) WRITE_PERI_REG(reg, (READ_PERI_REG(reg)|(mask))) -/* Returns the current time according to the timer timer. */ -#define NOW() TIMER_REG_READ(FRC2_COUNT_ADDRESS) -//load initial_value to timer1 -#define FRC1_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR +0x00) -#define FRC1_LOAD_DATA_MSB 22 -#define FRC1_LOAD_DATA_LSB 0 -#define FRC1_LOAD_DATA_MASK 0x007fffff +//interrupt cpu using table, Please see the core-isa.h +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host Reserved + * 2 1 extern level FROM_CPU FROM_CPU + * 3 1 extern level TG0_WDT Reserved + * 4 1 extern level WBB + * 5 1 extern level Reserved + * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) + * 7 1 software Reserved Reserved + * 8 1 extern level Reserved + * 9 1 extern level + * 10 1 extern edge Internal Timer + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level + * 25 4 extern level Reserved Reserved + * 26 5 extern level Reserved Reserved + * 27 3 extern level Reserved Reserved + * 28 4 extern edge + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level Reserved Reserved + ************************************************************************************************************* + */ -//timer1's counter value(count from initial_value to 0) -#define FRC1_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x04) -#define FRC1_COUNT_DATA_MSB 22 -#define FRC1_COUNT_DATA_LSB 0 -#define FRC1_COUNT_DATA_MASK 0x007fffff +//CPU0 Interrupt number reserved, not touch this. +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_FROM_CPU_INUM 2 +#define ETS_T0_WDT_INUM 3 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ -#define FRC1_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR +0x08) -#define FRC1_CTRL_DATA_MSB 7 -#define FRC1_CTRL_DATA_LSB 0 -#define FRC1_CTRL_DATA_MASK 0x000000ff +//CPU0 Intrrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 -//clear timer1's interrupt when write this address -#define FRC1_INT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x0c) -#define FRC1_INT_CLR_MSB 0 -#define FRC1_INT_CLR_LSB 0 -#define FRC1_INT_CLR_MASK 0x00000001 -//only used for simulation -#define FRC1_TEST_ADDRESS (PERIPHS_TIMER_BASEDDR +0x10) -#define FRC1_TEST_MODE_MSB 0 -#define FRC1_TEST_MODE_LSB 0 -#define FRC1_TEST_MODE_MASK 0x00000001 - -//load initial_value to timer2 -#define FRC2_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR +0x20) -#define FRC2_LOAD_DATA_MSB 31 -#define FRC2_LOAD_DATA_LSB 0 -#define FRC2_LOAD_DATA_MASK 0xffffffff - -//timer2's counter value(count from initial_value to 0) -#define FRC2_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x24) -#define FRC2_COUNT_DATA_MSB 31 -#define FRC2_COUNT_DATA_LSB 0 -#define FRC2_COUNT_DATA_MASK 0xffffffff - -#define FRC2_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR +0x28) -#define FRC2_CTRL_DATA_MSB 7 -#define FRC2_CTRL_DATA_LSB 0 -#define FRC2_CTRL_DATA_MASK 0x000000ff - -//clear interrupt when write this address -#define FRC2_INT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x2c) -#define FRC2_INT_CLR_MSB 0 -#define FRC2_INT_CLR_LSB 0 -#define FRC2_INT_CLR_MASK 0x00000001 - -//set Alarm_value for timer2 to generate interrupt -#define FRC2_ALARM_ADDRESS (PERIPHS_TIMER_BASEDDR +0x30) -#define FRC2_ALARM_DATA_MSB 31 -#define FRC2_ALARM_DATA_LSB 0 -#define FRC2_ALARM_DATA_MASK 0xffffffff -// }} - -#define SPI_ENCRYPT_CNTL (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x20) -#define SPI_ENCRYPT_CNTL_ENA BIT(0) - -#define SPI_ENCRYPT_ADDR (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x24) - -#define SPI_ENCRYPT_CHECKDONE (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x28) -#define SPI_ENCRYPT_CHECKDONE_STATUS BIT(0) #endif /* _ESP32_SOC_H_ */ diff --git a/components/esp32/include/soc/timers_reg.h b/components/esp32/include/soc/timers_reg.h index 577f375aa..21ddfafcb 100644 --- a/components/esp32/include/soc/timers_reg.h +++ b/components/esp32/include/soc/timers_reg.h @@ -16,7 +16,7 @@ #include "soc.h" -#define T0CONFIG (DR_REG_TIMERS_BASE + 0x0000) +#define T0CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0000) #define TIMERS_T0_EN (BIT(31)) #define TIMERS_T0_EN_S 31 #define TIMERS_T0_INCREASE (BIT(30)) @@ -32,39 +32,39 @@ #define TIMERS_T0_ALARM_EN (BIT(10)) #define TIMERS_T0_ALARM_EN_S 10 -#define T0LO (DR_REG_TIMERS_BASE + 0x0004) +#define T0LO(i) (DR_REG_TIMERS_BASE(i) + 0x0004) #define TIMERS_T0_LO 0xFFFFFFFF #define TIMERS_T0_LO_S 0 -#define T0HI (DR_REG_TIMERS_BASE + 0x0008) +#define T0HI(i) (DR_REG_TIMERS_BASE(i) + 0x0008) #define TIMERS_T0_HI 0xFFFFFFFF #define TIMERS_T0_HI_S 0 -#define T0UPDATE (DR_REG_TIMERS_BASE + 0x000c) +#define T0UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x000c) #define TIMERS_T0_UPDATE 0xFFFFFFFF #define TIMERS_T0_UPDATE_S 0 -#define T0ALARMLO (DR_REG_TIMERS_BASE + 0x0010) +#define T0ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0010) #define TIMERS_T0_ALARM_LO 0xFFFFFFFF #define TIMERS_T0_ALARM_LO_S 0 -#define T0ALARMHI (DR_REG_TIMERS_BASE + 0x0014) +#define T0ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0014) #define TIMERS_T0_ALARM_HI 0xFFFFFFFF #define TIMERS_T0_ALARM_HI_S 0 -#define T0LOADLO (DR_REG_TIMERS_BASE + 0x0018) +#define T0LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x0018) #define TIMERS_T0_LOAD_LO 0xFFFFFFFF #define TIMERS_T0_LOAD_LO_S 0 -#define T0LOADHI (DR_REG_TIMERS_BASE + 0x001c) +#define T0LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x001c) #define TIMERS_T0_LOAD_HI 0xFFFFFFFF #define TIMERS_T0_LOAD_HI_S 0 -#define T0LOAD (DR_REG_TIMERS_BASE + 0x0020) +#define T0LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0020) #define TIMERS_T0_LOAD 0xFFFFFFFF #define TIMERS_T0_LOAD_S 0 -#define T1CONFIG (DR_REG_TIMERS_BASE + 0x0024) +#define T1CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0024) #define TIMERS_T1_EN (BIT(31)) #define TIMERS_T1_EN_S 31 #define TIMERS_T1_INCREASE (BIT(30)) @@ -80,39 +80,39 @@ #define TIMERS_T1_ALARM_EN (BIT(10)) #define TIMERS_T1_ALARM_EN_S 10 -#define T1LO (DR_REG_TIMERS_BASE + 0x0028) +#define T1LO(i) (DR_REG_TIMERS_BASE(i) + 0x0028) #define TIMERS_T1_LO 0xFFFFFFFF #define TIMERS_T1_LO_S 0 -#define T1HI (DR_REG_TIMERS_BASE + 0x002c) +#define T1HI(i) (DR_REG_TIMERS_BASE(i) + 0x002c) #define TIMERS_T1_HI 0xFFFFFFFF #define TIMERS_T1_HI_S 0 -#define T1UPDATE (DR_REG_TIMERS_BASE + 0x0030) +#define T1UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0030) #define TIMERS_T1_UPDATE 0xFFFFFFFF #define TIMERS_T1_UPDATE_S 0 -#define T1ALARMLO (DR_REG_TIMERS_BASE + 0x0034) +#define T1ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0034) #define TIMERS_T1_ALARM_LO 0xFFFFFFFF #define TIMERS_T1_ALARM_LO_S 0 -#define T1ALARMHI (DR_REG_TIMERS_BASE + 0x0038) +#define T1ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0038) #define TIMERS_T1_ALARM_HI 0xFFFFFFFF #define TIMERS_T1_ALARM_HI_S 0 -#define T1LOADLO (DR_REG_TIMERS_BASE + 0x003c) +#define T1LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x003c) #define TIMERS_T1_LOAD_LO 0xFFFFFFFF #define TIMERS_T1_LOAD_LO_S 0 -#define T1LOADHI (DR_REG_TIMERS_BASE + 0x0040) +#define T1LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0040) #define TIMERS_T1_LOAD_HI 0xFFFFFFFF #define TIMERS_T1_LOAD_HI_S 0 -#define T1LOAD (DR_REG_TIMERS_BASE + 0x0044) +#define T1LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0044) #define TIMERS_T1_LOAD 0xFFFFFFFF #define TIMERS_T1_LOAD_S 0 -#define WDTCONFIG0 (DR_REG_TIMERS_BASE + 0x0048) +#define WDTCONFIG0(i) (DR_REG_TIMERS_BASE(i) + 0x0048) #define TIMERS_WDT_EN (BIT(31)) #define TIMERS_WDT_EN_S 31 #define TIMERS_WDT_STG0 0x00000003 @@ -134,35 +134,35 @@ #define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14)) #define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14 -#define WDTCONFIG1 (DR_REG_TIMERS_BASE + 0x004c) +#define WDTCONFIG1(i) (DR_REG_TIMERS_BASE(i) + 0x004c) #define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF #define TIMERS_WDT_CLK_PRESCALE_S 16 -#define WDTCONFIG2 (DR_REG_TIMERS_BASE + 0x0050) +#define WDTCONFIG2(i) (DR_REG_TIMERS_BASE(i) + 0x0050) #define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF #define TIMERS_WDT_STG0_HOLD_S 0 -#define WDTCONFIG3 (DR_REG_TIMERS_BASE + 0x0054) +#define WDTCONFIG3(i) (DR_REG_TIMERS_BASE(i) + 0x0054) #define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF #define TIMERS_WDT_STG1_HOLD_S 0 -#define WDTCONFIG4 (DR_REG_TIMERS_BASE + 0x0058) +#define WDTCONFIG4(i) (DR_REG_TIMERS_BASE(i) + 0x0058) #define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF #define TIMERS_WDT_STG2_HOLD_S 0 -#define WDTCONFIG5 (DR_REG_TIMERS_BASE + 0x005c) +#define WDTCONFIG5(i) (DR_REG_TIMERS_BASE(i) + 0x005c) #define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF #define TIMERS_WDT_STG3_HOLD_S 0 -#define WDTFEED (DR_REG_TIMERS_BASE + 0x0060) +#define WDTFEED(i) (DR_REG_TIMERS_BASE(i) + 0x0060) #define TIMERS_WDT_FEED 0xFFFFFFFF #define TIMERS_WDT_FEED_S 0 -#define WDTWPROTECT (DR_REG_TIMERS_BASE + 0x0064) +#define WDTWPROTECT(i) (DR_REG_TIMERS_BASE(i) + 0x0064) #define TIMERS_WDT_WKEY 0xFFFFFFFF #define TIMERS_WDT_WKEY_S 0 -#define RTCCALICFG (DR_REG_TIMERS_BASE + 0x0068) +#define RTCCALICFG(i) (DR_REG_TIMERS_BASE(i) + 0x0068) #define TIMERS_RTC_CALI_START (BIT(31)) #define TIMERS_RTC_CALI_START_S 31 #define TIMERS_RTC_CALI_MAX 0x00007FFF @@ -174,11 +174,11 @@ #define TIMERS_RTC_CALI_START_CYCLING (BIT(12)) #define TIMERS_RTC_CALI_START_CYCLING_S 12 -#define RTCCALICFG1 (DR_REG_TIMERS_BASE + 0x006c) +#define RTCCALICFG1(i) (DR_REG_TIMERS_BASE(i) + 0x006c) #define TIMERS_RTC_CALI_VALUE 0x01FFFFFF #define TIMERS_RTC_CALI_VALUE_S 7 -#define LACTCONFIG (DR_REG_TIMERS_BASE + 0x0070) +#define LACTCONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0070) #define TIMERS_LACT_EN (BIT(31)) #define TIMERS_LACT_EN_S 31 #define TIMERS_LACT_INCREASE (BIT(30)) @@ -200,43 +200,43 @@ #define TIMERS_LACT_RTC_ONLY (BIT(7)) #define TIMERS_LACT_RTC_ONLY_S 7 -#define LACTRTC (DR_REG_TIMERS_BASE + 0x0074) +#define LACTRTC(i) (DR_REG_TIMERS_BASE(i) + 0x0074) #define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF #define TIMERS_LACT_RTC_STEP_LEN_S 6 -#define LACTLO (DR_REG_TIMERS_BASE + 0x0078) +#define LACTLO(i) (DR_REG_TIMERS_BASE(i) + 0x0078) #define TIMERS_LACT_LO 0xFFFFFFFF #define TIMERS_LACT_LO_S 0 -#define LACTHI (DR_REG_TIMERS_BASE + 0x007c) +#define LACTHI(i) (DR_REG_TIMERS_BASE(i) + 0x007c) #define TIMERS_LACT_HI 0xFFFFFFFF #define TIMERS_LACT_HI_S 0 -#define LACTUPDATE (DR_REG_TIMERS_BASE + 0x0080) +#define LACTUPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0080) #define TIMERS_LACT_UPDATE 0xFFFFFFFF #define TIMERS_LACT_UPDATE_S 0 -#define LACTALARMLO (DR_REG_TIMERS_BASE + 0x0084) +#define LACTALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0084) #define TIMERS_LACT_ALARM_LO 0xFFFFFFFF #define TIMERS_LACT_ALARM_LO_S 0 -#define LACTALARMHI (DR_REG_TIMERS_BASE + 0x0088) +#define LACTALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0088) #define TIMERS_LACT_ALARM_HI 0xFFFFFFFF #define TIMERS_LACT_ALARM_HI_S 0 -#define LACTLOADLO (DR_REG_TIMERS_BASE + 0x008c) +#define LACTLOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x008c) #define TIMERS_LACT_LOAD_LO 0xFFFFFFFF #define TIMERS_LACT_LOAD_LO_S 0 -#define LACTLOADHI (DR_REG_TIMERS_BASE + 0x0090) +#define LACTLOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0090) #define TIMERS_LACT_LOAD_HI 0xFFFFFFFF #define TIMERS_LACT_LOAD_HI_S 0 -#define LACTLOAD (DR_REG_TIMERS_BASE + 0x0094) +#define LACTLOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0094) #define TIMERS_LACT_LOAD 0xFFFFFFFF #define TIMERS_LACT_LOAD_S 0 -#define INT_ENA_TIMERS (DR_REG_TIMERS_BASE + 0x0098) +#define INT_ENA_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x0098) #define TIMERS_LACT_INT_ENA (BIT(3)) #define TIMERS_LACT_INT_ENA_S 3 #define TIMERS_WDT_INT_ENA (BIT(2)) @@ -246,7 +246,7 @@ #define TIMERS_T0_INT_ENA (BIT(0)) #define TIMERS_T0_INT_ENA_S 0 -#define INT_RAW_TIMERS (DR_REG_TIMERS_BASE + 0x009c) +#define INT_RAW_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x009c) #define TIMERS_LACT_INT_RAW (BIT(3)) #define TIMERS_LACT_INT_RAW_S 3 #define TIMERS_WDT_INT_RAW (BIT(2)) @@ -256,7 +256,7 @@ #define TIMERS_T0_INT_RAW (BIT(0)) #define TIMERS_T0_INT_RAW_S 0 -#define INT_ST_TIMERS (DR_REG_TIMERS_BASE + 0x00a0) +#define INT_ST_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a0) #define TIMERS_LACT_INT_ST (BIT(3)) #define TIMERS_LACT_INT_ST_S 3 #define TIMERS_WDT_INT_ST (BIT(2)) @@ -266,7 +266,7 @@ #define TIMERS_T0_INT_ST (BIT(0)) #define TIMERS_T0_INT_ST_S 0 -#define INT_CLR_TIMERS (DR_REG_TIMERS_BASE + 0x00a4) +#define INT_CLR_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a4) #define TIMERS_LACT_INT_CLR (BIT(3)) #define TIMERS_LACT_INT_CLR_S 3 #define TIMERS_WDT_INT_CLR (BIT(2)) @@ -276,12 +276,12 @@ #define TIMERS_T0_INT_CLR (BIT(0)) #define TIMERS_T0_INT_CLR_S 0 -#define NTIMERS_DATE (DR_REG_TIMERS_BASE + 0x00f8) +#define NTIMERS_DATE(i) (DR_REG_TIMERS_BASE(i) + 0x00f8) #define TIMERS_NTIMERS_DATE 0x0FFFFFFF #define TIMERS_NTIMERS_DATE_S 0 #define TIMERS_NTIMERS_DATE_VERSION 0x1604290 -#define REGCLK (DR_REG_TIMERS_BASE + 0x00fc) +#define REGCLK(i) (DR_REG_TIMERS_BASE(i) + 0x00fc) #define TIMERS_CLK_EN (BIT(31)) #define TIMERS_CLK_EN_S 31 diff --git a/components/esp32/ld/esp32.rom.ld b/components/esp32/ld/esp32.rom.ld index 3777405fe..823ca4c6e 100644 --- a/components/esp32/ld/esp32.rom.ld +++ b/components/esp32/ld/esp32.rom.ld @@ -64,6 +64,8 @@ PROVIDE ( Cache_Read_Disable = 0x40009ab8 ); PROVIDE ( Cache_Read_Enable = 0x40009a84 ); PROVIDE ( Cache_Read_Init = 0x40009950 ); PROVIDE ( cache_sram_mmu_set = 0x400097f4 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( calc_rtc_memory_crc = 0x40008170 ); PROVIDE ( calloc = 0x4000bee4 ); PROVIDE ( _calloc_r = 0x4000bbf8 ); PROVIDE ( check_pos = 0x400068b8 ); @@ -1585,12 +1587,20 @@ PROVIDE ( SPIParamCfg = 0x40063238 ); PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c ); PROVIDE ( SPIRead = 0x40062ed8 ); PROVIDE ( SPIReadModeCnfig = 0x40062944 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_read_status = 0x4006226c ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_read_status_high = 0x40062448 ); PROVIDE ( SPIUnlock = 0x400628b0 ); PROVIDE ( SPI_user_command_read = 0x400621b0 ); PROVIDE ( spi_w25q16 = 0x3ffae270 ); PROVIDE ( SPIWrite = 0x40062d50 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_write_enable = 0x40062320 ); PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 ); PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_write_status = 0x400622f0 ); PROVIDE ( sprintf = 0x40056c08 ); PROVIDE ( _sprintf_r = 0x40056bbc ); PROVIDE ( __sprint_r = 0x400577e4 ); @@ -1826,4 +1836,4 @@ PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); -PROVIDE ( I2S0 = 0x6000F000 ); \ No newline at end of file +PROVIDE ( I2S0 = 0x6000F000 );