diff --git a/components/esp32/psram.c b/components/esp32/psram.c
index 52e0f01f6..93d1f99d2 100644
--- a/components/esp32/psram.c
+++ b/components/esp32/psram.c
@@ -306,154 +306,6 @@ static void psram_disable_qio_mode(psram_spi_num_t spi_num)
     psram_cmd_start(spi_num, PSRAM_CMD_QPI);
 }
 
-//The following helper functions aren't used in this code right now, but may be useful for other SPI RAM chips.
-#if 0
-
-static void psram_dma_cmd_write_config(uint32_t dst, uint32_t len, uint32_t dummy_bits)
-{
-    uint32_t addr = (PSRAM_QUAD_WRITE << 24) | dst;
-    psram_cmd_t ps_cmd;
-    switch(s_psram_mode) {
-        case PSRAM_CACHE_F80M_S80M:
-            ps_cmd.cmdBitLen = 0;
-            break;
-        case PSRAM_CACHE_F80M_S40M:
-        case PSRAM_CACHE_F40M_S40M:
-        default:
-            ps_cmd.cmdBitLen = 2;
-            break;
-    }
-    ps_cmd.cmd = 0;
-    ps_cmd.addr = &addr;
-    ps_cmd.addrBitLen = 32;
-    ps_cmd.txData = NULL;
-    ps_cmd.txDataBitLen = len * 8;
-    ps_cmd.rxData = NULL;
-    ps_cmd.rxDataBitLen = 0;
-    ps_cmd.dummyBitLen = dummy_bits;
-    psram_cmd_config(PSRAM_SPI_1, &ps_cmd);
-}
-
-static void psram_dma_qio_read_config(psram_spi_num_t spi_num, uint32_t src, uint32_t len)
-{
-    uint32_t addr = (PSRAM_FAST_READ_QUAD << 24) | src;
-    uint32_t dummy_bits = 0;
-    psram_cmd_t ps_cmd;
-    switch(s_psram_mode) {
-        case PSRAM_CACHE_F80M_S80M:
-            dummy_bits = 6+extra_dummy;
-            ps_cmd.cmdBitLen = 0;
-            break;
-        case PSRAM_CACHE_F80M_S40M:
-        case PSRAM_CACHE_F40M_S40M:
-        default:
-            dummy_bits = 6+extra_dummy;
-            ps_cmd.cmdBitLen = 2;
-            break;
-    }
-    ps_cmd.cmd = 0;
-    ps_cmd.addr = &addr;
-    ps_cmd.addrBitLen = 4*8;
-    ps_cmd.txDataBitLen = 0;
-    ps_cmd.txData = NULL;
-    ps_cmd.rxDataBitLen = len*8 ;
-    ps_cmd.rxData = NULL;
-    ps_cmd.dummyBitLen = dummy_bits;
-    psram_cmd_config(spi_num,&ps_cmd);
-}
-
-//switch psram burst length(32 bytes or 1024 bytes)
-//datasheet says it should be 1024 bytes by default
-//but they sent us a correction doc and told us it is 32 bytes for these samples
-static void psram_set_burst_length(psram_spi_num_t spi_num)
-{
-    psram_cmd_t ps_cmd;
-    switch (s_psram_mode) {
-        case PSRAM_CACHE_F80M_S80M:
-            ps_cmd.cmd = 0xC0;
-            ps_cmd.cmdBitLen = 8;
-            break;
-        case PSRAM_CACHE_F80M_S40M:
-        case PSRAM_CACHE_F40M_S40M:
-        default:
-            ps_cmd.cmd = 0x0030;
-            ps_cmd.cmdBitLen = 10;
-            break;
-    }
-    ps_cmd.addr = 0;
-    ps_cmd.addrBitLen = 0;
-    ps_cmd.txData = NULL;
-    ps_cmd.txDataBitLen = 0;
-    ps_cmd.rxData = NULL;
-    ps_cmd.rxDataBitLen = 0;
-    ps_cmd.dummyBitLen = 0;
-    psram_cmd_config(spi_num, &ps_cmd);
-    psram_cmd_start(spi_num, PSRAM_CMD_QPI);
-}
-
-//send reset command to psram(right now,we only send this command in QPI mode)
-//seems not working
-static void psram_reset_mode(psram_spi_num_t spi_num)
-{
-    psram_cmd_t ps_cmd;
-    uint32_t cmd_rst = 0x99066;
-    ps_cmd.txData = &cmd_rst;
-    ps_cmd.txDataBitLen = 20;
-    ps_cmd.addr = NULL;
-    ps_cmd.addrBitLen = 0;
-    ps_cmd.cmd = 0;
-    ps_cmd.cmdBitLen = 0;
-    ps_cmd.rxData = NULL;
-    ps_cmd.rxDataBitLen = 0;
-    ps_cmd.dummyBitLen = 0;
-    psram_cmd_config(spi_num, &ps_cmd);
-    psram_cmd_start(spi_num, PSRAM_CMD_QPI);
-}
-
-static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
-{
-    gpio_matrix_out(6, SPICLK_OUT_IDX, 0, 0);
-    gpio_matrix_out(11, SPICS0_OUT_IDX, 0, 0);
-    gpio_matrix_out(7, SPIQ_OUT_IDX, 0, 0);
-    gpio_matrix_in(7,SPIQ_IN_IDX, 0);
-    gpio_matrix_out(8, SPID_OUT_IDX, 0, 0);
-    gpio_matrix_in(8, SPID_IN_IDX, 0);
-    gpio_matrix_out(10, SPIWP_OUT_IDX, 0, 0);
-    gpio_matrix_in(10, SPIWP_IN_IDX, 0);
-    gpio_matrix_out(9, SPIHD_OUT_IDX, 0, 0);
-    gpio_matrix_in(9, SPIHD_IN_IDX, 0);
-    switch(mode){
-        case PSRAM_CACHE_F80M_S80M:
-        case PSRAM_CACHE_F80M_S40M:
-            SET_PERI_REG_MASK(SPI_USER_REG(0),SPI_USR_DUMMY); // dummy en
-            SET_PERI_REG_BITS(SPI_USER1_REG(0),SPI_USR_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_USR_DUMMY_CYCLELEN_S);  //DUMMY
-            break;
-        case PSRAM_CACHE_F40M_S40M:
-        default:
-            SET_PERI_REG_MASK(SPI_USER_REG(0),SPI_USR_DUMMY); // dummy en
-            SET_PERI_REG_BITS(SPI_USER1_REG(0),SPI_USR_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_USR_DUMMY_CYCLELEN_S);  //DUMMY
-            break;
-    }
-    //drive ability
-    SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_CLK_U,  FUN_DRV, 3 ,FUN_DRV_S);
-    SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA0_U,FUN_DRV, 3 ,FUN_DRV_S);
-    SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA1_U,FUN_DRV, 3 ,FUN_DRV_S);
-    SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA2_U,FUN_DRV, 3 ,FUN_DRV_S);
-    SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA3_U,FUN_DRV, 3 ,FUN_DRV_S);
-    SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_CMD_U,  FUN_DRV, 3 ,FUN_DRV_S);
-    //select pin function gpio
-    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U,2);
-    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U,2);
-    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U,2);
-    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U,2);
-
-    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U,2);
-    PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U,2);
-}
-
-
-#endif
-
 //read psram id
 static void psram_read_id(uint32_t* dev_id)
 {