Merge branch 'bugfix/timer_group_reset_ut' into 'master'
timer: remove check for POWERON_RESET in the test case, add esp_reset_reason API for s2beta See merge request espressif/esp-idf!6747
This commit is contained in:
commit
b7b4cd3418
8 changed files with 205 additions and 65 deletions
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@ -836,3 +836,56 @@ TEST_CASE("Timer interrupt register", "[hw_timer]")
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}
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}
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TEST_ASSERT_INT_WITHIN(100, heap_size, esp_get_free_heap_size());
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TEST_ASSERT_INT_WITHIN(100, heap_size, esp_get_free_heap_size());
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}
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}
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// The following test cases are used to check if the timer_group fix works.
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// Some applications use a software reset, at the reset time, timer_group happens to generate an interrupt.
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// but software reset does not clear interrupt status, this is not safe for application when enable the interrupt of timer_group.
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// This case will check under this fix, whether the interrupt status is cleared after timer_group initialization.
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static void timer_group_test_init(void)
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{
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static const uint32_t time_ms = 100; //Alarm value 100ms.
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static const uint16_t timer_div = 10; //Timer prescaler
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static const uint32_t ste_val = time_ms * (TIMER_BASE_CLK / timer_div / 1000);
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timer_config_t config = {
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.divider = timer_div,
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.counter_dir = TIMER_COUNT_UP,
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.counter_en = TIMER_PAUSE,
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.alarm_en = TIMER_ALARM_EN,
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.intr_type = TIMER_INTR_LEVEL,
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.auto_reload = true,
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};
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timer_init(TIMER_GROUP_0, TIMER_0, &config);
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timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL);
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timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, ste_val);
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//Now the timer is ready.
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//We only need to check the interrupt status and don't have to register a interrupt routine.
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}
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static void timer_group_test_first_stage(void)
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{
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static uint8_t loop_cnt = 0;
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timer_group_test_init();
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//Start timer
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timer_start(TIMER_GROUP_0, TIMER_0);
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//Waiting for timer_group to generate an interrupt
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while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
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loop_cnt++ < 100) {
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vTaskDelay(200);
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}
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//TIMERG0.int_raw.t0 == 1 means an interruption has occurred
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TEST_ASSERT(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0);
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esp_restart();
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}
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static void timer_group_test_second_stage(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
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timer_group_test_init();
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//After the timer_group is initialized, TIMERG0.int_raw.t0 should be cleared.
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TEST_ASSERT_EQUAL(0, TIMERG0.int_raw.t0);
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}
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TEST_CASE_MULTIPLE_STAGES("timer_group software reset test",
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"[intr_status][intr_status = 0]",
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timer_group_test_first_stage,
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timer_group_test_second_stage);
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@ -244,66 +244,4 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event",
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check_reset_reason_brownout);
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check_reset_reason_brownout);
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// The following test cases are used to check if the timer_group fix works.
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// Some applications use a software reset, at the reset time, timer_group happens to generate an interrupt.
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// but software reset does not clear interrupt status, this is not safe for application when enable the interrupt of timer_group.
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// This case will check under this fix, whether the interrupt status is cleared after timer_group initialization.
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static void timer_group_test_init(void)
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{
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static const uint32_t time_ms = 100; //Alarm value 100ms.
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static const uint16_t timer_div = 10; //Timer prescaler
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static const uint32_t ste_val = time_ms * (TIMER_BASE_CLK / timer_div / 1000);
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timer_config_t config = {
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.divider = timer_div,
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.counter_dir = TIMER_COUNT_UP,
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.counter_en = TIMER_PAUSE,
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.alarm_en = TIMER_ALARM_EN,
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.intr_type = TIMER_INTR_LEVEL,
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.auto_reload = true,
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};
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timer_init(TIMER_GROUP_0, TIMER_0, &config);
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timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL);
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timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, ste_val);
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//Now the timer is ready.
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//We only need to check the interrupt status and don't have to register a interrupt routine.
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}
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static void timer_group_test_first_stage(void)
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{
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RESET_REASON rst_res = rtc_get_reset_reason(0);
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if(rst_res != POWERON_RESET){
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printf("Not power on reset\n");
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}
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TEST_ASSERT_EQUAL(POWERON_RESET, rst_res);
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static uint8_t loop_cnt = 0;
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timer_group_test_init();
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//Start timer
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timer_start(TIMER_GROUP_0, TIMER_0);
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//Waiting for timer_group to generate an interrupt
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while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
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loop_cnt++ < 100) {
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vTaskDelay(200);
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}
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//TIMERG0.int_raw.t0 == 1 means an interruption has occurred
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TEST_ASSERT(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0);
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esp_restart();
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}
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static void timer_group_test_second_stage(void)
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{
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RESET_REASON rst_res = rtc_get_reset_reason(0);
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if(rst_res != SW_CPU_RESET){
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printf("Not software reset\n");
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}
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TEST_ASSERT_EQUAL(SW_CPU_RESET, rst_res);
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timer_group_test_init();
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//After the timer_group is initialized, TIMERG0.int_raw.t0 should be cleared.
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TEST_ASSERT_EQUAL(0, TIMERG0.int_raw.t0);
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}
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TEST_CASE_MULTIPLE_STAGES("timer_group software reset test",
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"[intr_status][intr_status = 0]",
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timer_group_test_first_stage,
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timer_group_test_second_stage);
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/* Not tested here: ESP_RST_SDIO */
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/* Not tested here: ESP_RST_SDIO */
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@ -26,6 +26,7 @@ else()
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"panic.c"
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"panic.c"
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"pm_esp32s2beta.c"
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"pm_esp32s2beta.c"
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"pm_trace.c"
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"pm_trace.c"
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"reset_reason.c"
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"sleep_modes.c"
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"sleep_modes.c"
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"spiram.c"
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"spiram.c"
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"spiram_psram.c"
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"spiram_psram.c"
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@ -123,6 +123,20 @@ void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, s
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abort();
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abort();
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}
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}
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/* These two weak stubs for esp_reset_reason_{get,set}_hint are used when
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* the application does not call esp_reset_reason() function, and
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* reset_reason.c is not linked into the output file.
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*/
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void __attribute__((weak)) esp_reset_reason_set_hint(esp_reset_reason_t hint)
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{
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}
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esp_reset_reason_t __attribute__((weak)) esp_reset_reason_get_hint(void)
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{
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return ESP_RST_UNKNOWN;
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}
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static bool abort_called;
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static bool abort_called;
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static __attribute__((noreturn)) inline void invoke_abort(void)
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static __attribute__((noreturn)) inline void invoke_abort(void)
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@ -149,6 +163,12 @@ void abort(void)
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#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
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#if !CONFIG_ESP32S2_PANIC_SILENT_REBOOT
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ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
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ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
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#endif
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#endif
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/* Calling code might have set other reset reason hint (such as Task WDT),
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* don't overwrite that.
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*/
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if (esp_reset_reason_get_hint() == ESP_RST_UNKNOWN) {
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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}
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invoke_abort();
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invoke_abort();
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}
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}
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@ -326,6 +346,10 @@ void panicHandler(XtExcFrame *frame)
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}
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}
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#endif //!CONFIG_FREERTOS_UNICORE
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#endif //!CONFIG_FREERTOS_UNICORE
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if (frame->exccause == PANIC_RSN_INTWDT_CPU0) {
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esp_reset_reason_set_hint(ESP_RST_INT_WDT);
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}
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haltOtherCore();
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haltOtherCore();
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panicPutStr("Guru Meditation Error: Core ");
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panicPutStr("Guru Meditation Error: Core ");
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panicPutDec(core_id);
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panicPutDec(core_id);
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@ -426,6 +450,7 @@ void xt_unhandled_exception(XtExcFrame *frame)
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return;
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return;
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}
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}
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panicPutStr(". Exception was unhandled.\r\n");
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panicPutStr(". Exception was unhandled.\r\n");
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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}
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}
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commonErrorHandler(frame);
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commonErrorHandler(frame);
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}
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}
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123
components/esp32s2beta/reset_reason.c
Normal file
123
components/esp32s2beta/reset_reason.c
Normal file
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@ -0,0 +1,123 @@
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// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_system.h"
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#include "esp32s2beta/rom/rtc.h"
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#include "esp_private/system_internal.h"
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#include "soc/rtc_periph.h"
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static void esp_reset_reason_clear_hint(void);
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static esp_reset_reason_t s_reset_reason;
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static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
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{
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switch (rtc_reset_reason) {
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case POWERON_RESET:
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return ESP_RST_POWERON;
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case RTC_SW_CPU_RESET:
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case RTC_SW_SYS_RESET:
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if (reset_reason_hint == ESP_RST_PANIC ||
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reset_reason_hint == ESP_RST_BROWNOUT ||
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reset_reason_hint == ESP_RST_TASK_WDT ||
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reset_reason_hint == ESP_RST_INT_WDT) {
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return reset_reason_hint;
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}
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return ESP_RST_SW;
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case DEEPSLEEP_RESET:
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return ESP_RST_DEEPSLEEP;
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case TG0WDT_SYS_RESET:
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return ESP_RST_TASK_WDT;
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case TG1WDT_SYS_RESET:
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return ESP_RST_INT_WDT;
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case RTCWDT_SYS_RESET:
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case RTCWDT_RTC_RESET:
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case SUPER_WDT_RESET:
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case RTCWDT_CPU_RESET: /* unused */
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case TG0WDT_CPU_RESET: /* unused */
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case TG1WDT_CPU_RESET: /* unused */
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return ESP_RST_WDT;
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case RTCWDT_BROWN_OUT_RESET:
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return ESP_RST_BROWNOUT;
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case SDIO_RESET:
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return ESP_RST_SDIO;
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case INTRUSION_RESET: /* unused */
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default:
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return ESP_RST_UNKNOWN;
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}
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}
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static void __attribute__((constructor)) esp_reset_reason_init(void)
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{
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esp_reset_reason_t hint = esp_reset_reason_get_hint();
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s_reset_reason = get_reset_reason(rtc_get_reset_reason(PRO_CPU_NUM),
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hint);
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if (hint != ESP_RST_UNKNOWN) {
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esp_reset_reason_clear_hint();
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}
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}
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esp_reset_reason_t esp_reset_reason(void)
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{
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return s_reset_reason;
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}
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/* Reset reason hint is stored in RTC_RESET_CAUSE_REG, a.k.a. RTC_CNTL_STORE6_REG,
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* a.k.a. RTC_ENTRY_ADDR_REG. It is safe to use this register both for the
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* deep sleep wake stub entry address and for reset reason hint, since wake stub
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* is only used for deep sleep reset, and in this case the reason provided by
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* rtc_get_reset_reason is unambiguous.
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*
|
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* Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
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* the value is replicated in low and high half-words. In addition to that,
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* MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
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* deep sleep wake stub address.
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*/
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#define RST_REASON_BIT 0x80000000
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#define RST_REASON_MASK 0x7FFF
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#define RST_REASON_SHIFT 16
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/* in IRAM, can be called from panic handler */
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void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
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{
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assert((hint & (~RST_REASON_MASK)) == 0);
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uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;
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REG_WRITE(RTC_RESET_CAUSE_REG, val);
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}
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||||||
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/* in IRAM, can be called from panic handler */
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esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void)
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{
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uint32_t reset_reason_hint = REG_READ(RTC_RESET_CAUSE_REG);
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uint32_t high = (reset_reason_hint >> RST_REASON_SHIFT) & RST_REASON_MASK;
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uint32_t low = reset_reason_hint & RST_REASON_MASK;
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if ((reset_reason_hint & RST_REASON_BIT) == 0 || high != low) {
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return ESP_RST_UNKNOWN;
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}
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return (esp_reset_reason_t) low;
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}
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static void esp_reset_reason_clear_hint(void)
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{
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REG_WRITE(RTC_RESET_CAUSE_REG, 0);
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}
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|
|
@ -168,8 +168,7 @@ static void task_wdt_isr(void *arg)
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if (twdt_config->panic){ //Trigger Panic if configured to do so
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if (twdt_config->panic){ //Trigger Panic if configured to do so
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ESP_EARLY_LOGE(TAG, "Aborting.");
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ESP_EARLY_LOGE(TAG, "Aborting.");
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portEXIT_CRITICAL_ISR(&twdt_spinlock);
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portEXIT_CRITICAL_ISR(&twdt_spinlock);
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// TODO: Add support reset reason for esp32s2beta.
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esp_reset_reason_set_hint(ESP_RST_TASK_WDT);
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// esp_reset_reason_set_hint(ESP_RST_TASK_WDT);
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|
||||||
abort();
|
abort();
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}
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}
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||||||
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|
||||||
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|
|
@ -68,6 +68,7 @@ extern "C" {
|
||||||
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
|
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
|
||||||
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
|
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
|
||||||
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
|
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
|
||||||
|
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
|
||||||
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
|
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -488,7 +488,7 @@ UT_034:
|
||||||
|
|
||||||
UT_035:
|
UT_035:
|
||||||
extends: .unit_test_template
|
extends: .unit_test_template
|
||||||
parallel: 34
|
parallel: 35
|
||||||
tags:
|
tags:
|
||||||
- ESP32S2BETA_IDF
|
- ESP32S2BETA_IDF
|
||||||
- UT_T1_1
|
- UT_T1_1
|
||||||
|
|
Loading…
Reference in a new issue