diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig
index 8019c6fef..9190fcf9c 100644
--- a/components/esp32/Kconfig
+++ b/components/esp32/Kconfig
@@ -157,6 +157,14 @@ config MEMMAP_SPIRAM_ENABLE
 
 if MEMMAP_SPIRAM_ENABLE
 
+config SPIRAM_CACHE_WORKAROUND
+    bool "Enable workaround for bug in SPI RAM cache for V1 silicon"
+    default "y"
+    help
+        V1 ESP32 silicon has a bug that can cause a write to PSRAM not to take place in some situations
+        when the cache line needs to be fetched from external RAM and an interrupt occurs. This enables a
+        fix in the compiler that makes sure the specific code that is vulnerable to this will not be emitted.
+
 choice MEMMAP_SPIRAM_TYPE
     prompt "Type of SPI RAM chip in use"
     default MEMMAP_SPIRAM_TYPE_ESPPSRAM32
diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c
index 12ecc285c..246fc6653 100644
--- a/components/esp32/cpu_start.c
+++ b/components/esp32/cpu_start.c
@@ -98,7 +98,7 @@ static const char* TAG = "cpu_start";
 #if CONFIG_FREERTOS_UNICORE
 #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
 #else
-#define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH
+#define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD
 #endif
 
 /*
diff --git a/make/project.mk b/make/project.mk
index 1c868ad30..f5276aef5 100644
--- a/make/project.mk
+++ b/make/project.mk
@@ -239,6 +239,11 @@ else
 OPTIMIZATION_FLAGS = -Og
 endif
 
+# Enable psram cache bug workaround in compiler if selected
+ifeq ("$(CONFIG_SPIRAM_CACHE_WORKAROUND)", "y")
+COMMON_FLAGS+=-mfix-esp32-psram-cache-issue
+endif
+
 # Enable generation of debugging symbols
 # (we generate even in Release mode, as this has no impact on final binary size.)
 DEBUG_FLAGS ?= -ggdb